1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Primary to Sideband (P2SB) bridge access support 4 * 5 * Copyright (c) 2017, 2021-2022 Intel Corporation. 6 * 7 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8 * Jonathan Yong <jonathan.yong@intel.com> 9 */ 10 11 #include <linux/bits.h> 12 #include <linux/export.h> 13 #include <linux/pci.h> 14 #include <linux/platform_data/x86/p2sb.h> 15 16 #include <asm/cpu_device_id.h> 17 #include <asm/intel-family.h> 18 19 #define P2SBC 0xe0 20 #define P2SBC_HIDE BIT(8) 21 22 static const struct x86_cpu_id p2sb_cpu_ids[] = { 23 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, PCI_DEVFN(13, 0)), 24 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, PCI_DEVFN(31, 1)), 25 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, PCI_DEVFN(31, 1)), 26 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, PCI_DEVFN(31, 1)), 27 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, PCI_DEVFN(31, 1)), 28 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, PCI_DEVFN(31, 1)), 29 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, PCI_DEVFN(31, 1)), 30 {} 31 }; 32 33 static int p2sb_get_devfn(unsigned int *devfn) 34 { 35 const struct x86_cpu_id *id; 36 37 id = x86_match_cpu(p2sb_cpu_ids); 38 if (!id) 39 return -ENODEV; 40 41 *devfn = (unsigned int)id->driver_data; 42 return 0; 43 } 44 45 static int p2sb_read_bar0(struct pci_dev *pdev, struct resource *mem) 46 { 47 /* Copy resource from the first BAR of the device in question */ 48 *mem = pdev->resource[0]; 49 return 0; 50 } 51 52 static int p2sb_scan_and_read(struct pci_bus *bus, unsigned int devfn, struct resource *mem) 53 { 54 struct pci_dev *pdev; 55 int ret; 56 57 pdev = pci_scan_single_device(bus, devfn); 58 if (!pdev) 59 return -ENODEV; 60 61 ret = p2sb_read_bar0(pdev, mem); 62 63 pci_stop_and_remove_bus_device(pdev); 64 return ret; 65 } 66 67 /** 68 * p2sb_bar - Get Primary to Sideband (P2SB) bridge device BAR 69 * @bus: PCI bus to communicate with 70 * @devfn: PCI slot and function to communicate with 71 * @mem: memory resource to be filled in 72 * 73 * The BIOS prevents the P2SB device from being enumerated by the PCI 74 * subsystem, so we need to unhide and hide it back to lookup the BAR. 75 * 76 * if @bus is NULL, the bus 0 in domain 0 will be used. 77 * If @devfn is 0, it will be replaced by devfn of the P2SB device. 78 * 79 * Caller must provide a valid pointer to @mem. 80 * 81 * Locking is handled by pci_rescan_remove_lock mutex. 82 * 83 * Return: 84 * 0 on success or appropriate errno value on error. 85 */ 86 int p2sb_bar(struct pci_bus *bus, unsigned int devfn, struct resource *mem) 87 { 88 struct pci_dev *pdev_p2sb; 89 unsigned int devfn_p2sb; 90 u32 value = P2SBC_HIDE; 91 int ret; 92 93 /* Get devfn for P2SB device itself */ 94 ret = p2sb_get_devfn(&devfn_p2sb); 95 if (ret) 96 return ret; 97 98 /* if @bus is NULL, use bus 0 in domain 0 */ 99 bus = bus ?: pci_find_bus(0, 0); 100 101 /* 102 * Prevent concurrent PCI bus scan from seeing the P2SB device and 103 * removing via sysfs while it is temporarily exposed. 104 */ 105 pci_lock_rescan_remove(); 106 107 /* Unhide the P2SB device, if needed */ 108 pci_bus_read_config_dword(bus, devfn_p2sb, P2SBC, &value); 109 if (value & P2SBC_HIDE) 110 pci_bus_write_config_dword(bus, devfn_p2sb, P2SBC, 0); 111 112 pdev_p2sb = pci_scan_single_device(bus, devfn_p2sb); 113 if (devfn) 114 ret = p2sb_scan_and_read(bus, devfn, mem); 115 else 116 ret = p2sb_read_bar0(pdev_p2sb, mem); 117 pci_stop_and_remove_bus_device(pdev_p2sb); 118 119 /* Hide the P2SB device, if it was hidden */ 120 if (value & P2SBC_HIDE) 121 pci_bus_write_config_dword(bus, devfn_p2sb, P2SBC, P2SBC_HIDE); 122 123 pci_unlock_rescan_remove(); 124 125 if (ret) 126 return ret; 127 128 if (mem->flags == 0) 129 return -ENODEV; 130 131 return 0; 132 } 133 EXPORT_SYMBOL_GPL(p2sb_bar); 134