1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* 3 * Mellanox platform driver 4 * 5 * Copyright (C) 2016-2018 Mellanox Technologies 6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com> 7 */ 8 9 #include <linux/device.h> 10 #include <linux/dmi.h> 11 #include <linux/i2c.h> 12 #include <linux/i2c-mux.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/platform_data/i2c-mux-reg.h> 17 #include <linux/platform_data/mlxreg.h> 18 #include <linux/regmap.h> 19 20 #define MLX_PLAT_DEVICE_NAME "mlxplat" 21 22 /* LPC bus IO offsets */ 23 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000 24 #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500 25 #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00 26 #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01 27 #define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02 28 #define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03 29 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04 30 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06 31 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08 32 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a 33 #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d 34 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e 35 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f 36 #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20 37 #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21 38 #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22 39 #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23 40 #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 41 #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a 42 #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b 43 #define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e 44 #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 45 #define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31 46 #define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32 47 #define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33 48 #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 49 #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a 50 #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b 51 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 52 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 53 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 54 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 55 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 56 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 57 #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 58 #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 59 #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 60 #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 61 #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 62 #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a 63 #define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 64 #define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 65 #define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 66 #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 67 #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 68 #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a 69 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 70 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8 71 #define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9 72 #define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb 73 #define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd 74 #define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce 75 #define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf 76 #define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1 77 #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 78 #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 79 #define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde 80 #define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf 81 #define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 82 #define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1 83 #define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2 84 #define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3 85 #define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4 86 #define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5 87 #define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6 88 #define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7 89 #define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8 90 #define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9 91 #define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb 92 #define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec 93 #define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed 94 #define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee 95 #define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef 96 #define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0 97 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5 98 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6 99 #define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7 100 #define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8 101 #define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9 102 #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb 103 #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc 104 #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 105 #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb 106 #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda 107 #define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc 108 109 #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL 110 #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 111 MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \ 112 MLXPLAT_CPLD_LPC_PIO_OFFSET) 113 #define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 114 MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \ 115 MLXPLAT_CPLD_LPC_PIO_OFFSET) 116 #define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 117 MLXPLAT_CPLD_LPC_I2C_CH3_OFF) | \ 118 MLXPLAT_CPLD_LPC_PIO_OFFSET) 119 120 /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ 121 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04 122 #define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08 123 #define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08 124 #define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40 125 #define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 126 MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \ 127 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF) 128 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01 129 #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04 130 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) 131 #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 132 #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) 133 #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) 134 #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) 135 #define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) 136 #define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0) 137 #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) 138 #define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) 139 #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(5, 0) 140 #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) 141 #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) 142 #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) 143 #define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 144 #define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) 145 146 /* Masks for aggregation for comex carriers */ 147 #define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1) 148 #define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 149 MLXPLAT_CPLD_AGGR_MASK_CARRIER) 150 #define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1 151 152 /* Default I2C parent bus number */ 153 #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 154 155 /* Maximum number of possible physical buses equipped on system */ 156 #define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 157 #define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 158 159 /* Number of channels in group */ 160 #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 161 162 /* Start channel numbers */ 163 #define MLXPLAT_CPLD_CH1 2 164 #define MLXPLAT_CPLD_CH2 10 165 #define MLXPLAT_CPLD_CH3 18 166 167 /* Number of LPC attached MUX platform devices */ 168 #define MLXPLAT_CPLD_LPC_MUX_DEVS 3 169 170 /* Hotplug devices adapter numbers */ 171 #define MLXPLAT_CPLD_NR_NONE -1 172 #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 173 #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 174 #define MLXPLAT_CPLD_PSU_MSNXXXX_NR2 3 175 #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 176 #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 177 #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 178 #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 179 180 /* Masks and default values for watchdogs */ 181 #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1) 182 #define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1)) 183 184 #define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4) 185 #define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0 186 #define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1) 187 #define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4)) 188 #define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7)) 189 #define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30 190 #define MLXPLAT_CPLD_WD_MAX_DEVS 2 191 192 /* mlxplat_priv - platform private data 193 * @pdev_i2c - i2c controller platform device 194 * @pdev_mux - array of mux platform devices 195 * @pdev_hotplug - hotplug platform devices 196 * @pdev_led - led platform devices 197 * @pdev_io_regs - register access platform devices 198 * @pdev_fan - FAN platform devices 199 * @pdev_wd - array of watchdog platform devices 200 * @regmap: device register map 201 */ 202 struct mlxplat_priv { 203 struct platform_device *pdev_i2c; 204 struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS]; 205 struct platform_device *pdev_hotplug; 206 struct platform_device *pdev_led; 207 struct platform_device *pdev_io_regs; 208 struct platform_device *pdev_fan; 209 struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; 210 void *regmap; 211 }; 212 213 /* Regions for LPC I2C controller and LPC base register space */ 214 static const struct resource mlxplat_lpc_resources[] = { 215 [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR, 216 MLXPLAT_CPLD_LPC_IO_RANGE, 217 "mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO), 218 [1] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR, 219 MLXPLAT_CPLD_LPC_IO_RANGE, 220 "mlxplat_cpld_lpc_regs", 221 IORESOURCE_IO), 222 }; 223 224 /* Platform i2c next generation systems data */ 225 static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = { 226 { 227 .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 228 .mask = MLXPLAT_CPLD_I2C_CAP_MASK, 229 .bit = MLXPLAT_CPLD_I2C_CAP_BIT, 230 }, 231 }; 232 233 static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = { 234 { 235 .data = mlxplat_mlxcpld_i2c_ng_items_data, 236 }, 237 }; 238 239 /* Platform next generation systems i2c data */ 240 static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = { 241 .items = mlxplat_mlxcpld_i2c_ng_items, 242 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 243 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 244 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET, 245 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C, 246 }; 247 248 /* Platform default channels */ 249 static const int mlxplat_default_channels[][MLXPLAT_CPLD_GRP_CHNL_NUM] = { 250 { 251 MLXPLAT_CPLD_CH1, MLXPLAT_CPLD_CH1 + 1, MLXPLAT_CPLD_CH1 + 2, 252 MLXPLAT_CPLD_CH1 + 3, MLXPLAT_CPLD_CH1 + 4, MLXPLAT_CPLD_CH1 + 253 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7 254 }, 255 { 256 MLXPLAT_CPLD_CH2, MLXPLAT_CPLD_CH2 + 1, MLXPLAT_CPLD_CH2 + 2, 257 MLXPLAT_CPLD_CH2 + 3, MLXPLAT_CPLD_CH2 + 4, MLXPLAT_CPLD_CH2 + 258 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7 259 }, 260 }; 261 262 /* Platform channels for MSN21xx system family */ 263 static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 }; 264 265 /* Platform mux data */ 266 static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { 267 { 268 .parent = 1, 269 .base_nr = MLXPLAT_CPLD_CH1, 270 .write_only = 1, 271 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 272 .reg_size = 1, 273 .idle_in_use = 1, 274 }, 275 { 276 .parent = 1, 277 .base_nr = MLXPLAT_CPLD_CH2, 278 .write_only = 1, 279 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 280 .reg_size = 1, 281 .idle_in_use = 1, 282 }, 283 284 }; 285 286 /* Platform mux configuration variables */ 287 static int mlxplat_max_adap_num; 288 static int mlxplat_mux_num; 289 static struct i2c_mux_reg_platform_data *mlxplat_mux_data; 290 291 /* Platform extended mux data */ 292 static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = { 293 { 294 .parent = 1, 295 .base_nr = MLXPLAT_CPLD_CH1, 296 .write_only = 1, 297 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 298 .reg_size = 1, 299 .idle_in_use = 1, 300 }, 301 { 302 .parent = 1, 303 .base_nr = MLXPLAT_CPLD_CH2, 304 .write_only = 1, 305 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 306 .reg_size = 1, 307 .idle_in_use = 1, 308 }, 309 { 310 .parent = 1, 311 .base_nr = MLXPLAT_CPLD_CH3, 312 .write_only = 1, 313 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 314 .reg_size = 1, 315 .idle_in_use = 1, 316 }, 317 318 }; 319 320 /* Platform hotplug devices */ 321 static struct i2c_board_info mlxplat_mlxcpld_psu[] = { 322 { 323 I2C_BOARD_INFO("24c02", 0x51), 324 }, 325 { 326 I2C_BOARD_INFO("24c02", 0x50), 327 }, 328 }; 329 330 static struct i2c_board_info mlxplat_mlxcpld_ng_psu[] = { 331 { 332 I2C_BOARD_INFO("24c32", 0x51), 333 }, 334 { 335 I2C_BOARD_INFO("24c32", 0x50), 336 }, 337 }; 338 339 static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { 340 { 341 I2C_BOARD_INFO("dps460", 0x59), 342 }, 343 { 344 I2C_BOARD_INFO("dps460", 0x58), 345 }, 346 }; 347 348 static struct i2c_board_info mlxplat_mlxcpld_fan[] = { 349 { 350 I2C_BOARD_INFO("24c32", 0x50), 351 }, 352 { 353 I2C_BOARD_INFO("24c32", 0x50), 354 }, 355 { 356 I2C_BOARD_INFO("24c32", 0x50), 357 }, 358 { 359 I2C_BOARD_INFO("24c32", 0x50), 360 }, 361 }; 362 363 /* Platform hotplug comex carrier system family data */ 364 static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = { 365 { 366 .label = "psu1", 367 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 368 .mask = BIT(0), 369 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 370 }, 371 { 372 .label = "psu2", 373 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 374 .mask = BIT(1), 375 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 376 }, 377 }; 378 379 /* Platform hotplug default data */ 380 static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = { 381 { 382 .label = "psu1", 383 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 384 .mask = BIT(0), 385 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[0], 386 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 387 }, 388 { 389 .label = "psu2", 390 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 391 .mask = BIT(1), 392 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[1], 393 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 394 }, 395 }; 396 397 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = { 398 { 399 .label = "pwr1", 400 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 401 .mask = BIT(0), 402 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 403 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 404 }, 405 { 406 .label = "pwr2", 407 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 408 .mask = BIT(1), 409 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 410 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 411 }, 412 }; 413 414 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = { 415 { 416 .label = "fan1", 417 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 418 .mask = BIT(0), 419 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0], 420 .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR, 421 }, 422 { 423 .label = "fan2", 424 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 425 .mask = BIT(1), 426 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1], 427 .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR, 428 }, 429 { 430 .label = "fan3", 431 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 432 .mask = BIT(2), 433 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2], 434 .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR, 435 }, 436 { 437 .label = "fan4", 438 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 439 .mask = BIT(3), 440 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3], 441 .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR, 442 }, 443 }; 444 445 static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = { 446 { 447 .label = "asic1", 448 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 449 .mask = MLXPLAT_CPLD_ASIC_MASK, 450 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 451 }, 452 }; 453 454 static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = { 455 { 456 .data = mlxplat_mlxcpld_default_psu_items_data, 457 .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF, 458 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 459 .mask = MLXPLAT_CPLD_PSU_MASK, 460 .count = ARRAY_SIZE(mlxplat_mlxcpld_psu), 461 .inversed = 1, 462 .health = false, 463 }, 464 { 465 .data = mlxplat_mlxcpld_default_pwr_items_data, 466 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 467 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 468 .mask = MLXPLAT_CPLD_PWR_MASK, 469 .count = ARRAY_SIZE(mlxplat_mlxcpld_pwr), 470 .inversed = 0, 471 .health = false, 472 }, 473 { 474 .data = mlxplat_mlxcpld_default_fan_items_data, 475 .aggr_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF, 476 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 477 .mask = MLXPLAT_CPLD_FAN_MASK, 478 .count = ARRAY_SIZE(mlxplat_mlxcpld_fan), 479 .inversed = 1, 480 .health = false, 481 }, 482 { 483 .data = mlxplat_mlxcpld_default_asic_items_data, 484 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 485 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 486 .mask = MLXPLAT_CPLD_ASIC_MASK, 487 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 488 .inversed = 0, 489 .health = true, 490 }, 491 }; 492 493 static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = { 494 { 495 .data = mlxplat_mlxcpld_comex_psu_items_data, 496 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 497 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 498 .mask = MLXPLAT_CPLD_PSU_MASK, 499 .count = ARRAY_SIZE(mlxplat_mlxcpld_psu), 500 .inversed = 1, 501 .health = false, 502 }, 503 { 504 .data = mlxplat_mlxcpld_default_pwr_items_data, 505 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 506 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 507 .mask = MLXPLAT_CPLD_PWR_MASK, 508 .count = ARRAY_SIZE(mlxplat_mlxcpld_pwr), 509 .inversed = 0, 510 .health = false, 511 }, 512 { 513 .data = mlxplat_mlxcpld_default_fan_items_data, 514 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 515 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 516 .mask = MLXPLAT_CPLD_FAN_MASK, 517 .count = ARRAY_SIZE(mlxplat_mlxcpld_fan), 518 .inversed = 1, 519 .health = false, 520 }, 521 { 522 .data = mlxplat_mlxcpld_default_asic_items_data, 523 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 524 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 525 .mask = MLXPLAT_CPLD_ASIC_MASK, 526 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 527 .inversed = 0, 528 .health = true, 529 }, 530 }; 531 532 static 533 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = { 534 .items = mlxplat_mlxcpld_default_items, 535 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_items), 536 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 537 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 538 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 539 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 540 }; 541 542 static 543 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = { 544 .items = mlxplat_mlxcpld_comex_items, 545 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_items), 546 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 547 .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF, 548 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET, 549 .mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK, 550 }; 551 552 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = { 553 { 554 .label = "pwr1", 555 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 556 .mask = BIT(0), 557 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 558 }, 559 { 560 .label = "pwr2", 561 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 562 .mask = BIT(1), 563 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 564 }, 565 }; 566 567 /* Platform hotplug MSN21xx system family data */ 568 static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = { 569 { 570 .data = mlxplat_mlxcpld_msn21xx_pwr_items_data, 571 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 572 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 573 .mask = MLXPLAT_CPLD_PWR_MASK, 574 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data), 575 .inversed = 0, 576 .health = false, 577 }, 578 { 579 .data = mlxplat_mlxcpld_default_asic_items_data, 580 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 581 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 582 .mask = MLXPLAT_CPLD_ASIC_MASK, 583 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 584 .inversed = 0, 585 .health = true, 586 }, 587 }; 588 589 static 590 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = { 591 .items = mlxplat_mlxcpld_msn21xx_items, 592 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items), 593 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 594 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 595 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 596 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 597 }; 598 599 /* Platform hotplug msn274x system family data */ 600 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = { 601 { 602 .label = "psu1", 603 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 604 .mask = BIT(0), 605 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[0], 606 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 607 }, 608 { 609 .label = "psu2", 610 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 611 .mask = BIT(1), 612 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[1], 613 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 614 }, 615 }; 616 617 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = { 618 { 619 .label = "pwr1", 620 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 621 .mask = BIT(0), 622 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 623 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 624 }, 625 { 626 .label = "pwr2", 627 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 628 .mask = BIT(1), 629 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 630 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 631 }, 632 }; 633 634 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = { 635 { 636 .label = "fan1", 637 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 638 .mask = BIT(0), 639 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 640 }, 641 { 642 .label = "fan2", 643 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 644 .mask = BIT(1), 645 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 646 }, 647 { 648 .label = "fan3", 649 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 650 .mask = BIT(2), 651 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 652 }, 653 { 654 .label = "fan4", 655 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 656 .mask = BIT(3), 657 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 658 }, 659 }; 660 661 static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = { 662 { 663 .data = mlxplat_mlxcpld_msn274x_psu_items_data, 664 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 665 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 666 .mask = MLXPLAT_CPLD_PSU_MASK, 667 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_psu_items_data), 668 .inversed = 1, 669 .health = false, 670 }, 671 { 672 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 673 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 674 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 675 .mask = MLXPLAT_CPLD_PWR_MASK, 676 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 677 .inversed = 0, 678 .health = false, 679 }, 680 { 681 .data = mlxplat_mlxcpld_msn274x_fan_items_data, 682 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 683 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 684 .mask = MLXPLAT_CPLD_FAN_MASK, 685 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_fan_items_data), 686 .inversed = 1, 687 .health = false, 688 }, 689 { 690 .data = mlxplat_mlxcpld_default_asic_items_data, 691 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 692 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 693 .mask = MLXPLAT_CPLD_ASIC_MASK, 694 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 695 .inversed = 0, 696 .health = true, 697 }, 698 }; 699 700 static 701 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = { 702 .items = mlxplat_mlxcpld_msn274x_items, 703 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items), 704 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 705 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 706 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 707 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 708 }; 709 710 /* Platform hotplug MSN201x system family data */ 711 static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = { 712 { 713 .label = "pwr1", 714 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 715 .mask = BIT(0), 716 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 717 }, 718 { 719 .label = "pwr2", 720 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 721 .mask = BIT(1), 722 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 723 }, 724 }; 725 726 static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = { 727 { 728 .data = mlxplat_mlxcpld_msn201x_pwr_items_data, 729 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 730 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 731 .mask = MLXPLAT_CPLD_PWR_MASK, 732 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_pwr_items_data), 733 .inversed = 0, 734 .health = false, 735 }, 736 { 737 .data = mlxplat_mlxcpld_default_asic_items_data, 738 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 739 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 740 .mask = MLXPLAT_CPLD_ASIC_MASK, 741 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 742 .inversed = 0, 743 .health = true, 744 }, 745 }; 746 747 static 748 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = { 749 .items = mlxplat_mlxcpld_msn201x_items, 750 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items), 751 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 752 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 753 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 754 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 755 }; 756 757 /* Platform hotplug next generation system family data */ 758 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = { 759 { 760 .label = "psu1", 761 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 762 .mask = BIT(0), 763 .hpdev.brdinfo = &mlxplat_mlxcpld_ng_psu[0], 764 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 765 }, 766 { 767 .label = "psu2", 768 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 769 .mask = BIT(1), 770 .hpdev.brdinfo = &mlxplat_mlxcpld_ng_psu[1], 771 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 772 }, 773 }; 774 775 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = { 776 { 777 .label = "fan1", 778 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 779 .mask = BIT(0), 780 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 781 .bit = BIT(0), 782 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 783 }, 784 { 785 .label = "fan2", 786 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 787 .mask = BIT(1), 788 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 789 .bit = BIT(1), 790 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 791 }, 792 { 793 .label = "fan3", 794 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 795 .mask = BIT(2), 796 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 797 .bit = BIT(2), 798 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 799 }, 800 { 801 .label = "fan4", 802 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 803 .mask = BIT(3), 804 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 805 .bit = BIT(3), 806 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 807 }, 808 { 809 .label = "fan5", 810 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 811 .mask = BIT(4), 812 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 813 .bit = BIT(4), 814 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 815 }, 816 { 817 .label = "fan6", 818 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 819 .mask = BIT(5), 820 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 821 .bit = BIT(5), 822 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 823 }, 824 }; 825 826 static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = { 827 { 828 .data = mlxplat_mlxcpld_default_ng_psu_items_data, 829 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 830 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 831 .mask = MLXPLAT_CPLD_PSU_MASK, 832 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), 833 .inversed = 1, 834 .health = false, 835 }, 836 { 837 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 838 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 839 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 840 .mask = MLXPLAT_CPLD_PWR_MASK, 841 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 842 .inversed = 0, 843 .health = false, 844 }, 845 { 846 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 847 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 848 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 849 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 850 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 851 .inversed = 1, 852 .health = false, 853 }, 854 { 855 .data = mlxplat_mlxcpld_default_asic_items_data, 856 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 857 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 858 .mask = MLXPLAT_CPLD_ASIC_MASK, 859 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 860 .inversed = 0, 861 .health = true, 862 }, 863 }; 864 865 static 866 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = { 867 .items = mlxplat_mlxcpld_default_ng_items, 868 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items), 869 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 870 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 871 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 872 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 873 }; 874 875 /* Platform hotplug extended system family data */ 876 static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = { 877 { 878 .label = "psu1", 879 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 880 .mask = BIT(0), 881 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 882 }, 883 { 884 .label = "psu2", 885 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 886 .mask = BIT(1), 887 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 888 }, 889 { 890 .label = "psu3", 891 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 892 .mask = BIT(2), 893 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 894 }, 895 { 896 .label = "psu4", 897 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 898 .mask = BIT(3), 899 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 900 }, 901 }; 902 903 static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = { 904 { 905 .label = "pwr1", 906 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 907 .mask = BIT(0), 908 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 909 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 910 }, 911 { 912 .label = "pwr2", 913 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 914 .mask = BIT(1), 915 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 916 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 917 }, 918 { 919 .label = "pwr3", 920 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 921 .mask = BIT(2), 922 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 923 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR2, 924 }, 925 { 926 .label = "pwr4", 927 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 928 .mask = BIT(3), 929 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 930 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR2, 931 }, 932 }; 933 934 static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { 935 { 936 .data = mlxplat_mlxcpld_ext_psu_items_data, 937 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 938 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 939 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 940 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 941 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 942 .inversed = 1, 943 .health = false, 944 }, 945 { 946 .data = mlxplat_mlxcpld_ext_pwr_items_data, 947 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 948 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 949 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 950 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 951 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 952 .inversed = 0, 953 .health = false, 954 }, 955 { 956 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 957 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 958 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 959 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 960 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 961 .inversed = 1, 962 .health = false, 963 }, 964 { 965 .data = mlxplat_mlxcpld_default_asic_items_data, 966 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 967 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 968 .mask = MLXPLAT_CPLD_ASIC_MASK, 969 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 970 .inversed = 0, 971 .health = true, 972 }, 973 }; 974 975 static 976 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { 977 .items = mlxplat_mlxcpld_ext_items, 978 .counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_items), 979 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 980 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 981 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 982 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 983 }; 984 985 /* Platform led default data */ 986 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { 987 { 988 .label = "status:green", 989 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 990 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 991 }, 992 { 993 .label = "status:red", 994 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 995 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 996 }, 997 { 998 .label = "psu:green", 999 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1000 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1001 }, 1002 { 1003 .label = "psu:red", 1004 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1005 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1006 }, 1007 { 1008 .label = "fan1:green", 1009 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1010 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1011 }, 1012 { 1013 .label = "fan1:red", 1014 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1015 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1016 }, 1017 { 1018 .label = "fan2:green", 1019 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1020 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1021 }, 1022 { 1023 .label = "fan2:red", 1024 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1025 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1026 }, 1027 { 1028 .label = "fan3:green", 1029 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1030 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1031 }, 1032 { 1033 .label = "fan3:red", 1034 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1035 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1036 }, 1037 { 1038 .label = "fan4:green", 1039 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1040 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1041 }, 1042 { 1043 .label = "fan4:red", 1044 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1045 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1046 }, 1047 }; 1048 1049 static struct mlxreg_core_platform_data mlxplat_default_led_data = { 1050 .data = mlxplat_mlxcpld_default_led_data, 1051 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data), 1052 }; 1053 1054 /* Platform led MSN21xx system family data */ 1055 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { 1056 { 1057 .label = "status:green", 1058 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1059 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1060 }, 1061 { 1062 .label = "status:red", 1063 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1064 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 1065 }, 1066 { 1067 .label = "fan:green", 1068 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1069 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1070 }, 1071 { 1072 .label = "fan:red", 1073 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1074 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1075 }, 1076 { 1077 .label = "psu1:green", 1078 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1079 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1080 }, 1081 { 1082 .label = "psu1:red", 1083 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1084 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1085 }, 1086 { 1087 .label = "psu2:green", 1088 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1089 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1090 }, 1091 { 1092 .label = "psu2:red", 1093 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1094 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1095 }, 1096 { 1097 .label = "uid:blue", 1098 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 1099 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1100 }, 1101 }; 1102 1103 static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = { 1104 .data = mlxplat_mlxcpld_msn21xx_led_data, 1105 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data), 1106 }; 1107 1108 /* Platform led for default data for 200GbE systems */ 1109 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { 1110 { 1111 .label = "status:green", 1112 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1113 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1114 }, 1115 { 1116 .label = "status:orange", 1117 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1118 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 1119 }, 1120 { 1121 .label = "psu:green", 1122 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1123 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1124 }, 1125 { 1126 .label = "psu:orange", 1127 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1128 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1129 }, 1130 { 1131 .label = "fan1:green", 1132 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1133 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1134 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1135 .bit = BIT(0), 1136 }, 1137 { 1138 .label = "fan1:orange", 1139 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1140 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1141 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1142 .bit = BIT(0), 1143 }, 1144 { 1145 .label = "fan2:green", 1146 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1147 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1148 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1149 .bit = BIT(1), 1150 }, 1151 { 1152 .label = "fan2:orange", 1153 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1154 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1155 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1156 .bit = BIT(1), 1157 }, 1158 { 1159 .label = "fan3:green", 1160 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1161 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1162 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1163 .bit = BIT(2), 1164 }, 1165 { 1166 .label = "fan3:orange", 1167 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1168 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1169 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1170 .bit = BIT(2), 1171 }, 1172 { 1173 .label = "fan4:green", 1174 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1175 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1176 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1177 .bit = BIT(3), 1178 }, 1179 { 1180 .label = "fan4:orange", 1181 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1182 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1183 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1184 .bit = BIT(3), 1185 }, 1186 { 1187 .label = "fan5:green", 1188 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1189 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1190 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1191 .bit = BIT(4), 1192 }, 1193 { 1194 .label = "fan5:orange", 1195 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1196 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1197 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1198 .bit = BIT(4), 1199 }, 1200 { 1201 .label = "fan6:green", 1202 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1203 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1204 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1205 .bit = BIT(5), 1206 }, 1207 { 1208 .label = "fan6:orange", 1209 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1210 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1211 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1212 .bit = BIT(5), 1213 }, 1214 { 1215 .label = "uid:blue", 1216 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 1217 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1218 }, 1219 }; 1220 1221 static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = { 1222 .data = mlxplat_mlxcpld_default_ng_led_data, 1223 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data), 1224 }; 1225 1226 /* Platform led for Comex based 100GbE systems */ 1227 static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = { 1228 { 1229 .label = "status:green", 1230 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1231 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1232 }, 1233 { 1234 .label = "status:red", 1235 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1236 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 1237 }, 1238 { 1239 .label = "psu:green", 1240 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1241 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1242 }, 1243 { 1244 .label = "psu:red", 1245 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1246 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1247 }, 1248 { 1249 .label = "fan1:green", 1250 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1251 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1252 }, 1253 { 1254 .label = "fan1:red", 1255 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1256 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1257 }, 1258 { 1259 .label = "fan2:green", 1260 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1261 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1262 }, 1263 { 1264 .label = "fan2:red", 1265 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1266 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1267 }, 1268 { 1269 .label = "fan3:green", 1270 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1271 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1272 }, 1273 { 1274 .label = "fan3:red", 1275 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1276 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1277 }, 1278 { 1279 .label = "fan4:green", 1280 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1281 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1282 }, 1283 { 1284 .label = "fan4:red", 1285 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1286 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1287 }, 1288 { 1289 .label = "uid:blue", 1290 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 1291 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1292 }, 1293 }; 1294 1295 static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = { 1296 .data = mlxplat_mlxcpld_comex_100G_led_data, 1297 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data), 1298 }; 1299 1300 /* Platform register access default */ 1301 static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { 1302 { 1303 .label = "cpld1_version", 1304 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 1305 .bit = GENMASK(7, 0), 1306 .mode = 0444, 1307 }, 1308 { 1309 .label = "cpld2_version", 1310 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 1311 .bit = GENMASK(7, 0), 1312 .mode = 0444, 1313 }, 1314 { 1315 .label = "cpld1_pn", 1316 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 1317 .bit = GENMASK(15, 0), 1318 .mode = 0444, 1319 .regnum = 2, 1320 }, 1321 { 1322 .label = "cpld2_pn", 1323 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 1324 .bit = GENMASK(15, 0), 1325 .mode = 0444, 1326 .regnum = 2, 1327 }, 1328 { 1329 .label = "cpld1_version_min", 1330 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 1331 .bit = GENMASK(7, 0), 1332 .mode = 0444, 1333 }, 1334 { 1335 .label = "cpld2_version_min", 1336 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 1337 .bit = GENMASK(7, 0), 1338 .mode = 0444, 1339 }, 1340 { 1341 .label = "reset_long_pb", 1342 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1343 .mask = GENMASK(7, 0) & ~BIT(0), 1344 .mode = 0444, 1345 }, 1346 { 1347 .label = "reset_short_pb", 1348 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1349 .mask = GENMASK(7, 0) & ~BIT(1), 1350 .mode = 0444, 1351 }, 1352 { 1353 .label = "reset_aux_pwr_or_ref", 1354 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1355 .mask = GENMASK(7, 0) & ~BIT(2), 1356 .mode = 0444, 1357 }, 1358 { 1359 .label = "reset_main_pwr_fail", 1360 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1361 .mask = GENMASK(7, 0) & ~BIT(3), 1362 .mode = 0444, 1363 }, 1364 { 1365 .label = "reset_sw_reset", 1366 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1367 .mask = GENMASK(7, 0) & ~BIT(4), 1368 .mode = 0444, 1369 }, 1370 { 1371 .label = "reset_fw_reset", 1372 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1373 .mask = GENMASK(7, 0) & ~BIT(5), 1374 .mode = 0444, 1375 }, 1376 { 1377 .label = "reset_hotswap_or_wd", 1378 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1379 .mask = GENMASK(7, 0) & ~BIT(6), 1380 .mode = 0444, 1381 }, 1382 { 1383 .label = "reset_asic_thermal", 1384 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1385 .mask = GENMASK(7, 0) & ~BIT(7), 1386 .mode = 0444, 1387 }, 1388 { 1389 .label = "psu1_on", 1390 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1391 .mask = GENMASK(7, 0) & ~BIT(0), 1392 .mode = 0200, 1393 }, 1394 { 1395 .label = "psu2_on", 1396 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1397 .mask = GENMASK(7, 0) & ~BIT(1), 1398 .mode = 0200, 1399 }, 1400 { 1401 .label = "pwr_cycle", 1402 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1403 .mask = GENMASK(7, 0) & ~BIT(2), 1404 .mode = 0200, 1405 }, 1406 { 1407 .label = "pwr_down", 1408 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1409 .mask = GENMASK(7, 0) & ~BIT(3), 1410 .mode = 0200, 1411 }, 1412 { 1413 .label = "select_iio", 1414 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 1415 .mask = GENMASK(7, 0) & ~BIT(6), 1416 .mode = 0644, 1417 }, 1418 { 1419 .label = "asic_health", 1420 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1421 .mask = MLXPLAT_CPLD_ASIC_MASK, 1422 .bit = 1, 1423 .mode = 0444, 1424 }, 1425 }; 1426 1427 static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = { 1428 .data = mlxplat_mlxcpld_default_regs_io_data, 1429 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data), 1430 }; 1431 1432 /* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ 1433 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { 1434 { 1435 .label = "cpld1_version", 1436 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 1437 .bit = GENMASK(7, 0), 1438 .mode = 0444, 1439 }, 1440 { 1441 .label = "cpld2_version", 1442 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 1443 .bit = GENMASK(7, 0), 1444 .mode = 0444, 1445 }, 1446 { 1447 .label = "cpld1_pn", 1448 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 1449 .bit = GENMASK(15, 0), 1450 .mode = 0444, 1451 .regnum = 2, 1452 }, 1453 { 1454 .label = "cpld2_pn", 1455 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 1456 .bit = GENMASK(15, 0), 1457 .mode = 0444, 1458 .regnum = 2, 1459 }, 1460 { 1461 .label = "cpld1_version_min", 1462 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 1463 .bit = GENMASK(7, 0), 1464 .mode = 0444, 1465 }, 1466 { 1467 .label = "cpld2_version_min", 1468 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 1469 .bit = GENMASK(7, 0), 1470 .mode = 0444, 1471 }, 1472 { 1473 .label = "reset_long_pb", 1474 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1475 .mask = GENMASK(7, 0) & ~BIT(0), 1476 .mode = 0444, 1477 }, 1478 { 1479 .label = "reset_short_pb", 1480 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1481 .mask = GENMASK(7, 0) & ~BIT(1), 1482 .mode = 0444, 1483 }, 1484 { 1485 .label = "reset_aux_pwr_or_ref", 1486 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1487 .mask = GENMASK(7, 0) & ~BIT(2), 1488 .mode = 0444, 1489 }, 1490 { 1491 .label = "reset_sw_reset", 1492 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1493 .mask = GENMASK(7, 0) & ~BIT(3), 1494 .mode = 0444, 1495 }, 1496 { 1497 .label = "reset_main_pwr_fail", 1498 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1499 .mask = GENMASK(7, 0) & ~BIT(4), 1500 .mode = 0444, 1501 }, 1502 { 1503 .label = "reset_asic_thermal", 1504 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1505 .mask = GENMASK(7, 0) & ~BIT(5), 1506 .mode = 0444, 1507 }, 1508 { 1509 .label = "reset_hotswap_or_halt", 1510 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1511 .mask = GENMASK(7, 0) & ~BIT(6), 1512 .mode = 0444, 1513 }, 1514 { 1515 .label = "reset_sff_wd", 1516 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1517 .mask = GENMASK(7, 0) & ~BIT(6), 1518 .mode = 0444, 1519 }, 1520 { 1521 .label = "psu1_on", 1522 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1523 .mask = GENMASK(7, 0) & ~BIT(0), 1524 .mode = 0200, 1525 }, 1526 { 1527 .label = "psu2_on", 1528 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1529 .mask = GENMASK(7, 0) & ~BIT(1), 1530 .mode = 0200, 1531 }, 1532 { 1533 .label = "pwr_cycle", 1534 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1535 .mask = GENMASK(7, 0) & ~BIT(2), 1536 .mode = 0200, 1537 }, 1538 { 1539 .label = "pwr_down", 1540 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1541 .mask = GENMASK(7, 0) & ~BIT(3), 1542 .mode = 0200, 1543 }, 1544 { 1545 .label = "select_iio", 1546 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 1547 .mask = GENMASK(7, 0) & ~BIT(6), 1548 .mode = 0644, 1549 }, 1550 { 1551 .label = "asic_health", 1552 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1553 .mask = MLXPLAT_CPLD_ASIC_MASK, 1554 .bit = 1, 1555 .mode = 0444, 1556 }, 1557 }; 1558 1559 static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = { 1560 .data = mlxplat_mlxcpld_msn21xx_regs_io_data, 1561 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data), 1562 }; 1563 1564 /* Platform register access for next generation systems families data */ 1565 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 1566 { 1567 .label = "cpld1_version", 1568 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 1569 .bit = GENMASK(7, 0), 1570 .mode = 0444, 1571 }, 1572 { 1573 .label = "cpld2_version", 1574 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 1575 .bit = GENMASK(7, 0), 1576 .mode = 0444, 1577 }, 1578 { 1579 .label = "cpld3_version", 1580 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 1581 .bit = GENMASK(7, 0), 1582 .mode = 0444, 1583 }, 1584 { 1585 .label = "cpld4_version", 1586 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 1587 .bit = GENMASK(7, 0), 1588 .mode = 0444, 1589 }, 1590 { 1591 .label = "cpld1_pn", 1592 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 1593 .bit = GENMASK(15, 0), 1594 .mode = 0444, 1595 .regnum = 2, 1596 }, 1597 { 1598 .label = "cpld2_pn", 1599 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 1600 .bit = GENMASK(15, 0), 1601 .mode = 0444, 1602 .regnum = 2, 1603 }, 1604 { 1605 .label = "cpld3_pn", 1606 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 1607 .bit = GENMASK(15, 0), 1608 .mode = 0444, 1609 .regnum = 2, 1610 }, 1611 { 1612 .label = "cpld4_pn", 1613 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 1614 .bit = GENMASK(15, 0), 1615 .mode = 0444, 1616 .regnum = 2, 1617 }, 1618 { 1619 .label = "cpld1_version_min", 1620 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 1621 .bit = GENMASK(7, 0), 1622 .mode = 0444, 1623 }, 1624 { 1625 .label = "cpld2_version_min", 1626 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 1627 .bit = GENMASK(7, 0), 1628 .mode = 0444, 1629 }, 1630 { 1631 .label = "cpld3_version_min", 1632 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 1633 .bit = GENMASK(7, 0), 1634 .mode = 0444, 1635 }, 1636 { 1637 .label = "cpld4_version_min", 1638 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 1639 .bit = GENMASK(7, 0), 1640 .mode = 0444, 1641 }, 1642 { 1643 .label = "reset_long_pb", 1644 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1645 .mask = GENMASK(7, 0) & ~BIT(0), 1646 .mode = 0444, 1647 }, 1648 { 1649 .label = "reset_short_pb", 1650 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1651 .mask = GENMASK(7, 0) & ~BIT(1), 1652 .mode = 0444, 1653 }, 1654 { 1655 .label = "reset_aux_pwr_or_ref", 1656 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1657 .mask = GENMASK(7, 0) & ~BIT(2), 1658 .mode = 0444, 1659 }, 1660 { 1661 .label = "reset_from_comex", 1662 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1663 .mask = GENMASK(7, 0) & ~BIT(4), 1664 .mode = 0444, 1665 }, 1666 { 1667 .label = "reset_from_asic", 1668 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1669 .mask = GENMASK(7, 0) & ~BIT(5), 1670 .mode = 0444, 1671 }, 1672 { 1673 .label = "reset_swb_wd", 1674 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1675 .mask = GENMASK(7, 0) & ~BIT(6), 1676 .mode = 0444, 1677 }, 1678 { 1679 .label = "reset_asic_thermal", 1680 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1681 .mask = GENMASK(7, 0) & ~BIT(7), 1682 .mode = 0444, 1683 }, 1684 { 1685 .label = "reset_comex_pwr_fail", 1686 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1687 .mask = GENMASK(7, 0) & ~BIT(3), 1688 .mode = 0444, 1689 }, 1690 { 1691 .label = "reset_platform", 1692 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1693 .mask = GENMASK(7, 0) & ~BIT(4), 1694 .mode = 0444, 1695 }, 1696 { 1697 .label = "reset_soc", 1698 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1699 .mask = GENMASK(7, 0) & ~BIT(5), 1700 .mode = 0444, 1701 }, 1702 { 1703 .label = "reset_comex_wd", 1704 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1705 .mask = GENMASK(7, 0) & ~BIT(6), 1706 .mode = 0444, 1707 }, 1708 { 1709 .label = "reset_voltmon_upgrade_fail", 1710 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1711 .mask = GENMASK(7, 0) & ~BIT(0), 1712 .mode = 0444, 1713 }, 1714 { 1715 .label = "reset_system", 1716 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1717 .mask = GENMASK(7, 0) & ~BIT(1), 1718 .mode = 0444, 1719 }, 1720 { 1721 .label = "reset_sw_pwr_off", 1722 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1723 .mask = GENMASK(7, 0) & ~BIT(2), 1724 .mode = 0444, 1725 }, 1726 { 1727 .label = "reset_comex_thermal", 1728 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1729 .mask = GENMASK(7, 0) & ~BIT(3), 1730 .mode = 0444, 1731 }, 1732 { 1733 .label = "reset_reload_bios", 1734 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1735 .mask = GENMASK(7, 0) & ~BIT(5), 1736 .mode = 0444, 1737 }, 1738 { 1739 .label = "reset_ac_pwr_fail", 1740 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1741 .mask = GENMASK(7, 0) & ~BIT(6), 1742 .mode = 0444, 1743 }, 1744 { 1745 .label = "psu1_on", 1746 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1747 .mask = GENMASK(7, 0) & ~BIT(0), 1748 .mode = 0200, 1749 }, 1750 { 1751 .label = "psu2_on", 1752 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1753 .mask = GENMASK(7, 0) & ~BIT(1), 1754 .mode = 0200, 1755 }, 1756 { 1757 .label = "pwr_cycle", 1758 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1759 .mask = GENMASK(7, 0) & ~BIT(2), 1760 .mode = 0200, 1761 }, 1762 { 1763 .label = "pwr_down", 1764 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1765 .mask = GENMASK(7, 0) & ~BIT(3), 1766 .mode = 0200, 1767 }, 1768 { 1769 .label = "jtag_enable", 1770 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 1771 .mask = GENMASK(7, 0) & ~BIT(4), 1772 .mode = 0644, 1773 }, 1774 { 1775 .label = "asic_health", 1776 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1777 .mask = MLXPLAT_CPLD_ASIC_MASK, 1778 .bit = 1, 1779 .mode = 0444, 1780 }, 1781 { 1782 .label = "fan_dir", 1783 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 1784 .bit = GENMASK(7, 0), 1785 .mode = 0444, 1786 }, 1787 { 1788 .label = "voltreg_update_status", 1789 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 1790 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 1791 .bit = 5, 1792 .mode = 0444, 1793 }, 1794 { 1795 .label = "vpd_wp", 1796 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 1797 .mask = GENMASK(7, 0) & ~BIT(3), 1798 .mode = 0644, 1799 }, 1800 { 1801 .label = "pcie_asic_reset_dis", 1802 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 1803 .mask = GENMASK(7, 0) & ~BIT(4), 1804 .mode = 0644, 1805 }, 1806 { 1807 .label = "config1", 1808 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 1809 .bit = GENMASK(7, 0), 1810 .mode = 0444, 1811 }, 1812 { 1813 .label = "config2", 1814 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 1815 .bit = GENMASK(7, 0), 1816 .mode = 0444, 1817 }, 1818 { 1819 .label = "ufm_version", 1820 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 1821 .bit = GENMASK(7, 0), 1822 .mode = 0444, 1823 }, 1824 }; 1825 1826 static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { 1827 .data = mlxplat_mlxcpld_default_ng_regs_io_data, 1828 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), 1829 }; 1830 1831 /* Platform FAN default */ 1832 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { 1833 { 1834 .label = "pwm1", 1835 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, 1836 }, 1837 { 1838 .label = "tacho1", 1839 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, 1840 .mask = GENMASK(7, 0), 1841 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1842 .bit = BIT(0), 1843 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1844 1845 }, 1846 { 1847 .label = "tacho2", 1848 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, 1849 .mask = GENMASK(7, 0), 1850 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1851 .bit = BIT(1), 1852 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1853 }, 1854 { 1855 .label = "tacho3", 1856 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, 1857 .mask = GENMASK(7, 0), 1858 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1859 .bit = BIT(2), 1860 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1861 }, 1862 { 1863 .label = "tacho4", 1864 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, 1865 .mask = GENMASK(7, 0), 1866 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1867 .bit = BIT(3), 1868 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1869 }, 1870 { 1871 .label = "tacho5", 1872 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, 1873 .mask = GENMASK(7, 0), 1874 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1875 .bit = BIT(4), 1876 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1877 }, 1878 { 1879 .label = "tacho6", 1880 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, 1881 .mask = GENMASK(7, 0), 1882 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1883 .bit = BIT(5), 1884 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1885 }, 1886 { 1887 .label = "tacho7", 1888 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, 1889 .mask = GENMASK(7, 0), 1890 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1891 .bit = BIT(6), 1892 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1893 }, 1894 { 1895 .label = "tacho8", 1896 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, 1897 .mask = GENMASK(7, 0), 1898 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1899 .bit = BIT(7), 1900 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1901 }, 1902 { 1903 .label = "tacho9", 1904 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, 1905 .mask = GENMASK(7, 0), 1906 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 1907 .bit = BIT(0), 1908 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1909 }, 1910 { 1911 .label = "tacho10", 1912 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, 1913 .mask = GENMASK(7, 0), 1914 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 1915 .bit = BIT(1), 1916 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1917 }, 1918 { 1919 .label = "tacho11", 1920 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, 1921 .mask = GENMASK(7, 0), 1922 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 1923 .bit = BIT(2), 1924 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1925 }, 1926 { 1927 .label = "tacho12", 1928 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, 1929 .mask = GENMASK(7, 0), 1930 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 1931 .bit = BIT(3), 1932 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1933 }, 1934 { 1935 .label = "conf", 1936 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, 1937 }, 1938 }; 1939 1940 static struct mlxreg_core_platform_data mlxplat_default_fan_data = { 1941 .data = mlxplat_mlxcpld_default_fan_data, 1942 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data), 1943 }; 1944 1945 /* Watchdog type1: hardware implementation version1 1946 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). 1947 */ 1948 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = { 1949 { 1950 .label = "action", 1951 .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 1952 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 1953 .bit = 0, 1954 }, 1955 { 1956 .label = "timeout", 1957 .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET, 1958 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 1959 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 1960 }, 1961 { 1962 .label = "ping", 1963 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 1964 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 1965 .bit = 0, 1966 }, 1967 { 1968 .label = "reset", 1969 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1970 .mask = GENMASK(7, 0) & ~BIT(6), 1971 .bit = 6, 1972 }, 1973 }; 1974 1975 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = { 1976 { 1977 .label = "action", 1978 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 1979 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 1980 .bit = 4, 1981 }, 1982 { 1983 .label = "timeout", 1984 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 1985 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 1986 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 1987 }, 1988 { 1989 .label = "ping", 1990 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 1991 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 1992 .bit = 1, 1993 }, 1994 }; 1995 1996 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = { 1997 { 1998 .data = mlxplat_mlxcpld_wd_main_regs_type1, 1999 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1), 2000 .version = MLX_WDT_TYPE1, 2001 .identity = "mlx-wdt-main", 2002 }, 2003 { 2004 .data = mlxplat_mlxcpld_wd_aux_regs_type1, 2005 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1), 2006 .version = MLX_WDT_TYPE1, 2007 .identity = "mlx-wdt-aux", 2008 }, 2009 }; 2010 2011 /* Watchdog type2: hardware implementation version 2 2012 * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140). 2013 */ 2014 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = { 2015 { 2016 .label = "action", 2017 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 2018 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 2019 .bit = 0, 2020 }, 2021 { 2022 .label = "timeout", 2023 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 2024 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2025 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 2026 }, 2027 { 2028 .label = "timeleft", 2029 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET, 2030 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2031 }, 2032 { 2033 .label = "ping", 2034 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 2035 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 2036 .bit = 0, 2037 }, 2038 { 2039 .label = "reset", 2040 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2041 .mask = GENMASK(7, 0) & ~BIT(6), 2042 .bit = 6, 2043 }, 2044 }; 2045 2046 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = { 2047 { 2048 .label = "action", 2049 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 2050 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 2051 .bit = 4, 2052 }, 2053 { 2054 .label = "timeout", 2055 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 2056 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2057 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 2058 }, 2059 { 2060 .label = "timeleft", 2061 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET, 2062 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2063 }, 2064 { 2065 .label = "ping", 2066 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 2067 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 2068 .bit = 4, 2069 }, 2070 }; 2071 2072 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = { 2073 { 2074 .data = mlxplat_mlxcpld_wd_main_regs_type2, 2075 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2), 2076 .version = MLX_WDT_TYPE2, 2077 .identity = "mlx-wdt-main", 2078 }, 2079 { 2080 .data = mlxplat_mlxcpld_wd_aux_regs_type2, 2081 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2), 2082 .version = MLX_WDT_TYPE2, 2083 .identity = "mlx-wdt-aux", 2084 }, 2085 }; 2086 2087 static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) 2088 { 2089 switch (reg) { 2090 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 2091 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 2092 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 2093 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 2094 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 2095 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 2096 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 2097 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 2098 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 2099 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 2100 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 2101 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 2102 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 2103 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 2104 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 2105 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 2106 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 2107 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 2108 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 2109 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 2110 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 2111 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 2112 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 2113 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 2114 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 2115 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 2116 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 2117 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 2118 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 2119 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 2120 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 2121 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 2122 return true; 2123 } 2124 return false; 2125 } 2126 2127 static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) 2128 { 2129 switch (reg) { 2130 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 2131 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 2132 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 2133 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 2134 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 2135 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 2136 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 2137 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 2138 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 2139 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 2140 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 2141 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 2142 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 2143 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 2144 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 2145 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 2146 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 2147 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 2148 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 2149 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 2150 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 2151 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 2152 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 2153 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 2154 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 2155 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 2156 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 2157 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 2158 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 2159 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 2160 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 2161 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 2162 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 2163 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 2164 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 2165 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 2166 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 2167 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 2168 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 2169 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 2170 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 2171 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 2172 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 2173 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 2174 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 2175 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 2176 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 2177 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 2178 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 2179 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 2180 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 2181 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 2182 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 2183 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 2184 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 2185 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 2186 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 2187 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 2188 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 2189 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 2190 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 2191 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 2192 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 2193 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 2194 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 2195 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 2196 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 2197 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 2198 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 2199 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 2200 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 2201 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 2202 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 2203 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 2204 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 2205 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 2206 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 2207 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 2208 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 2209 return true; 2210 } 2211 return false; 2212 } 2213 2214 static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) 2215 { 2216 switch (reg) { 2217 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 2218 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 2219 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 2220 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 2221 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 2222 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 2223 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 2224 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 2225 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 2226 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 2227 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 2228 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 2229 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 2230 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 2231 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 2232 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 2233 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 2234 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 2235 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 2236 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 2237 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 2238 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 2239 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 2240 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 2241 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 2242 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 2243 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 2244 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 2245 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 2246 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 2247 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 2248 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 2249 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 2250 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 2251 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 2252 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 2253 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 2254 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 2255 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 2256 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 2257 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 2258 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 2259 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 2260 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 2261 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 2262 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 2263 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 2264 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 2265 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 2266 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 2267 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 2268 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 2269 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 2270 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 2271 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 2272 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 2273 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 2274 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 2275 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 2276 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 2277 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 2278 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 2279 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 2280 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 2281 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 2282 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 2283 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 2284 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 2285 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 2286 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 2287 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 2288 return true; 2289 } 2290 return false; 2291 } 2292 2293 static const struct reg_default mlxplat_mlxcpld_regmap_default[] = { 2294 { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 }, 2295 { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 }, 2296 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 2297 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 2298 }; 2299 2300 static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = { 2301 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 2302 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 2303 }; 2304 2305 static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = { 2306 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, 2307 MLXPLAT_CPLD_LOW_AGGRCX_MASK }, 2308 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 2309 }; 2310 2311 static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { 2312 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 2313 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 2314 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 2315 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 2316 }; 2317 2318 struct mlxplat_mlxcpld_regmap_context { 2319 void __iomem *base; 2320 }; 2321 2322 static struct mlxplat_mlxcpld_regmap_context mlxplat_mlxcpld_regmap_ctx; 2323 2324 static int 2325 mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val) 2326 { 2327 struct mlxplat_mlxcpld_regmap_context *ctx = context; 2328 2329 *val = ioread8(ctx->base + reg); 2330 return 0; 2331 } 2332 2333 static int 2334 mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val) 2335 { 2336 struct mlxplat_mlxcpld_regmap_context *ctx = context; 2337 2338 iowrite8(val, ctx->base + reg); 2339 return 0; 2340 } 2341 2342 static const struct regmap_config mlxplat_mlxcpld_regmap_config = { 2343 .reg_bits = 8, 2344 .val_bits = 8, 2345 .max_register = 255, 2346 .cache_type = REGCACHE_FLAT, 2347 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 2348 .readable_reg = mlxplat_mlxcpld_readable_reg, 2349 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 2350 .reg_defaults = mlxplat_mlxcpld_regmap_default, 2351 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default), 2352 .reg_read = mlxplat_mlxcpld_reg_read, 2353 .reg_write = mlxplat_mlxcpld_reg_write, 2354 }; 2355 2356 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = { 2357 .reg_bits = 8, 2358 .val_bits = 8, 2359 .max_register = 255, 2360 .cache_type = REGCACHE_FLAT, 2361 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 2362 .readable_reg = mlxplat_mlxcpld_readable_reg, 2363 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 2364 .reg_defaults = mlxplat_mlxcpld_regmap_ng, 2365 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng), 2366 .reg_read = mlxplat_mlxcpld_reg_read, 2367 .reg_write = mlxplat_mlxcpld_reg_write, 2368 }; 2369 2370 static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = { 2371 .reg_bits = 8, 2372 .val_bits = 8, 2373 .max_register = 255, 2374 .cache_type = REGCACHE_FLAT, 2375 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 2376 .readable_reg = mlxplat_mlxcpld_readable_reg, 2377 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 2378 .reg_defaults = mlxplat_mlxcpld_regmap_comex_default, 2379 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default), 2380 .reg_read = mlxplat_mlxcpld_reg_read, 2381 .reg_write = mlxplat_mlxcpld_reg_write, 2382 }; 2383 2384 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = { 2385 .reg_bits = 8, 2386 .val_bits = 8, 2387 .max_register = 255, 2388 .cache_type = REGCACHE_FLAT, 2389 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 2390 .readable_reg = mlxplat_mlxcpld_readable_reg, 2391 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 2392 .reg_defaults = mlxplat_mlxcpld_regmap_ng400, 2393 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400), 2394 .reg_read = mlxplat_mlxcpld_reg_read, 2395 .reg_write = mlxplat_mlxcpld_reg_write, 2396 }; 2397 2398 static struct resource mlxplat_mlxcpld_resources[] = { 2399 [0] = DEFINE_RES_IRQ_NAMED(17, "mlxreg-hotplug"), 2400 }; 2401 2402 static struct platform_device *mlxplat_dev; 2403 static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c; 2404 static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug; 2405 static struct mlxreg_core_platform_data *mlxplat_led; 2406 static struct mlxreg_core_platform_data *mlxplat_regs_io; 2407 static struct mlxreg_core_platform_data *mlxplat_fan; 2408 static struct mlxreg_core_platform_data 2409 *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; 2410 static const struct regmap_config *mlxplat_regmap_config; 2411 2412 static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) 2413 { 2414 int i; 2415 2416 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2417 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2418 mlxplat_mux_data = mlxplat_default_mux_data; 2419 for (i = 0; i < mlxplat_mux_num; i++) { 2420 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 2421 mlxplat_mux_data[i].n_values = 2422 ARRAY_SIZE(mlxplat_default_channels[i]); 2423 } 2424 mlxplat_hotplug = &mlxplat_mlxcpld_default_data; 2425 mlxplat_hotplug->deferred_nr = 2426 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2427 mlxplat_led = &mlxplat_default_led_data; 2428 mlxplat_regs_io = &mlxplat_default_regs_io_data; 2429 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 2430 2431 return 1; 2432 } 2433 2434 static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) 2435 { 2436 int i; 2437 2438 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2439 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2440 mlxplat_mux_data = mlxplat_default_mux_data; 2441 for (i = 0; i < mlxplat_mux_num; i++) { 2442 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2443 mlxplat_mux_data[i].n_values = 2444 ARRAY_SIZE(mlxplat_msn21xx_channels); 2445 } 2446 mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data; 2447 mlxplat_hotplug->deferred_nr = 2448 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2449 mlxplat_led = &mlxplat_msn21xx_led_data; 2450 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 2451 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 2452 2453 return 1; 2454 } 2455 2456 static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) 2457 { 2458 int i; 2459 2460 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2461 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2462 mlxplat_mux_data = mlxplat_default_mux_data; 2463 for (i = 0; i < mlxplat_mux_num; i++) { 2464 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2465 mlxplat_mux_data[i].n_values = 2466 ARRAY_SIZE(mlxplat_msn21xx_channels); 2467 } 2468 mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data; 2469 mlxplat_hotplug->deferred_nr = 2470 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2471 mlxplat_led = &mlxplat_default_led_data; 2472 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 2473 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 2474 2475 return 1; 2476 } 2477 2478 static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) 2479 { 2480 int i; 2481 2482 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2483 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2484 mlxplat_mux_data = mlxplat_default_mux_data; 2485 for (i = 0; i < mlxplat_mux_num; i++) { 2486 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2487 mlxplat_mux_data[i].n_values = 2488 ARRAY_SIZE(mlxplat_msn21xx_channels); 2489 } 2490 mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data; 2491 mlxplat_hotplug->deferred_nr = 2492 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2493 mlxplat_led = &mlxplat_msn21xx_led_data; 2494 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 2495 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 2496 2497 return 1; 2498 } 2499 2500 static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi) 2501 { 2502 int i; 2503 2504 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2505 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2506 mlxplat_mux_data = mlxplat_default_mux_data; 2507 for (i = 0; i < mlxplat_mux_num; i++) { 2508 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2509 mlxplat_mux_data[i].n_values = 2510 ARRAY_SIZE(mlxplat_msn21xx_channels); 2511 } 2512 mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data; 2513 mlxplat_hotplug->deferred_nr = 2514 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2515 mlxplat_led = &mlxplat_default_ng_led_data; 2516 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 2517 mlxplat_fan = &mlxplat_default_fan_data; 2518 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 2519 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 2520 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 2521 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 2522 2523 return 1; 2524 } 2525 2526 static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) 2527 { 2528 int i; 2529 2530 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 2531 mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data); 2532 mlxplat_mux_data = mlxplat_extended_mux_data; 2533 for (i = 0; i < mlxplat_mux_num; i++) { 2534 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2535 mlxplat_mux_data[i].n_values = 2536 ARRAY_SIZE(mlxplat_msn21xx_channels); 2537 } 2538 mlxplat_hotplug = &mlxplat_mlxcpld_comex_data; 2539 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 2540 mlxplat_led = &mlxplat_comex_100G_led_data; 2541 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 2542 mlxplat_fan = &mlxplat_default_fan_data; 2543 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 2544 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 2545 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex; 2546 2547 return 1; 2548 } 2549 2550 static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) 2551 { 2552 int i; 2553 2554 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2555 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2556 mlxplat_mux_data = mlxplat_default_mux_data; 2557 for (i = 0; i < mlxplat_mux_num; i++) { 2558 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2559 mlxplat_mux_data[i].n_values = 2560 ARRAY_SIZE(mlxplat_msn21xx_channels); 2561 } 2562 mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; 2563 mlxplat_hotplug->deferred_nr = 2564 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2565 mlxplat_led = &mlxplat_default_ng_led_data; 2566 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 2567 mlxplat_fan = &mlxplat_default_fan_data; 2568 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 2569 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 2570 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 2571 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 2572 2573 return 1; 2574 } 2575 2576 static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { 2577 { 2578 .callback = mlxplat_dmi_default_matched, 2579 .matches = { 2580 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 2581 }, 2582 }, 2583 { 2584 .callback = mlxplat_dmi_msn21xx_matched, 2585 .matches = { 2586 DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"), 2587 }, 2588 }, 2589 { 2590 .callback = mlxplat_dmi_msn274x_matched, 2591 .matches = { 2592 DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"), 2593 }, 2594 }, 2595 { 2596 .callback = mlxplat_dmi_msn201x_matched, 2597 .matches = { 2598 DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"), 2599 }, 2600 }, 2601 { 2602 .callback = mlxplat_dmi_qmb7xx_matched, 2603 .matches = { 2604 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 2605 }, 2606 }, 2607 { 2608 .callback = mlxplat_dmi_qmb7xx_matched, 2609 .matches = { 2610 DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"), 2611 }, 2612 }, 2613 { 2614 .callback = mlxplat_dmi_comex_matched, 2615 .matches = { 2616 DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"), 2617 }, 2618 }, 2619 { 2620 .callback = mlxplat_dmi_ng400_matched, 2621 .matches = { 2622 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 2623 }, 2624 }, 2625 { 2626 .callback = mlxplat_dmi_msn274x_matched, 2627 .matches = { 2628 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2629 DMI_MATCH(DMI_PRODUCT_NAME, "MSN274"), 2630 }, 2631 }, 2632 { 2633 .callback = mlxplat_dmi_default_matched, 2634 .matches = { 2635 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2636 DMI_MATCH(DMI_PRODUCT_NAME, "MSN24"), 2637 }, 2638 }, 2639 { 2640 .callback = mlxplat_dmi_default_matched, 2641 .matches = { 2642 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2643 DMI_MATCH(DMI_PRODUCT_NAME, "MSN27"), 2644 }, 2645 }, 2646 { 2647 .callback = mlxplat_dmi_default_matched, 2648 .matches = { 2649 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2650 DMI_MATCH(DMI_PRODUCT_NAME, "MSB"), 2651 }, 2652 }, 2653 { 2654 .callback = mlxplat_dmi_default_matched, 2655 .matches = { 2656 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2657 DMI_MATCH(DMI_PRODUCT_NAME, "MSX"), 2658 }, 2659 }, 2660 { 2661 .callback = mlxplat_dmi_msn21xx_matched, 2662 .matches = { 2663 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2664 DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"), 2665 }, 2666 }, 2667 { 2668 .callback = mlxplat_dmi_msn201x_matched, 2669 .matches = { 2670 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2671 DMI_MATCH(DMI_PRODUCT_NAME, "MSN201"), 2672 }, 2673 }, 2674 { 2675 .callback = mlxplat_dmi_qmb7xx_matched, 2676 .matches = { 2677 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2678 DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"), 2679 }, 2680 }, 2681 { 2682 .callback = mlxplat_dmi_qmb7xx_matched, 2683 .matches = { 2684 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2685 DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"), 2686 }, 2687 }, 2688 { 2689 .callback = mlxplat_dmi_qmb7xx_matched, 2690 .matches = { 2691 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2692 DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"), 2693 }, 2694 }, 2695 { 2696 .callback = mlxplat_dmi_qmb7xx_matched, 2697 .matches = { 2698 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2699 DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"), 2700 }, 2701 }, 2702 { } 2703 }; 2704 2705 MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table); 2706 2707 static int mlxplat_mlxcpld_verify_bus_topology(int *nr) 2708 { 2709 struct i2c_adapter *search_adap; 2710 int shift, i; 2711 2712 /* Scan adapters from expected id to verify it is free. */ 2713 *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; 2714 for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i < 2715 mlxplat_max_adap_num; i++) { 2716 search_adap = i2c_get_adapter(i); 2717 if (search_adap) { 2718 i2c_put_adapter(search_adap); 2719 continue; 2720 } 2721 2722 /* Return if expected parent adapter is free. */ 2723 if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR) 2724 return 0; 2725 break; 2726 } 2727 2728 /* Return with error if free id for adapter is not found. */ 2729 if (i == mlxplat_max_adap_num) 2730 return -ENODEV; 2731 2732 /* Shift adapter ids, since expected parent adapter is not free. */ 2733 *nr = i; 2734 for (i = 0; i < mlxplat_mux_num; i++) { 2735 shift = *nr - mlxplat_mux_data[i].parent; 2736 mlxplat_mux_data[i].parent = *nr; 2737 mlxplat_mux_data[i].base_nr += shift; 2738 if (shift > 0) 2739 mlxplat_hotplug->shift_nr = shift; 2740 } 2741 2742 return 0; 2743 } 2744 2745 static int __init mlxplat_init(void) 2746 { 2747 struct mlxplat_priv *priv; 2748 int i, j, nr, err; 2749 2750 if (!dmi_check_system(mlxplat_dmi_table)) 2751 return -ENODEV; 2752 2753 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1, 2754 mlxplat_lpc_resources, 2755 ARRAY_SIZE(mlxplat_lpc_resources)); 2756 2757 if (IS_ERR(mlxplat_dev)) 2758 return PTR_ERR(mlxplat_dev); 2759 2760 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), 2761 GFP_KERNEL); 2762 if (!priv) { 2763 err = -ENOMEM; 2764 goto fail_alloc; 2765 } 2766 platform_set_drvdata(mlxplat_dev, priv); 2767 2768 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, 2769 mlxplat_lpc_resources[1].start, 1); 2770 if (!mlxplat_mlxcpld_regmap_ctx.base) { 2771 err = -ENOMEM; 2772 goto fail_alloc; 2773 } 2774 2775 if (!mlxplat_regmap_config) 2776 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; 2777 2778 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, 2779 &mlxplat_mlxcpld_regmap_ctx, 2780 mlxplat_regmap_config); 2781 if (IS_ERR(priv->regmap)) { 2782 err = PTR_ERR(priv->regmap); 2783 goto fail_alloc; 2784 } 2785 2786 err = mlxplat_mlxcpld_verify_bus_topology(&nr); 2787 if (nr < 0) 2788 goto fail_alloc; 2789 2790 nr = (nr == mlxplat_max_adap_num) ? -1 : nr; 2791 if (mlxplat_i2c) 2792 mlxplat_i2c->regmap = priv->regmap; 2793 priv->pdev_i2c = platform_device_register_resndata( 2794 &mlxplat_dev->dev, "i2c_mlxcpld", 2795 nr, mlxplat_mlxcpld_resources, 2796 ARRAY_SIZE(mlxplat_mlxcpld_resources), 2797 mlxplat_i2c, sizeof(*mlxplat_i2c)); 2798 if (IS_ERR(priv->pdev_i2c)) { 2799 err = PTR_ERR(priv->pdev_i2c); 2800 goto fail_alloc; 2801 } 2802 2803 for (i = 0; i < mlxplat_mux_num; i++) { 2804 priv->pdev_mux[i] = platform_device_register_resndata( 2805 &priv->pdev_i2c->dev, 2806 "i2c-mux-reg", i, NULL, 2807 0, &mlxplat_mux_data[i], 2808 sizeof(mlxplat_mux_data[i])); 2809 if (IS_ERR(priv->pdev_mux[i])) { 2810 err = PTR_ERR(priv->pdev_mux[i]); 2811 goto fail_platform_mux_register; 2812 } 2813 } 2814 2815 /* Add hotplug driver */ 2816 mlxplat_hotplug->regmap = priv->regmap; 2817 priv->pdev_hotplug = platform_device_register_resndata( 2818 &mlxplat_dev->dev, "mlxreg-hotplug", 2819 PLATFORM_DEVID_NONE, 2820 mlxplat_mlxcpld_resources, 2821 ARRAY_SIZE(mlxplat_mlxcpld_resources), 2822 mlxplat_hotplug, sizeof(*mlxplat_hotplug)); 2823 if (IS_ERR(priv->pdev_hotplug)) { 2824 err = PTR_ERR(priv->pdev_hotplug); 2825 goto fail_platform_mux_register; 2826 } 2827 2828 /* Set default registers. */ 2829 for (j = 0; j < mlxplat_regmap_config->num_reg_defaults; j++) { 2830 err = regmap_write(priv->regmap, 2831 mlxplat_regmap_config->reg_defaults[j].reg, 2832 mlxplat_regmap_config->reg_defaults[j].def); 2833 if (err) 2834 goto fail_platform_mux_register; 2835 } 2836 2837 /* Add LED driver. */ 2838 mlxplat_led->regmap = priv->regmap; 2839 priv->pdev_led = platform_device_register_resndata( 2840 &mlxplat_dev->dev, "leds-mlxreg", 2841 PLATFORM_DEVID_NONE, NULL, 0, 2842 mlxplat_led, sizeof(*mlxplat_led)); 2843 if (IS_ERR(priv->pdev_led)) { 2844 err = PTR_ERR(priv->pdev_led); 2845 goto fail_platform_hotplug_register; 2846 } 2847 2848 /* Add registers io access driver. */ 2849 if (mlxplat_regs_io) { 2850 mlxplat_regs_io->regmap = priv->regmap; 2851 priv->pdev_io_regs = platform_device_register_resndata( 2852 &mlxplat_dev->dev, "mlxreg-io", 2853 PLATFORM_DEVID_NONE, NULL, 0, 2854 mlxplat_regs_io, 2855 sizeof(*mlxplat_regs_io)); 2856 if (IS_ERR(priv->pdev_io_regs)) { 2857 err = PTR_ERR(priv->pdev_io_regs); 2858 goto fail_platform_led_register; 2859 } 2860 } 2861 2862 /* Add FAN driver. */ 2863 if (mlxplat_fan) { 2864 mlxplat_fan->regmap = priv->regmap; 2865 priv->pdev_fan = platform_device_register_resndata( 2866 &mlxplat_dev->dev, "mlxreg-fan", 2867 PLATFORM_DEVID_NONE, NULL, 0, 2868 mlxplat_fan, 2869 sizeof(*mlxplat_fan)); 2870 if (IS_ERR(priv->pdev_fan)) { 2871 err = PTR_ERR(priv->pdev_fan); 2872 goto fail_platform_io_regs_register; 2873 } 2874 } 2875 2876 /* Add WD drivers. */ 2877 for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) { 2878 if (mlxplat_wd_data[j]) { 2879 mlxplat_wd_data[j]->regmap = priv->regmap; 2880 priv->pdev_wd[j] = platform_device_register_resndata( 2881 &mlxplat_dev->dev, "mlx-wdt", 2882 j, NULL, 0, 2883 mlxplat_wd_data[j], 2884 sizeof(*mlxplat_wd_data[j])); 2885 if (IS_ERR(priv->pdev_wd[j])) { 2886 err = PTR_ERR(priv->pdev_wd[j]); 2887 goto fail_platform_wd_register; 2888 } 2889 } 2890 } 2891 2892 /* Sync registers with hardware. */ 2893 regcache_mark_dirty(priv->regmap); 2894 err = regcache_sync(priv->regmap); 2895 if (err) 2896 goto fail_platform_wd_register; 2897 2898 return 0; 2899 2900 fail_platform_wd_register: 2901 while (--j >= 0) 2902 platform_device_unregister(priv->pdev_wd[j]); 2903 if (mlxplat_fan) 2904 platform_device_unregister(priv->pdev_fan); 2905 fail_platform_io_regs_register: 2906 if (mlxplat_regs_io) 2907 platform_device_unregister(priv->pdev_io_regs); 2908 fail_platform_led_register: 2909 platform_device_unregister(priv->pdev_led); 2910 fail_platform_hotplug_register: 2911 platform_device_unregister(priv->pdev_hotplug); 2912 fail_platform_mux_register: 2913 while (--i >= 0) 2914 platform_device_unregister(priv->pdev_mux[i]); 2915 platform_device_unregister(priv->pdev_i2c); 2916 fail_alloc: 2917 platform_device_unregister(mlxplat_dev); 2918 2919 return err; 2920 } 2921 module_init(mlxplat_init); 2922 2923 static void __exit mlxplat_exit(void) 2924 { 2925 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 2926 int i; 2927 2928 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) 2929 platform_device_unregister(priv->pdev_wd[i]); 2930 if (priv->pdev_fan) 2931 platform_device_unregister(priv->pdev_fan); 2932 if (priv->pdev_io_regs) 2933 platform_device_unregister(priv->pdev_io_regs); 2934 platform_device_unregister(priv->pdev_led); 2935 platform_device_unregister(priv->pdev_hotplug); 2936 2937 for (i = mlxplat_mux_num - 1; i >= 0 ; i--) 2938 platform_device_unregister(priv->pdev_mux[i]); 2939 2940 platform_device_unregister(priv->pdev_i2c); 2941 platform_device_unregister(mlxplat_dev); 2942 } 2943 module_exit(mlxplat_exit); 2944 2945 MODULE_AUTHOR("Vadim Pasternak (vadimp@mellanox.com)"); 2946 MODULE_DESCRIPTION("Mellanox platform driver"); 2947 MODULE_LICENSE("Dual BSD/GPL"); 2948