1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* 3 * Mellanox platform driver 4 * 5 * Copyright (C) 2016-2018 Mellanox Technologies 6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com> 7 */ 8 9 #include <linux/device.h> 10 #include <linux/dmi.h> 11 #include <linux/i2c.h> 12 #include <linux/i2c-mux.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/platform_data/i2c-mux-reg.h> 17 #include <linux/platform_data/mlxreg.h> 18 #include <linux/regmap.h> 19 20 #define MLX_PLAT_DEVICE_NAME "mlxplat" 21 22 /* LPC bus IO offsets */ 23 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000 24 #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500 25 #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00 26 #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01 27 #define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02 28 #define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03 29 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04 30 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06 31 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08 32 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a 33 #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d 34 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e 35 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f 36 #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20 37 #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21 38 #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22 39 #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23 40 #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 41 #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a 42 #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b 43 #define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e 44 #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 45 #define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31 46 #define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32 47 #define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33 48 #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 49 #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a 50 #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b 51 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 52 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 53 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 54 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 55 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 56 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 57 #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 58 #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 59 #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 60 #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 61 #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 62 #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a 63 #define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 64 #define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 65 #define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 66 #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 67 #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 68 #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a 69 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 70 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8 71 #define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9 72 #define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb 73 #define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd 74 #define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce 75 #define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf 76 #define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1 77 #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 78 #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 79 #define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde 80 #define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf 81 #define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 82 #define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1 83 #define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2 84 #define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3 85 #define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4 86 #define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5 87 #define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6 88 #define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7 89 #define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8 90 #define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9 91 #define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb 92 #define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec 93 #define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed 94 #define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee 95 #define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef 96 #define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0 97 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5 98 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6 99 #define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7 100 #define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8 101 #define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9 102 #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb 103 #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc 104 #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 105 #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb 106 #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda 107 #define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc 108 109 #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL 110 #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 111 MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \ 112 MLXPLAT_CPLD_LPC_PIO_OFFSET) 113 #define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 114 MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \ 115 MLXPLAT_CPLD_LPC_PIO_OFFSET) 116 #define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 117 MLXPLAT_CPLD_LPC_I2C_CH3_OFF) | \ 118 MLXPLAT_CPLD_LPC_PIO_OFFSET) 119 120 /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ 121 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04 122 #define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08 123 #define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08 124 #define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40 125 #define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 126 MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \ 127 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF) 128 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01 129 #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04 130 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) 131 #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 132 #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) 133 #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) 134 #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) 135 #define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) 136 #define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0) 137 #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) 138 #define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) 139 #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(5, 0) 140 #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) 141 #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) 142 #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) 143 #define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 144 #define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) 145 146 /* Masks for aggregation for comex carriers */ 147 #define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1) 148 #define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 149 MLXPLAT_CPLD_AGGR_MASK_CARRIER) 150 #define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1 151 152 /* Default I2C parent bus number */ 153 #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 154 155 /* Maximum number of possible physical buses equipped on system */ 156 #define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 157 #define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 158 159 /* Number of channels in group */ 160 #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 161 162 /* Start channel numbers */ 163 #define MLXPLAT_CPLD_CH1 2 164 #define MLXPLAT_CPLD_CH2 10 165 #define MLXPLAT_CPLD_CH3 18 166 167 /* Number of LPC attached MUX platform devices */ 168 #define MLXPLAT_CPLD_LPC_MUX_DEVS 3 169 170 /* Hotplug devices adapter numbers */ 171 #define MLXPLAT_CPLD_NR_NONE -1 172 #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 173 #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 174 #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 175 #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 176 #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 177 #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 178 179 /* Masks and default values for watchdogs */ 180 #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1) 181 #define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1)) 182 183 #define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4) 184 #define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0 185 #define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1) 186 #define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4)) 187 #define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7)) 188 #define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6)) 189 #define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30 190 #define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600 191 #define MLXPLAT_CPLD_WD_MAX_DEVS 2 192 193 /* mlxplat_priv - platform private data 194 * @pdev_i2c - i2c controller platform device 195 * @pdev_mux - array of mux platform devices 196 * @pdev_hotplug - hotplug platform devices 197 * @pdev_led - led platform devices 198 * @pdev_io_regs - register access platform devices 199 * @pdev_fan - FAN platform devices 200 * @pdev_wd - array of watchdog platform devices 201 * @regmap: device register map 202 */ 203 struct mlxplat_priv { 204 struct platform_device *pdev_i2c; 205 struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS]; 206 struct platform_device *pdev_hotplug; 207 struct platform_device *pdev_led; 208 struct platform_device *pdev_io_regs; 209 struct platform_device *pdev_fan; 210 struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; 211 void *regmap; 212 }; 213 214 /* Regions for LPC I2C controller and LPC base register space */ 215 static const struct resource mlxplat_lpc_resources[] = { 216 [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR, 217 MLXPLAT_CPLD_LPC_IO_RANGE, 218 "mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO), 219 [1] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR, 220 MLXPLAT_CPLD_LPC_IO_RANGE, 221 "mlxplat_cpld_lpc_regs", 222 IORESOURCE_IO), 223 }; 224 225 /* Platform i2c next generation systems data */ 226 static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = { 227 { 228 .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 229 .mask = MLXPLAT_CPLD_I2C_CAP_MASK, 230 .bit = MLXPLAT_CPLD_I2C_CAP_BIT, 231 }, 232 }; 233 234 static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = { 235 { 236 .data = mlxplat_mlxcpld_i2c_ng_items_data, 237 }, 238 }; 239 240 /* Platform next generation systems i2c data */ 241 static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = { 242 .items = mlxplat_mlxcpld_i2c_ng_items, 243 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 244 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 245 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET, 246 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C, 247 }; 248 249 /* Platform default channels */ 250 static const int mlxplat_default_channels[][MLXPLAT_CPLD_GRP_CHNL_NUM] = { 251 { 252 MLXPLAT_CPLD_CH1, MLXPLAT_CPLD_CH1 + 1, MLXPLAT_CPLD_CH1 + 2, 253 MLXPLAT_CPLD_CH1 + 3, MLXPLAT_CPLD_CH1 + 4, MLXPLAT_CPLD_CH1 + 254 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7 255 }, 256 { 257 MLXPLAT_CPLD_CH2, MLXPLAT_CPLD_CH2 + 1, MLXPLAT_CPLD_CH2 + 2, 258 MLXPLAT_CPLD_CH2 + 3, MLXPLAT_CPLD_CH2 + 4, MLXPLAT_CPLD_CH2 + 259 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7 260 }, 261 }; 262 263 /* Platform channels for MSN21xx system family */ 264 static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 }; 265 266 /* Platform mux data */ 267 static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { 268 { 269 .parent = 1, 270 .base_nr = MLXPLAT_CPLD_CH1, 271 .write_only = 1, 272 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 273 .reg_size = 1, 274 .idle_in_use = 1, 275 }, 276 { 277 .parent = 1, 278 .base_nr = MLXPLAT_CPLD_CH2, 279 .write_only = 1, 280 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 281 .reg_size = 1, 282 .idle_in_use = 1, 283 }, 284 285 }; 286 287 /* Platform mux configuration variables */ 288 static int mlxplat_max_adap_num; 289 static int mlxplat_mux_num; 290 static struct i2c_mux_reg_platform_data *mlxplat_mux_data; 291 292 /* Platform extended mux data */ 293 static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = { 294 { 295 .parent = 1, 296 .base_nr = MLXPLAT_CPLD_CH1, 297 .write_only = 1, 298 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 299 .reg_size = 1, 300 .idle_in_use = 1, 301 }, 302 { 303 .parent = 1, 304 .base_nr = MLXPLAT_CPLD_CH2, 305 .write_only = 1, 306 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 307 .reg_size = 1, 308 .idle_in_use = 1, 309 }, 310 { 311 .parent = 1, 312 .base_nr = MLXPLAT_CPLD_CH3, 313 .write_only = 1, 314 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 315 .reg_size = 1, 316 .idle_in_use = 1, 317 }, 318 319 }; 320 321 /* Platform hotplug devices */ 322 static struct i2c_board_info mlxplat_mlxcpld_psu[] = { 323 { 324 I2C_BOARD_INFO("24c02", 0x51), 325 }, 326 { 327 I2C_BOARD_INFO("24c02", 0x50), 328 }, 329 }; 330 331 static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { 332 { 333 I2C_BOARD_INFO("dps460", 0x59), 334 }, 335 { 336 I2C_BOARD_INFO("dps460", 0x58), 337 }, 338 }; 339 340 static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = { 341 { 342 I2C_BOARD_INFO("dps460", 0x5b), 343 }, 344 { 345 I2C_BOARD_INFO("dps460", 0x5a), 346 }, 347 }; 348 349 static struct i2c_board_info mlxplat_mlxcpld_fan[] = { 350 { 351 I2C_BOARD_INFO("24c32", 0x50), 352 }, 353 { 354 I2C_BOARD_INFO("24c32", 0x50), 355 }, 356 { 357 I2C_BOARD_INFO("24c32", 0x50), 358 }, 359 { 360 I2C_BOARD_INFO("24c32", 0x50), 361 }, 362 }; 363 364 /* Platform hotplug comex carrier system family data */ 365 static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = { 366 { 367 .label = "psu1", 368 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 369 .mask = BIT(0), 370 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 371 }, 372 { 373 .label = "psu2", 374 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 375 .mask = BIT(1), 376 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 377 }, 378 }; 379 380 /* Platform hotplug default data */ 381 static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = { 382 { 383 .label = "psu1", 384 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 385 .mask = BIT(0), 386 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[0], 387 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 388 }, 389 { 390 .label = "psu2", 391 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 392 .mask = BIT(1), 393 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[1], 394 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 395 }, 396 }; 397 398 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = { 399 { 400 .label = "pwr1", 401 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 402 .mask = BIT(0), 403 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 404 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 405 }, 406 { 407 .label = "pwr2", 408 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 409 .mask = BIT(1), 410 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 411 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 412 }, 413 }; 414 415 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = { 416 { 417 .label = "fan1", 418 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 419 .mask = BIT(0), 420 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0], 421 .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR, 422 }, 423 { 424 .label = "fan2", 425 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 426 .mask = BIT(1), 427 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1], 428 .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR, 429 }, 430 { 431 .label = "fan3", 432 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 433 .mask = BIT(2), 434 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2], 435 .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR, 436 }, 437 { 438 .label = "fan4", 439 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 440 .mask = BIT(3), 441 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3], 442 .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR, 443 }, 444 }; 445 446 static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = { 447 { 448 .label = "asic1", 449 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 450 .mask = MLXPLAT_CPLD_ASIC_MASK, 451 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 452 }, 453 }; 454 455 static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = { 456 { 457 .data = mlxplat_mlxcpld_default_psu_items_data, 458 .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF, 459 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 460 .mask = MLXPLAT_CPLD_PSU_MASK, 461 .count = ARRAY_SIZE(mlxplat_mlxcpld_psu), 462 .inversed = 1, 463 .health = false, 464 }, 465 { 466 .data = mlxplat_mlxcpld_default_pwr_items_data, 467 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 468 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 469 .mask = MLXPLAT_CPLD_PWR_MASK, 470 .count = ARRAY_SIZE(mlxplat_mlxcpld_pwr), 471 .inversed = 0, 472 .health = false, 473 }, 474 { 475 .data = mlxplat_mlxcpld_default_fan_items_data, 476 .aggr_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF, 477 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 478 .mask = MLXPLAT_CPLD_FAN_MASK, 479 .count = ARRAY_SIZE(mlxplat_mlxcpld_fan), 480 .inversed = 1, 481 .health = false, 482 }, 483 { 484 .data = mlxplat_mlxcpld_default_asic_items_data, 485 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 486 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 487 .mask = MLXPLAT_CPLD_ASIC_MASK, 488 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 489 .inversed = 0, 490 .health = true, 491 }, 492 }; 493 494 static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = { 495 { 496 .data = mlxplat_mlxcpld_comex_psu_items_data, 497 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 498 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 499 .mask = MLXPLAT_CPLD_PSU_MASK, 500 .count = ARRAY_SIZE(mlxplat_mlxcpld_psu), 501 .inversed = 1, 502 .health = false, 503 }, 504 { 505 .data = mlxplat_mlxcpld_default_pwr_items_data, 506 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 507 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 508 .mask = MLXPLAT_CPLD_PWR_MASK, 509 .count = ARRAY_SIZE(mlxplat_mlxcpld_pwr), 510 .inversed = 0, 511 .health = false, 512 }, 513 { 514 .data = mlxplat_mlxcpld_default_fan_items_data, 515 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 516 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 517 .mask = MLXPLAT_CPLD_FAN_MASK, 518 .count = ARRAY_SIZE(mlxplat_mlxcpld_fan), 519 .inversed = 1, 520 .health = false, 521 }, 522 { 523 .data = mlxplat_mlxcpld_default_asic_items_data, 524 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 525 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 526 .mask = MLXPLAT_CPLD_ASIC_MASK, 527 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 528 .inversed = 0, 529 .health = true, 530 }, 531 }; 532 533 static 534 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = { 535 .items = mlxplat_mlxcpld_default_items, 536 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_items), 537 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 538 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 539 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 540 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 541 }; 542 543 static 544 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = { 545 .items = mlxplat_mlxcpld_comex_items, 546 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_items), 547 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 548 .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF, 549 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET, 550 .mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK, 551 }; 552 553 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = { 554 { 555 .label = "pwr1", 556 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 557 .mask = BIT(0), 558 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 559 }, 560 { 561 .label = "pwr2", 562 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 563 .mask = BIT(1), 564 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 565 }, 566 }; 567 568 /* Platform hotplug MSN21xx system family data */ 569 static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = { 570 { 571 .data = mlxplat_mlxcpld_msn21xx_pwr_items_data, 572 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 573 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 574 .mask = MLXPLAT_CPLD_PWR_MASK, 575 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data), 576 .inversed = 0, 577 .health = false, 578 }, 579 { 580 .data = mlxplat_mlxcpld_default_asic_items_data, 581 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 582 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 583 .mask = MLXPLAT_CPLD_ASIC_MASK, 584 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 585 .inversed = 0, 586 .health = true, 587 }, 588 }; 589 590 static 591 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = { 592 .items = mlxplat_mlxcpld_msn21xx_items, 593 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items), 594 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 595 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 596 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 597 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 598 }; 599 600 /* Platform hotplug msn274x system family data */ 601 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = { 602 { 603 .label = "psu1", 604 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 605 .mask = BIT(0), 606 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[0], 607 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 608 }, 609 { 610 .label = "psu2", 611 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 612 .mask = BIT(1), 613 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[1], 614 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 615 }, 616 }; 617 618 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = { 619 { 620 .label = "pwr1", 621 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 622 .mask = BIT(0), 623 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 624 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 625 }, 626 { 627 .label = "pwr2", 628 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 629 .mask = BIT(1), 630 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 631 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 632 }, 633 }; 634 635 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = { 636 { 637 .label = "fan1", 638 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 639 .mask = BIT(0), 640 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 641 }, 642 { 643 .label = "fan2", 644 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 645 .mask = BIT(1), 646 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 647 }, 648 { 649 .label = "fan3", 650 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 651 .mask = BIT(2), 652 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 653 }, 654 { 655 .label = "fan4", 656 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 657 .mask = BIT(3), 658 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 659 }, 660 }; 661 662 static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = { 663 { 664 .data = mlxplat_mlxcpld_msn274x_psu_items_data, 665 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 666 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 667 .mask = MLXPLAT_CPLD_PSU_MASK, 668 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_psu_items_data), 669 .inversed = 1, 670 .health = false, 671 }, 672 { 673 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 674 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 675 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 676 .mask = MLXPLAT_CPLD_PWR_MASK, 677 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 678 .inversed = 0, 679 .health = false, 680 }, 681 { 682 .data = mlxplat_mlxcpld_msn274x_fan_items_data, 683 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 684 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 685 .mask = MLXPLAT_CPLD_FAN_MASK, 686 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_fan_items_data), 687 .inversed = 1, 688 .health = false, 689 }, 690 { 691 .data = mlxplat_mlxcpld_default_asic_items_data, 692 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 693 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 694 .mask = MLXPLAT_CPLD_ASIC_MASK, 695 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 696 .inversed = 0, 697 .health = true, 698 }, 699 }; 700 701 static 702 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = { 703 .items = mlxplat_mlxcpld_msn274x_items, 704 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items), 705 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 706 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 707 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 708 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 709 }; 710 711 /* Platform hotplug MSN201x system family data */ 712 static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = { 713 { 714 .label = "pwr1", 715 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 716 .mask = BIT(0), 717 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 718 }, 719 { 720 .label = "pwr2", 721 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 722 .mask = BIT(1), 723 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 724 }, 725 }; 726 727 static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = { 728 { 729 .data = mlxplat_mlxcpld_msn201x_pwr_items_data, 730 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 731 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 732 .mask = MLXPLAT_CPLD_PWR_MASK, 733 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_pwr_items_data), 734 .inversed = 0, 735 .health = false, 736 }, 737 { 738 .data = mlxplat_mlxcpld_default_asic_items_data, 739 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 740 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 741 .mask = MLXPLAT_CPLD_ASIC_MASK, 742 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 743 .inversed = 0, 744 .health = true, 745 }, 746 }; 747 748 static 749 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = { 750 .items = mlxplat_mlxcpld_msn201x_items, 751 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items), 752 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 753 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 754 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 755 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 756 }; 757 758 /* Platform hotplug next generation system family data */ 759 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = { 760 { 761 .label = "psu1", 762 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 763 .mask = BIT(0), 764 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 765 }, 766 { 767 .label = "psu2", 768 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 769 .mask = BIT(1), 770 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 771 }, 772 }; 773 774 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = { 775 { 776 .label = "fan1", 777 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 778 .mask = BIT(0), 779 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 780 .bit = BIT(0), 781 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 782 }, 783 { 784 .label = "fan2", 785 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 786 .mask = BIT(1), 787 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 788 .bit = BIT(1), 789 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 790 }, 791 { 792 .label = "fan3", 793 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 794 .mask = BIT(2), 795 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 796 .bit = BIT(2), 797 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 798 }, 799 { 800 .label = "fan4", 801 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 802 .mask = BIT(3), 803 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 804 .bit = BIT(3), 805 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 806 }, 807 { 808 .label = "fan5", 809 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 810 .mask = BIT(4), 811 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 812 .bit = BIT(4), 813 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 814 }, 815 { 816 .label = "fan6", 817 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 818 .mask = BIT(5), 819 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 820 .bit = BIT(5), 821 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 822 }, 823 }; 824 825 static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = { 826 { 827 .data = mlxplat_mlxcpld_default_ng_psu_items_data, 828 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 829 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 830 .mask = MLXPLAT_CPLD_PSU_MASK, 831 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), 832 .inversed = 1, 833 .health = false, 834 }, 835 { 836 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 837 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 838 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 839 .mask = MLXPLAT_CPLD_PWR_MASK, 840 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 841 .inversed = 0, 842 .health = false, 843 }, 844 { 845 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 846 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 847 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 848 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 849 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 850 .inversed = 1, 851 .health = false, 852 }, 853 { 854 .data = mlxplat_mlxcpld_default_asic_items_data, 855 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 856 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 857 .mask = MLXPLAT_CPLD_ASIC_MASK, 858 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 859 .inversed = 0, 860 .health = true, 861 }, 862 }; 863 864 static 865 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = { 866 .items = mlxplat_mlxcpld_default_ng_items, 867 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items), 868 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 869 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 870 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 871 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 872 }; 873 874 /* Platform hotplug extended system family data */ 875 static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = { 876 { 877 .label = "psu1", 878 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 879 .mask = BIT(0), 880 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 881 }, 882 { 883 .label = "psu2", 884 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 885 .mask = BIT(1), 886 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 887 }, 888 { 889 .label = "psu3", 890 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 891 .mask = BIT(2), 892 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 893 }, 894 { 895 .label = "psu4", 896 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 897 .mask = BIT(3), 898 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 899 }, 900 }; 901 902 static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = { 903 { 904 .label = "pwr1", 905 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 906 .mask = BIT(0), 907 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 908 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 909 }, 910 { 911 .label = "pwr2", 912 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 913 .mask = BIT(1), 914 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 915 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 916 }, 917 { 918 .label = "pwr3", 919 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 920 .mask = BIT(2), 921 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 922 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 923 }, 924 { 925 .label = "pwr4", 926 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 927 .mask = BIT(3), 928 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 929 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 930 }, 931 }; 932 933 static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { 934 { 935 .data = mlxplat_mlxcpld_ext_psu_items_data, 936 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 937 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 938 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 939 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 940 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 941 .inversed = 1, 942 .health = false, 943 }, 944 { 945 .data = mlxplat_mlxcpld_ext_pwr_items_data, 946 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 947 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 948 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 949 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 950 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 951 .inversed = 0, 952 .health = false, 953 }, 954 { 955 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 956 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 957 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 958 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 959 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 960 .inversed = 1, 961 .health = false, 962 }, 963 { 964 .data = mlxplat_mlxcpld_default_asic_items_data, 965 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 966 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 967 .mask = MLXPLAT_CPLD_ASIC_MASK, 968 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 969 .inversed = 0, 970 .health = true, 971 }, 972 }; 973 974 static 975 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { 976 .items = mlxplat_mlxcpld_ext_items, 977 .counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_items), 978 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 979 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 980 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 981 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 982 }; 983 984 /* Platform led default data */ 985 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { 986 { 987 .label = "status:green", 988 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 989 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 990 }, 991 { 992 .label = "status:red", 993 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 994 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 995 }, 996 { 997 .label = "psu:green", 998 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 999 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1000 }, 1001 { 1002 .label = "psu:red", 1003 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1004 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1005 }, 1006 { 1007 .label = "fan1:green", 1008 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1009 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1010 }, 1011 { 1012 .label = "fan1:red", 1013 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1014 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1015 }, 1016 { 1017 .label = "fan2:green", 1018 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1019 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1020 }, 1021 { 1022 .label = "fan2:red", 1023 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1024 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1025 }, 1026 { 1027 .label = "fan3:green", 1028 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1029 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1030 }, 1031 { 1032 .label = "fan3:red", 1033 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1034 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1035 }, 1036 { 1037 .label = "fan4:green", 1038 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1039 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1040 }, 1041 { 1042 .label = "fan4:red", 1043 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1044 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1045 }, 1046 }; 1047 1048 static struct mlxreg_core_platform_data mlxplat_default_led_data = { 1049 .data = mlxplat_mlxcpld_default_led_data, 1050 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data), 1051 }; 1052 1053 /* Platform led MSN21xx system family data */ 1054 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { 1055 { 1056 .label = "status:green", 1057 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1058 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1059 }, 1060 { 1061 .label = "status:red", 1062 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1063 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 1064 }, 1065 { 1066 .label = "fan:green", 1067 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1068 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1069 }, 1070 { 1071 .label = "fan:red", 1072 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1073 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1074 }, 1075 { 1076 .label = "psu1:green", 1077 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1078 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1079 }, 1080 { 1081 .label = "psu1:red", 1082 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1083 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1084 }, 1085 { 1086 .label = "psu2:green", 1087 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1088 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1089 }, 1090 { 1091 .label = "psu2:red", 1092 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1093 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1094 }, 1095 { 1096 .label = "uid:blue", 1097 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 1098 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1099 }, 1100 }; 1101 1102 static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = { 1103 .data = mlxplat_mlxcpld_msn21xx_led_data, 1104 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data), 1105 }; 1106 1107 /* Platform led for default data for 200GbE systems */ 1108 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { 1109 { 1110 .label = "status:green", 1111 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1112 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1113 }, 1114 { 1115 .label = "status:orange", 1116 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1117 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 1118 }, 1119 { 1120 .label = "psu:green", 1121 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1122 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1123 }, 1124 { 1125 .label = "psu:orange", 1126 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1127 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1128 }, 1129 { 1130 .label = "fan1:green", 1131 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1132 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1133 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1134 .bit = BIT(0), 1135 }, 1136 { 1137 .label = "fan1:orange", 1138 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1139 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1140 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1141 .bit = BIT(0), 1142 }, 1143 { 1144 .label = "fan2:green", 1145 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1146 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1147 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1148 .bit = BIT(1), 1149 }, 1150 { 1151 .label = "fan2:orange", 1152 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1153 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1154 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1155 .bit = BIT(1), 1156 }, 1157 { 1158 .label = "fan3:green", 1159 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1160 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1161 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1162 .bit = BIT(2), 1163 }, 1164 { 1165 .label = "fan3:orange", 1166 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1167 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1168 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1169 .bit = BIT(2), 1170 }, 1171 { 1172 .label = "fan4:green", 1173 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1174 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1175 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1176 .bit = BIT(3), 1177 }, 1178 { 1179 .label = "fan4:orange", 1180 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1181 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1182 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1183 .bit = BIT(3), 1184 }, 1185 { 1186 .label = "fan5:green", 1187 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1188 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1189 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1190 .bit = BIT(4), 1191 }, 1192 { 1193 .label = "fan5:orange", 1194 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1195 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1196 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1197 .bit = BIT(4), 1198 }, 1199 { 1200 .label = "fan6:green", 1201 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1202 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1203 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1204 .bit = BIT(5), 1205 }, 1206 { 1207 .label = "fan6:orange", 1208 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1209 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1210 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1211 .bit = BIT(5), 1212 }, 1213 { 1214 .label = "uid:blue", 1215 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 1216 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1217 }, 1218 }; 1219 1220 static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = { 1221 .data = mlxplat_mlxcpld_default_ng_led_data, 1222 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data), 1223 }; 1224 1225 /* Platform led for Comex based 100GbE systems */ 1226 static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = { 1227 { 1228 .label = "status:green", 1229 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1230 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1231 }, 1232 { 1233 .label = "status:red", 1234 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1235 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 1236 }, 1237 { 1238 .label = "psu:green", 1239 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1240 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1241 }, 1242 { 1243 .label = "psu:red", 1244 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1245 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1246 }, 1247 { 1248 .label = "fan1:green", 1249 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1250 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1251 }, 1252 { 1253 .label = "fan1:red", 1254 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1255 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1256 }, 1257 { 1258 .label = "fan2:green", 1259 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1260 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1261 }, 1262 { 1263 .label = "fan2:red", 1264 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1265 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1266 }, 1267 { 1268 .label = "fan3:green", 1269 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1270 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1271 }, 1272 { 1273 .label = "fan3:red", 1274 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1275 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1276 }, 1277 { 1278 .label = "fan4:green", 1279 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1280 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1281 }, 1282 { 1283 .label = "fan4:red", 1284 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1285 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1286 }, 1287 { 1288 .label = "uid:blue", 1289 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 1290 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1291 }, 1292 }; 1293 1294 static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = { 1295 .data = mlxplat_mlxcpld_comex_100G_led_data, 1296 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data), 1297 }; 1298 1299 /* Platform register access default */ 1300 static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { 1301 { 1302 .label = "cpld1_version", 1303 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 1304 .bit = GENMASK(7, 0), 1305 .mode = 0444, 1306 }, 1307 { 1308 .label = "cpld2_version", 1309 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 1310 .bit = GENMASK(7, 0), 1311 .mode = 0444, 1312 }, 1313 { 1314 .label = "cpld1_pn", 1315 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 1316 .bit = GENMASK(15, 0), 1317 .mode = 0444, 1318 .regnum = 2, 1319 }, 1320 { 1321 .label = "cpld2_pn", 1322 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 1323 .bit = GENMASK(15, 0), 1324 .mode = 0444, 1325 .regnum = 2, 1326 }, 1327 { 1328 .label = "cpld1_version_min", 1329 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 1330 .bit = GENMASK(7, 0), 1331 .mode = 0444, 1332 }, 1333 { 1334 .label = "cpld2_version_min", 1335 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 1336 .bit = GENMASK(7, 0), 1337 .mode = 0444, 1338 }, 1339 { 1340 .label = "reset_long_pb", 1341 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1342 .mask = GENMASK(7, 0) & ~BIT(0), 1343 .mode = 0444, 1344 }, 1345 { 1346 .label = "reset_short_pb", 1347 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1348 .mask = GENMASK(7, 0) & ~BIT(1), 1349 .mode = 0444, 1350 }, 1351 { 1352 .label = "reset_aux_pwr_or_ref", 1353 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1354 .mask = GENMASK(7, 0) & ~BIT(2), 1355 .mode = 0444, 1356 }, 1357 { 1358 .label = "reset_main_pwr_fail", 1359 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1360 .mask = GENMASK(7, 0) & ~BIT(3), 1361 .mode = 0444, 1362 }, 1363 { 1364 .label = "reset_sw_reset", 1365 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1366 .mask = GENMASK(7, 0) & ~BIT(4), 1367 .mode = 0444, 1368 }, 1369 { 1370 .label = "reset_fw_reset", 1371 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1372 .mask = GENMASK(7, 0) & ~BIT(5), 1373 .mode = 0444, 1374 }, 1375 { 1376 .label = "reset_hotswap_or_wd", 1377 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1378 .mask = GENMASK(7, 0) & ~BIT(6), 1379 .mode = 0444, 1380 }, 1381 { 1382 .label = "reset_asic_thermal", 1383 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1384 .mask = GENMASK(7, 0) & ~BIT(7), 1385 .mode = 0444, 1386 }, 1387 { 1388 .label = "psu1_on", 1389 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1390 .mask = GENMASK(7, 0) & ~BIT(0), 1391 .mode = 0200, 1392 }, 1393 { 1394 .label = "psu2_on", 1395 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1396 .mask = GENMASK(7, 0) & ~BIT(1), 1397 .mode = 0200, 1398 }, 1399 { 1400 .label = "pwr_cycle", 1401 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1402 .mask = GENMASK(7, 0) & ~BIT(2), 1403 .mode = 0200, 1404 }, 1405 { 1406 .label = "pwr_down", 1407 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1408 .mask = GENMASK(7, 0) & ~BIT(3), 1409 .mode = 0200, 1410 }, 1411 { 1412 .label = "select_iio", 1413 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 1414 .mask = GENMASK(7, 0) & ~BIT(6), 1415 .mode = 0644, 1416 }, 1417 { 1418 .label = "asic_health", 1419 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1420 .mask = MLXPLAT_CPLD_ASIC_MASK, 1421 .bit = 1, 1422 .mode = 0444, 1423 }, 1424 }; 1425 1426 static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = { 1427 .data = mlxplat_mlxcpld_default_regs_io_data, 1428 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data), 1429 }; 1430 1431 /* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ 1432 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { 1433 { 1434 .label = "cpld1_version", 1435 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 1436 .bit = GENMASK(7, 0), 1437 .mode = 0444, 1438 }, 1439 { 1440 .label = "cpld2_version", 1441 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 1442 .bit = GENMASK(7, 0), 1443 .mode = 0444, 1444 }, 1445 { 1446 .label = "cpld1_pn", 1447 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 1448 .bit = GENMASK(15, 0), 1449 .mode = 0444, 1450 .regnum = 2, 1451 }, 1452 { 1453 .label = "cpld2_pn", 1454 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 1455 .bit = GENMASK(15, 0), 1456 .mode = 0444, 1457 .regnum = 2, 1458 }, 1459 { 1460 .label = "cpld1_version_min", 1461 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 1462 .bit = GENMASK(7, 0), 1463 .mode = 0444, 1464 }, 1465 { 1466 .label = "cpld2_version_min", 1467 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 1468 .bit = GENMASK(7, 0), 1469 .mode = 0444, 1470 }, 1471 { 1472 .label = "reset_long_pb", 1473 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1474 .mask = GENMASK(7, 0) & ~BIT(0), 1475 .mode = 0444, 1476 }, 1477 { 1478 .label = "reset_short_pb", 1479 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1480 .mask = GENMASK(7, 0) & ~BIT(1), 1481 .mode = 0444, 1482 }, 1483 { 1484 .label = "reset_aux_pwr_or_ref", 1485 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1486 .mask = GENMASK(7, 0) & ~BIT(2), 1487 .mode = 0444, 1488 }, 1489 { 1490 .label = "reset_sw_reset", 1491 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1492 .mask = GENMASK(7, 0) & ~BIT(3), 1493 .mode = 0444, 1494 }, 1495 { 1496 .label = "reset_main_pwr_fail", 1497 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1498 .mask = GENMASK(7, 0) & ~BIT(4), 1499 .mode = 0444, 1500 }, 1501 { 1502 .label = "reset_asic_thermal", 1503 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1504 .mask = GENMASK(7, 0) & ~BIT(5), 1505 .mode = 0444, 1506 }, 1507 { 1508 .label = "reset_hotswap_or_halt", 1509 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1510 .mask = GENMASK(7, 0) & ~BIT(6), 1511 .mode = 0444, 1512 }, 1513 { 1514 .label = "reset_sff_wd", 1515 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1516 .mask = GENMASK(7, 0) & ~BIT(6), 1517 .mode = 0444, 1518 }, 1519 { 1520 .label = "psu1_on", 1521 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1522 .mask = GENMASK(7, 0) & ~BIT(0), 1523 .mode = 0200, 1524 }, 1525 { 1526 .label = "psu2_on", 1527 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1528 .mask = GENMASK(7, 0) & ~BIT(1), 1529 .mode = 0200, 1530 }, 1531 { 1532 .label = "pwr_cycle", 1533 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1534 .mask = GENMASK(7, 0) & ~BIT(2), 1535 .mode = 0200, 1536 }, 1537 { 1538 .label = "pwr_down", 1539 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1540 .mask = GENMASK(7, 0) & ~BIT(3), 1541 .mode = 0200, 1542 }, 1543 { 1544 .label = "select_iio", 1545 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 1546 .mask = GENMASK(7, 0) & ~BIT(6), 1547 .mode = 0644, 1548 }, 1549 { 1550 .label = "asic_health", 1551 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1552 .mask = MLXPLAT_CPLD_ASIC_MASK, 1553 .bit = 1, 1554 .mode = 0444, 1555 }, 1556 }; 1557 1558 static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = { 1559 .data = mlxplat_mlxcpld_msn21xx_regs_io_data, 1560 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data), 1561 }; 1562 1563 /* Platform register access for next generation systems families data */ 1564 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 1565 { 1566 .label = "cpld1_version", 1567 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 1568 .bit = GENMASK(7, 0), 1569 .mode = 0444, 1570 }, 1571 { 1572 .label = "cpld2_version", 1573 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 1574 .bit = GENMASK(7, 0), 1575 .mode = 0444, 1576 }, 1577 { 1578 .label = "cpld3_version", 1579 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 1580 .bit = GENMASK(7, 0), 1581 .mode = 0444, 1582 }, 1583 { 1584 .label = "cpld4_version", 1585 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 1586 .bit = GENMASK(7, 0), 1587 .mode = 0444, 1588 }, 1589 { 1590 .label = "cpld1_pn", 1591 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 1592 .bit = GENMASK(15, 0), 1593 .mode = 0444, 1594 .regnum = 2, 1595 }, 1596 { 1597 .label = "cpld2_pn", 1598 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 1599 .bit = GENMASK(15, 0), 1600 .mode = 0444, 1601 .regnum = 2, 1602 }, 1603 { 1604 .label = "cpld3_pn", 1605 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 1606 .bit = GENMASK(15, 0), 1607 .mode = 0444, 1608 .regnum = 2, 1609 }, 1610 { 1611 .label = "cpld4_pn", 1612 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 1613 .bit = GENMASK(15, 0), 1614 .mode = 0444, 1615 .regnum = 2, 1616 }, 1617 { 1618 .label = "cpld1_version_min", 1619 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 1620 .bit = GENMASK(7, 0), 1621 .mode = 0444, 1622 }, 1623 { 1624 .label = "cpld2_version_min", 1625 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 1626 .bit = GENMASK(7, 0), 1627 .mode = 0444, 1628 }, 1629 { 1630 .label = "cpld3_version_min", 1631 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 1632 .bit = GENMASK(7, 0), 1633 .mode = 0444, 1634 }, 1635 { 1636 .label = "cpld4_version_min", 1637 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 1638 .bit = GENMASK(7, 0), 1639 .mode = 0444, 1640 }, 1641 { 1642 .label = "reset_long_pb", 1643 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1644 .mask = GENMASK(7, 0) & ~BIT(0), 1645 .mode = 0444, 1646 }, 1647 { 1648 .label = "reset_short_pb", 1649 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1650 .mask = GENMASK(7, 0) & ~BIT(1), 1651 .mode = 0444, 1652 }, 1653 { 1654 .label = "reset_aux_pwr_or_ref", 1655 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1656 .mask = GENMASK(7, 0) & ~BIT(2), 1657 .mode = 0444, 1658 }, 1659 { 1660 .label = "reset_from_comex", 1661 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1662 .mask = GENMASK(7, 0) & ~BIT(4), 1663 .mode = 0444, 1664 }, 1665 { 1666 .label = "reset_from_asic", 1667 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1668 .mask = GENMASK(7, 0) & ~BIT(5), 1669 .mode = 0444, 1670 }, 1671 { 1672 .label = "reset_swb_wd", 1673 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1674 .mask = GENMASK(7, 0) & ~BIT(6), 1675 .mode = 0444, 1676 }, 1677 { 1678 .label = "reset_asic_thermal", 1679 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1680 .mask = GENMASK(7, 0) & ~BIT(7), 1681 .mode = 0444, 1682 }, 1683 { 1684 .label = "reset_comex_pwr_fail", 1685 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1686 .mask = GENMASK(7, 0) & ~BIT(3), 1687 .mode = 0444, 1688 }, 1689 { 1690 .label = "reset_platform", 1691 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1692 .mask = GENMASK(7, 0) & ~BIT(4), 1693 .mode = 0444, 1694 }, 1695 { 1696 .label = "reset_soc", 1697 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1698 .mask = GENMASK(7, 0) & ~BIT(5), 1699 .mode = 0444, 1700 }, 1701 { 1702 .label = "reset_comex_wd", 1703 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1704 .mask = GENMASK(7, 0) & ~BIT(6), 1705 .mode = 0444, 1706 }, 1707 { 1708 .label = "reset_voltmon_upgrade_fail", 1709 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1710 .mask = GENMASK(7, 0) & ~BIT(0), 1711 .mode = 0444, 1712 }, 1713 { 1714 .label = "reset_system", 1715 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1716 .mask = GENMASK(7, 0) & ~BIT(1), 1717 .mode = 0444, 1718 }, 1719 { 1720 .label = "reset_sw_pwr_off", 1721 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1722 .mask = GENMASK(7, 0) & ~BIT(2), 1723 .mode = 0444, 1724 }, 1725 { 1726 .label = "reset_comex_thermal", 1727 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1728 .mask = GENMASK(7, 0) & ~BIT(3), 1729 .mode = 0444, 1730 }, 1731 { 1732 .label = "reset_reload_bios", 1733 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1734 .mask = GENMASK(7, 0) & ~BIT(5), 1735 .mode = 0444, 1736 }, 1737 { 1738 .label = "reset_ac_pwr_fail", 1739 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1740 .mask = GENMASK(7, 0) & ~BIT(6), 1741 .mode = 0444, 1742 }, 1743 { 1744 .label = "psu1_on", 1745 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1746 .mask = GENMASK(7, 0) & ~BIT(0), 1747 .mode = 0200, 1748 }, 1749 { 1750 .label = "psu2_on", 1751 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1752 .mask = GENMASK(7, 0) & ~BIT(1), 1753 .mode = 0200, 1754 }, 1755 { 1756 .label = "pwr_cycle", 1757 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1758 .mask = GENMASK(7, 0) & ~BIT(2), 1759 .mode = 0200, 1760 }, 1761 { 1762 .label = "pwr_down", 1763 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1764 .mask = GENMASK(7, 0) & ~BIT(3), 1765 .mode = 0200, 1766 }, 1767 { 1768 .label = "jtag_enable", 1769 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 1770 .mask = GENMASK(7, 0) & ~BIT(4), 1771 .mode = 0644, 1772 }, 1773 { 1774 .label = "asic_health", 1775 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1776 .mask = MLXPLAT_CPLD_ASIC_MASK, 1777 .bit = 1, 1778 .mode = 0444, 1779 }, 1780 { 1781 .label = "fan_dir", 1782 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 1783 .bit = GENMASK(7, 0), 1784 .mode = 0444, 1785 }, 1786 { 1787 .label = "voltreg_update_status", 1788 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 1789 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 1790 .bit = 5, 1791 .mode = 0444, 1792 }, 1793 { 1794 .label = "vpd_wp", 1795 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 1796 .mask = GENMASK(7, 0) & ~BIT(3), 1797 .mode = 0644, 1798 }, 1799 { 1800 .label = "pcie_asic_reset_dis", 1801 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 1802 .mask = GENMASK(7, 0) & ~BIT(4), 1803 .mode = 0644, 1804 }, 1805 { 1806 .label = "config1", 1807 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 1808 .bit = GENMASK(7, 0), 1809 .mode = 0444, 1810 }, 1811 { 1812 .label = "config2", 1813 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 1814 .bit = GENMASK(7, 0), 1815 .mode = 0444, 1816 }, 1817 { 1818 .label = "ufm_version", 1819 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 1820 .bit = GENMASK(7, 0), 1821 .mode = 0444, 1822 }, 1823 }; 1824 1825 static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { 1826 .data = mlxplat_mlxcpld_default_ng_regs_io_data, 1827 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), 1828 }; 1829 1830 /* Platform FAN default */ 1831 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { 1832 { 1833 .label = "pwm1", 1834 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, 1835 }, 1836 { 1837 .label = "tacho1", 1838 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, 1839 .mask = GENMASK(7, 0), 1840 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1841 .bit = BIT(0), 1842 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1843 1844 }, 1845 { 1846 .label = "tacho2", 1847 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, 1848 .mask = GENMASK(7, 0), 1849 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1850 .bit = BIT(1), 1851 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1852 }, 1853 { 1854 .label = "tacho3", 1855 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, 1856 .mask = GENMASK(7, 0), 1857 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1858 .bit = BIT(2), 1859 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1860 }, 1861 { 1862 .label = "tacho4", 1863 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, 1864 .mask = GENMASK(7, 0), 1865 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1866 .bit = BIT(3), 1867 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1868 }, 1869 { 1870 .label = "tacho5", 1871 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, 1872 .mask = GENMASK(7, 0), 1873 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1874 .bit = BIT(4), 1875 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1876 }, 1877 { 1878 .label = "tacho6", 1879 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, 1880 .mask = GENMASK(7, 0), 1881 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1882 .bit = BIT(5), 1883 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1884 }, 1885 { 1886 .label = "tacho7", 1887 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, 1888 .mask = GENMASK(7, 0), 1889 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1890 .bit = BIT(6), 1891 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1892 }, 1893 { 1894 .label = "tacho8", 1895 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, 1896 .mask = GENMASK(7, 0), 1897 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1898 .bit = BIT(7), 1899 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1900 }, 1901 { 1902 .label = "tacho9", 1903 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, 1904 .mask = GENMASK(7, 0), 1905 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 1906 .bit = BIT(0), 1907 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1908 }, 1909 { 1910 .label = "tacho10", 1911 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, 1912 .mask = GENMASK(7, 0), 1913 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 1914 .bit = BIT(1), 1915 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1916 }, 1917 { 1918 .label = "tacho11", 1919 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, 1920 .mask = GENMASK(7, 0), 1921 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 1922 .bit = BIT(2), 1923 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1924 }, 1925 { 1926 .label = "tacho12", 1927 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, 1928 .mask = GENMASK(7, 0), 1929 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 1930 .bit = BIT(3), 1931 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1932 }, 1933 { 1934 .label = "conf", 1935 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, 1936 }, 1937 }; 1938 1939 static struct mlxreg_core_platform_data mlxplat_default_fan_data = { 1940 .data = mlxplat_mlxcpld_default_fan_data, 1941 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data), 1942 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1943 }; 1944 1945 /* Watchdog type1: hardware implementation version1 1946 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). 1947 */ 1948 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = { 1949 { 1950 .label = "action", 1951 .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 1952 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 1953 .bit = 0, 1954 }, 1955 { 1956 .label = "timeout", 1957 .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET, 1958 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 1959 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 1960 }, 1961 { 1962 .label = "ping", 1963 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 1964 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 1965 .bit = 0, 1966 }, 1967 { 1968 .label = "reset", 1969 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1970 .mask = GENMASK(7, 0) & ~BIT(6), 1971 .bit = 6, 1972 }, 1973 }; 1974 1975 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = { 1976 { 1977 .label = "action", 1978 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 1979 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 1980 .bit = 4, 1981 }, 1982 { 1983 .label = "timeout", 1984 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 1985 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 1986 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 1987 }, 1988 { 1989 .label = "ping", 1990 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 1991 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 1992 .bit = 1, 1993 }, 1994 }; 1995 1996 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = { 1997 { 1998 .data = mlxplat_mlxcpld_wd_main_regs_type1, 1999 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1), 2000 .version = MLX_WDT_TYPE1, 2001 .identity = "mlx-wdt-main", 2002 }, 2003 { 2004 .data = mlxplat_mlxcpld_wd_aux_regs_type1, 2005 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1), 2006 .version = MLX_WDT_TYPE1, 2007 .identity = "mlx-wdt-aux", 2008 }, 2009 }; 2010 2011 /* Watchdog type2: hardware implementation version 2 2012 * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140). 2013 */ 2014 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = { 2015 { 2016 .label = "action", 2017 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 2018 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 2019 .bit = 0, 2020 }, 2021 { 2022 .label = "timeout", 2023 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 2024 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2025 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 2026 }, 2027 { 2028 .label = "timeleft", 2029 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET, 2030 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2031 }, 2032 { 2033 .label = "ping", 2034 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 2035 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 2036 .bit = 0, 2037 }, 2038 { 2039 .label = "reset", 2040 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2041 .mask = GENMASK(7, 0) & ~BIT(6), 2042 .bit = 6, 2043 }, 2044 }; 2045 2046 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = { 2047 { 2048 .label = "action", 2049 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 2050 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 2051 .bit = 4, 2052 }, 2053 { 2054 .label = "timeout", 2055 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 2056 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2057 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 2058 }, 2059 { 2060 .label = "timeleft", 2061 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET, 2062 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2063 }, 2064 { 2065 .label = "ping", 2066 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 2067 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 2068 .bit = 4, 2069 }, 2070 }; 2071 2072 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = { 2073 { 2074 .data = mlxplat_mlxcpld_wd_main_regs_type2, 2075 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2), 2076 .version = MLX_WDT_TYPE2, 2077 .identity = "mlx-wdt-main", 2078 }, 2079 { 2080 .data = mlxplat_mlxcpld_wd_aux_regs_type2, 2081 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2), 2082 .version = MLX_WDT_TYPE2, 2083 .identity = "mlx-wdt-aux", 2084 }, 2085 }; 2086 2087 /* Watchdog type3: hardware implementation version 3 2088 * Can be on all systems. It's differentiated by WD capability bit. 2089 * Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140) 2090 * still have only one main watchdog. 2091 */ 2092 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = { 2093 { 2094 .label = "action", 2095 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 2096 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 2097 .bit = 0, 2098 }, 2099 { 2100 .label = "timeout", 2101 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 2102 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2103 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 2104 }, 2105 { 2106 .label = "timeleft", 2107 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 2108 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2109 }, 2110 { 2111 .label = "ping", 2112 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 2113 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 2114 .bit = 0, 2115 }, 2116 { 2117 .label = "reset", 2118 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2119 .mask = GENMASK(7, 0) & ~BIT(6), 2120 .bit = 6, 2121 }, 2122 }; 2123 2124 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = { 2125 { 2126 .label = "action", 2127 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 2128 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 2129 .bit = 4, 2130 }, 2131 { 2132 .label = "timeout", 2133 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 2134 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2135 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 2136 }, 2137 { 2138 .label = "timeleft", 2139 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 2140 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2141 }, 2142 { 2143 .label = "ping", 2144 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 2145 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 2146 .bit = 4, 2147 }, 2148 }; 2149 2150 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = { 2151 { 2152 .data = mlxplat_mlxcpld_wd_main_regs_type3, 2153 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type3), 2154 .version = MLX_WDT_TYPE3, 2155 .identity = "mlx-wdt-main", 2156 }, 2157 { 2158 .data = mlxplat_mlxcpld_wd_aux_regs_type3, 2159 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type3), 2160 .version = MLX_WDT_TYPE3, 2161 .identity = "mlx-wdt-aux", 2162 }, 2163 }; 2164 2165 static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) 2166 { 2167 switch (reg) { 2168 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 2169 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 2170 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 2171 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 2172 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 2173 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 2174 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 2175 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 2176 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 2177 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 2178 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 2179 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 2180 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 2181 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 2182 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 2183 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 2184 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 2185 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 2186 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 2187 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 2188 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 2189 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 2190 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 2191 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 2192 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 2193 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 2194 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 2195 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 2196 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 2197 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 2198 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 2199 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 2200 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 2201 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 2202 return true; 2203 } 2204 return false; 2205 } 2206 2207 static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) 2208 { 2209 switch (reg) { 2210 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 2211 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 2212 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 2213 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 2214 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 2215 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 2216 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 2217 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 2218 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 2219 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 2220 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 2221 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 2222 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 2223 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 2224 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 2225 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 2226 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 2227 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 2228 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 2229 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 2230 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 2231 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 2232 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 2233 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 2234 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 2235 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 2236 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 2237 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 2238 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 2239 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 2240 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 2241 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 2242 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 2243 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 2244 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 2245 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 2246 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 2247 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 2248 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 2249 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 2250 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 2251 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 2252 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 2253 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 2254 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 2255 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 2256 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 2257 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 2258 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 2259 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 2260 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 2261 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 2262 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 2263 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 2264 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 2265 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 2266 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 2267 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 2268 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 2269 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 2270 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 2271 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 2272 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 2273 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 2274 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 2275 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 2276 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 2277 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 2278 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 2279 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 2280 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 2281 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 2282 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 2283 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 2284 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 2285 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 2286 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 2287 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 2288 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 2289 return true; 2290 } 2291 return false; 2292 } 2293 2294 static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) 2295 { 2296 switch (reg) { 2297 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 2298 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 2299 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 2300 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 2301 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 2302 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 2303 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 2304 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 2305 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 2306 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 2307 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 2308 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 2309 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 2310 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 2311 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 2312 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 2313 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 2314 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 2315 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 2316 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 2317 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 2318 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 2319 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 2320 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 2321 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 2322 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 2323 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 2324 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 2325 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 2326 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 2327 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 2328 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 2329 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 2330 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 2331 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 2332 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 2333 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 2334 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 2335 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 2336 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 2337 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 2338 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 2339 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 2340 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 2341 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 2342 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 2343 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 2344 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 2345 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 2346 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 2347 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 2348 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 2349 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 2350 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 2351 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 2352 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 2353 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 2354 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 2355 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 2356 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 2357 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 2358 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 2359 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 2360 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 2361 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 2362 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 2363 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 2364 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 2365 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 2366 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 2367 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 2368 return true; 2369 } 2370 return false; 2371 } 2372 2373 static const struct reg_default mlxplat_mlxcpld_regmap_default[] = { 2374 { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 }, 2375 { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 }, 2376 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 2377 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 2378 }; 2379 2380 static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = { 2381 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 2382 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 2383 }; 2384 2385 static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = { 2386 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, 2387 MLXPLAT_CPLD_LOW_AGGRCX_MASK }, 2388 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 2389 }; 2390 2391 static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { 2392 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 2393 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 2394 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 2395 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 2396 }; 2397 2398 struct mlxplat_mlxcpld_regmap_context { 2399 void __iomem *base; 2400 }; 2401 2402 static struct mlxplat_mlxcpld_regmap_context mlxplat_mlxcpld_regmap_ctx; 2403 2404 static int 2405 mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val) 2406 { 2407 struct mlxplat_mlxcpld_regmap_context *ctx = context; 2408 2409 *val = ioread8(ctx->base + reg); 2410 return 0; 2411 } 2412 2413 static int 2414 mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val) 2415 { 2416 struct mlxplat_mlxcpld_regmap_context *ctx = context; 2417 2418 iowrite8(val, ctx->base + reg); 2419 return 0; 2420 } 2421 2422 static const struct regmap_config mlxplat_mlxcpld_regmap_config = { 2423 .reg_bits = 8, 2424 .val_bits = 8, 2425 .max_register = 255, 2426 .cache_type = REGCACHE_FLAT, 2427 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 2428 .readable_reg = mlxplat_mlxcpld_readable_reg, 2429 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 2430 .reg_defaults = mlxplat_mlxcpld_regmap_default, 2431 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default), 2432 .reg_read = mlxplat_mlxcpld_reg_read, 2433 .reg_write = mlxplat_mlxcpld_reg_write, 2434 }; 2435 2436 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = { 2437 .reg_bits = 8, 2438 .val_bits = 8, 2439 .max_register = 255, 2440 .cache_type = REGCACHE_FLAT, 2441 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 2442 .readable_reg = mlxplat_mlxcpld_readable_reg, 2443 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 2444 .reg_defaults = mlxplat_mlxcpld_regmap_ng, 2445 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng), 2446 .reg_read = mlxplat_mlxcpld_reg_read, 2447 .reg_write = mlxplat_mlxcpld_reg_write, 2448 }; 2449 2450 static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = { 2451 .reg_bits = 8, 2452 .val_bits = 8, 2453 .max_register = 255, 2454 .cache_type = REGCACHE_FLAT, 2455 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 2456 .readable_reg = mlxplat_mlxcpld_readable_reg, 2457 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 2458 .reg_defaults = mlxplat_mlxcpld_regmap_comex_default, 2459 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default), 2460 .reg_read = mlxplat_mlxcpld_reg_read, 2461 .reg_write = mlxplat_mlxcpld_reg_write, 2462 }; 2463 2464 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = { 2465 .reg_bits = 8, 2466 .val_bits = 8, 2467 .max_register = 255, 2468 .cache_type = REGCACHE_FLAT, 2469 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 2470 .readable_reg = mlxplat_mlxcpld_readable_reg, 2471 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 2472 .reg_defaults = mlxplat_mlxcpld_regmap_ng400, 2473 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400), 2474 .reg_read = mlxplat_mlxcpld_reg_read, 2475 .reg_write = mlxplat_mlxcpld_reg_write, 2476 }; 2477 2478 static struct resource mlxplat_mlxcpld_resources[] = { 2479 [0] = DEFINE_RES_IRQ_NAMED(17, "mlxreg-hotplug"), 2480 }; 2481 2482 static struct platform_device *mlxplat_dev; 2483 static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c; 2484 static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug; 2485 static struct mlxreg_core_platform_data *mlxplat_led; 2486 static struct mlxreg_core_platform_data *mlxplat_regs_io; 2487 static struct mlxreg_core_platform_data *mlxplat_fan; 2488 static struct mlxreg_core_platform_data 2489 *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; 2490 static const struct regmap_config *mlxplat_regmap_config; 2491 2492 static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) 2493 { 2494 int i; 2495 2496 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2497 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2498 mlxplat_mux_data = mlxplat_default_mux_data; 2499 for (i = 0; i < mlxplat_mux_num; i++) { 2500 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 2501 mlxplat_mux_data[i].n_values = 2502 ARRAY_SIZE(mlxplat_default_channels[i]); 2503 } 2504 mlxplat_hotplug = &mlxplat_mlxcpld_default_data; 2505 mlxplat_hotplug->deferred_nr = 2506 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2507 mlxplat_led = &mlxplat_default_led_data; 2508 mlxplat_regs_io = &mlxplat_default_regs_io_data; 2509 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 2510 2511 return 1; 2512 } 2513 2514 static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) 2515 { 2516 int i; 2517 2518 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2519 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2520 mlxplat_mux_data = mlxplat_default_mux_data; 2521 for (i = 0; i < mlxplat_mux_num; i++) { 2522 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2523 mlxplat_mux_data[i].n_values = 2524 ARRAY_SIZE(mlxplat_msn21xx_channels); 2525 } 2526 mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data; 2527 mlxplat_hotplug->deferred_nr = 2528 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2529 mlxplat_led = &mlxplat_msn21xx_led_data; 2530 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 2531 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 2532 2533 return 1; 2534 } 2535 2536 static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) 2537 { 2538 int i; 2539 2540 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2541 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2542 mlxplat_mux_data = mlxplat_default_mux_data; 2543 for (i = 0; i < mlxplat_mux_num; i++) { 2544 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2545 mlxplat_mux_data[i].n_values = 2546 ARRAY_SIZE(mlxplat_msn21xx_channels); 2547 } 2548 mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data; 2549 mlxplat_hotplug->deferred_nr = 2550 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2551 mlxplat_led = &mlxplat_default_led_data; 2552 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 2553 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 2554 2555 return 1; 2556 } 2557 2558 static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) 2559 { 2560 int i; 2561 2562 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2563 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2564 mlxplat_mux_data = mlxplat_default_mux_data; 2565 for (i = 0; i < mlxplat_mux_num; i++) { 2566 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2567 mlxplat_mux_data[i].n_values = 2568 ARRAY_SIZE(mlxplat_msn21xx_channels); 2569 } 2570 mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data; 2571 mlxplat_hotplug->deferred_nr = 2572 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2573 mlxplat_led = &mlxplat_msn21xx_led_data; 2574 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 2575 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 2576 2577 return 1; 2578 } 2579 2580 static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi) 2581 { 2582 int i; 2583 2584 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2585 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2586 mlxplat_mux_data = mlxplat_default_mux_data; 2587 for (i = 0; i < mlxplat_mux_num; i++) { 2588 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2589 mlxplat_mux_data[i].n_values = 2590 ARRAY_SIZE(mlxplat_msn21xx_channels); 2591 } 2592 mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data; 2593 mlxplat_hotplug->deferred_nr = 2594 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2595 mlxplat_led = &mlxplat_default_ng_led_data; 2596 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 2597 mlxplat_fan = &mlxplat_default_fan_data; 2598 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 2599 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 2600 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 2601 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 2602 2603 return 1; 2604 } 2605 2606 static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) 2607 { 2608 int i; 2609 2610 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 2611 mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data); 2612 mlxplat_mux_data = mlxplat_extended_mux_data; 2613 for (i = 0; i < mlxplat_mux_num; i++) { 2614 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2615 mlxplat_mux_data[i].n_values = 2616 ARRAY_SIZE(mlxplat_msn21xx_channels); 2617 } 2618 mlxplat_hotplug = &mlxplat_mlxcpld_comex_data; 2619 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 2620 mlxplat_led = &mlxplat_comex_100G_led_data; 2621 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 2622 mlxplat_fan = &mlxplat_default_fan_data; 2623 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 2624 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 2625 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex; 2626 2627 return 1; 2628 } 2629 2630 static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) 2631 { 2632 int i; 2633 2634 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2635 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2636 mlxplat_mux_data = mlxplat_default_mux_data; 2637 for (i = 0; i < mlxplat_mux_num; i++) { 2638 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2639 mlxplat_mux_data[i].n_values = 2640 ARRAY_SIZE(mlxplat_msn21xx_channels); 2641 } 2642 mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; 2643 mlxplat_hotplug->deferred_nr = 2644 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2645 mlxplat_led = &mlxplat_default_ng_led_data; 2646 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 2647 mlxplat_fan = &mlxplat_default_fan_data; 2648 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 2649 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 2650 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 2651 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 2652 2653 return 1; 2654 } 2655 2656 static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { 2657 { 2658 .callback = mlxplat_dmi_default_matched, 2659 .matches = { 2660 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 2661 }, 2662 }, 2663 { 2664 .callback = mlxplat_dmi_msn21xx_matched, 2665 .matches = { 2666 DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"), 2667 }, 2668 }, 2669 { 2670 .callback = mlxplat_dmi_msn274x_matched, 2671 .matches = { 2672 DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"), 2673 }, 2674 }, 2675 { 2676 .callback = mlxplat_dmi_msn201x_matched, 2677 .matches = { 2678 DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"), 2679 }, 2680 }, 2681 { 2682 .callback = mlxplat_dmi_qmb7xx_matched, 2683 .matches = { 2684 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 2685 }, 2686 }, 2687 { 2688 .callback = mlxplat_dmi_qmb7xx_matched, 2689 .matches = { 2690 DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"), 2691 }, 2692 }, 2693 { 2694 .callback = mlxplat_dmi_comex_matched, 2695 .matches = { 2696 DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"), 2697 }, 2698 }, 2699 { 2700 .callback = mlxplat_dmi_ng400_matched, 2701 .matches = { 2702 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 2703 }, 2704 }, 2705 { 2706 .callback = mlxplat_dmi_msn274x_matched, 2707 .matches = { 2708 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2709 DMI_MATCH(DMI_PRODUCT_NAME, "MSN274"), 2710 }, 2711 }, 2712 { 2713 .callback = mlxplat_dmi_default_matched, 2714 .matches = { 2715 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2716 DMI_MATCH(DMI_PRODUCT_NAME, "MSN24"), 2717 }, 2718 }, 2719 { 2720 .callback = mlxplat_dmi_default_matched, 2721 .matches = { 2722 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2723 DMI_MATCH(DMI_PRODUCT_NAME, "MSN27"), 2724 }, 2725 }, 2726 { 2727 .callback = mlxplat_dmi_default_matched, 2728 .matches = { 2729 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2730 DMI_MATCH(DMI_PRODUCT_NAME, "MSB"), 2731 }, 2732 }, 2733 { 2734 .callback = mlxplat_dmi_default_matched, 2735 .matches = { 2736 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2737 DMI_MATCH(DMI_PRODUCT_NAME, "MSX"), 2738 }, 2739 }, 2740 { 2741 .callback = mlxplat_dmi_msn21xx_matched, 2742 .matches = { 2743 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2744 DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"), 2745 }, 2746 }, 2747 { 2748 .callback = mlxplat_dmi_msn201x_matched, 2749 .matches = { 2750 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2751 DMI_MATCH(DMI_PRODUCT_NAME, "MSN201"), 2752 }, 2753 }, 2754 { 2755 .callback = mlxplat_dmi_qmb7xx_matched, 2756 .matches = { 2757 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2758 DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"), 2759 }, 2760 }, 2761 { 2762 .callback = mlxplat_dmi_qmb7xx_matched, 2763 .matches = { 2764 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2765 DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"), 2766 }, 2767 }, 2768 { 2769 .callback = mlxplat_dmi_qmb7xx_matched, 2770 .matches = { 2771 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2772 DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"), 2773 }, 2774 }, 2775 { 2776 .callback = mlxplat_dmi_qmb7xx_matched, 2777 .matches = { 2778 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2779 DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"), 2780 }, 2781 }, 2782 { } 2783 }; 2784 2785 MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table); 2786 2787 static int mlxplat_mlxcpld_verify_bus_topology(int *nr) 2788 { 2789 struct i2c_adapter *search_adap; 2790 int shift, i; 2791 2792 /* Scan adapters from expected id to verify it is free. */ 2793 *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; 2794 for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i < 2795 mlxplat_max_adap_num; i++) { 2796 search_adap = i2c_get_adapter(i); 2797 if (search_adap) { 2798 i2c_put_adapter(search_adap); 2799 continue; 2800 } 2801 2802 /* Return if expected parent adapter is free. */ 2803 if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR) 2804 return 0; 2805 break; 2806 } 2807 2808 /* Return with error if free id for adapter is not found. */ 2809 if (i == mlxplat_max_adap_num) 2810 return -ENODEV; 2811 2812 /* Shift adapter ids, since expected parent adapter is not free. */ 2813 *nr = i; 2814 for (i = 0; i < mlxplat_mux_num; i++) { 2815 shift = *nr - mlxplat_mux_data[i].parent; 2816 mlxplat_mux_data[i].parent = *nr; 2817 mlxplat_mux_data[i].base_nr += shift; 2818 if (shift > 0) 2819 mlxplat_hotplug->shift_nr = shift; 2820 } 2821 2822 return 0; 2823 } 2824 2825 static int mlxplat_mlxcpld_check_wd_capability(void *regmap) 2826 { 2827 u32 regval; 2828 int i, rc; 2829 2830 rc = regmap_read(regmap, MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2831 ®val); 2832 if (rc) 2833 return rc; 2834 2835 if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) { 2836 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) { 2837 if (mlxplat_wd_data[i]) 2838 mlxplat_wd_data[i] = 2839 &mlxplat_mlxcpld_wd_set_type3[i]; 2840 } 2841 } 2842 2843 return 0; 2844 } 2845 2846 static int __init mlxplat_init(void) 2847 { 2848 struct mlxplat_priv *priv; 2849 int i, j, nr, err; 2850 2851 if (!dmi_check_system(mlxplat_dmi_table)) 2852 return -ENODEV; 2853 2854 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1, 2855 mlxplat_lpc_resources, 2856 ARRAY_SIZE(mlxplat_lpc_resources)); 2857 2858 if (IS_ERR(mlxplat_dev)) 2859 return PTR_ERR(mlxplat_dev); 2860 2861 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), 2862 GFP_KERNEL); 2863 if (!priv) { 2864 err = -ENOMEM; 2865 goto fail_alloc; 2866 } 2867 platform_set_drvdata(mlxplat_dev, priv); 2868 2869 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, 2870 mlxplat_lpc_resources[1].start, 1); 2871 if (!mlxplat_mlxcpld_regmap_ctx.base) { 2872 err = -ENOMEM; 2873 goto fail_alloc; 2874 } 2875 2876 if (!mlxplat_regmap_config) 2877 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; 2878 2879 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, 2880 &mlxplat_mlxcpld_regmap_ctx, 2881 mlxplat_regmap_config); 2882 if (IS_ERR(priv->regmap)) { 2883 err = PTR_ERR(priv->regmap); 2884 goto fail_alloc; 2885 } 2886 2887 err = mlxplat_mlxcpld_verify_bus_topology(&nr); 2888 if (nr < 0) 2889 goto fail_alloc; 2890 2891 nr = (nr == mlxplat_max_adap_num) ? -1 : nr; 2892 if (mlxplat_i2c) 2893 mlxplat_i2c->regmap = priv->regmap; 2894 priv->pdev_i2c = platform_device_register_resndata( 2895 &mlxplat_dev->dev, "i2c_mlxcpld", 2896 nr, mlxplat_mlxcpld_resources, 2897 ARRAY_SIZE(mlxplat_mlxcpld_resources), 2898 mlxplat_i2c, sizeof(*mlxplat_i2c)); 2899 if (IS_ERR(priv->pdev_i2c)) { 2900 err = PTR_ERR(priv->pdev_i2c); 2901 goto fail_alloc; 2902 } 2903 2904 for (i = 0; i < mlxplat_mux_num; i++) { 2905 priv->pdev_mux[i] = platform_device_register_resndata( 2906 &priv->pdev_i2c->dev, 2907 "i2c-mux-reg", i, NULL, 2908 0, &mlxplat_mux_data[i], 2909 sizeof(mlxplat_mux_data[i])); 2910 if (IS_ERR(priv->pdev_mux[i])) { 2911 err = PTR_ERR(priv->pdev_mux[i]); 2912 goto fail_platform_mux_register; 2913 } 2914 } 2915 2916 /* Add hotplug driver */ 2917 mlxplat_hotplug->regmap = priv->regmap; 2918 priv->pdev_hotplug = platform_device_register_resndata( 2919 &mlxplat_dev->dev, "mlxreg-hotplug", 2920 PLATFORM_DEVID_NONE, 2921 mlxplat_mlxcpld_resources, 2922 ARRAY_SIZE(mlxplat_mlxcpld_resources), 2923 mlxplat_hotplug, sizeof(*mlxplat_hotplug)); 2924 if (IS_ERR(priv->pdev_hotplug)) { 2925 err = PTR_ERR(priv->pdev_hotplug); 2926 goto fail_platform_mux_register; 2927 } 2928 2929 /* Set default registers. */ 2930 for (j = 0; j < mlxplat_regmap_config->num_reg_defaults; j++) { 2931 err = regmap_write(priv->regmap, 2932 mlxplat_regmap_config->reg_defaults[j].reg, 2933 mlxplat_regmap_config->reg_defaults[j].def); 2934 if (err) 2935 goto fail_platform_mux_register; 2936 } 2937 2938 /* Add LED driver. */ 2939 mlxplat_led->regmap = priv->regmap; 2940 priv->pdev_led = platform_device_register_resndata( 2941 &mlxplat_dev->dev, "leds-mlxreg", 2942 PLATFORM_DEVID_NONE, NULL, 0, 2943 mlxplat_led, sizeof(*mlxplat_led)); 2944 if (IS_ERR(priv->pdev_led)) { 2945 err = PTR_ERR(priv->pdev_led); 2946 goto fail_platform_hotplug_register; 2947 } 2948 2949 /* Add registers io access driver. */ 2950 if (mlxplat_regs_io) { 2951 mlxplat_regs_io->regmap = priv->regmap; 2952 priv->pdev_io_regs = platform_device_register_resndata( 2953 &mlxplat_dev->dev, "mlxreg-io", 2954 PLATFORM_DEVID_NONE, NULL, 0, 2955 mlxplat_regs_io, 2956 sizeof(*mlxplat_regs_io)); 2957 if (IS_ERR(priv->pdev_io_regs)) { 2958 err = PTR_ERR(priv->pdev_io_regs); 2959 goto fail_platform_led_register; 2960 } 2961 } 2962 2963 /* Add FAN driver. */ 2964 if (mlxplat_fan) { 2965 mlxplat_fan->regmap = priv->regmap; 2966 priv->pdev_fan = platform_device_register_resndata( 2967 &mlxplat_dev->dev, "mlxreg-fan", 2968 PLATFORM_DEVID_NONE, NULL, 0, 2969 mlxplat_fan, 2970 sizeof(*mlxplat_fan)); 2971 if (IS_ERR(priv->pdev_fan)) { 2972 err = PTR_ERR(priv->pdev_fan); 2973 goto fail_platform_io_regs_register; 2974 } 2975 } 2976 2977 /* Add WD drivers. */ 2978 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); 2979 if (err) 2980 goto fail_platform_wd_register; 2981 for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) { 2982 if (mlxplat_wd_data[j]) { 2983 mlxplat_wd_data[j]->regmap = priv->regmap; 2984 priv->pdev_wd[j] = platform_device_register_resndata( 2985 &mlxplat_dev->dev, "mlx-wdt", 2986 j, NULL, 0, 2987 mlxplat_wd_data[j], 2988 sizeof(*mlxplat_wd_data[j])); 2989 if (IS_ERR(priv->pdev_wd[j])) { 2990 err = PTR_ERR(priv->pdev_wd[j]); 2991 goto fail_platform_wd_register; 2992 } 2993 } 2994 } 2995 2996 /* Sync registers with hardware. */ 2997 regcache_mark_dirty(priv->regmap); 2998 err = regcache_sync(priv->regmap); 2999 if (err) 3000 goto fail_platform_wd_register; 3001 3002 return 0; 3003 3004 fail_platform_wd_register: 3005 while (--j >= 0) 3006 platform_device_unregister(priv->pdev_wd[j]); 3007 if (mlxplat_fan) 3008 platform_device_unregister(priv->pdev_fan); 3009 fail_platform_io_regs_register: 3010 if (mlxplat_regs_io) 3011 platform_device_unregister(priv->pdev_io_regs); 3012 fail_platform_led_register: 3013 platform_device_unregister(priv->pdev_led); 3014 fail_platform_hotplug_register: 3015 platform_device_unregister(priv->pdev_hotplug); 3016 fail_platform_mux_register: 3017 while (--i >= 0) 3018 platform_device_unregister(priv->pdev_mux[i]); 3019 platform_device_unregister(priv->pdev_i2c); 3020 fail_alloc: 3021 platform_device_unregister(mlxplat_dev); 3022 3023 return err; 3024 } 3025 module_init(mlxplat_init); 3026 3027 static void __exit mlxplat_exit(void) 3028 { 3029 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 3030 int i; 3031 3032 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) 3033 platform_device_unregister(priv->pdev_wd[i]); 3034 if (priv->pdev_fan) 3035 platform_device_unregister(priv->pdev_fan); 3036 if (priv->pdev_io_regs) 3037 platform_device_unregister(priv->pdev_io_regs); 3038 platform_device_unregister(priv->pdev_led); 3039 platform_device_unregister(priv->pdev_hotplug); 3040 3041 for (i = mlxplat_mux_num - 1; i >= 0 ; i--) 3042 platform_device_unregister(priv->pdev_mux[i]); 3043 3044 platform_device_unregister(priv->pdev_i2c); 3045 platform_device_unregister(mlxplat_dev); 3046 } 3047 module_exit(mlxplat_exit); 3048 3049 MODULE_AUTHOR("Vadim Pasternak (vadimp@mellanox.com)"); 3050 MODULE_DESCRIPTION("Mellanox platform driver"); 3051 MODULE_LICENSE("Dual BSD/GPL"); 3052