1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* 3 * Mellanox platform driver 4 * 5 * Copyright (C) 2016-2018 Mellanox Technologies 6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com> 7 */ 8 9 #include <linux/device.h> 10 #include <linux/dmi.h> 11 #include <linux/i2c.h> 12 #include <linux/i2c-mux.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/platform_data/i2c-mux-reg.h> 17 #include <linux/platform_data/mlxreg.h> 18 #include <linux/reboot.h> 19 #include <linux/regmap.h> 20 21 #define MLX_PLAT_DEVICE_NAME "mlxplat" 22 23 /* LPC bus IO offsets */ 24 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000 25 #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500 26 #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00 27 #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01 28 #define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02 29 #define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03 30 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04 31 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET 0x05 32 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06 33 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET 0x07 34 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08 35 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0x09 36 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a 37 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b 38 #define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19 39 #define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c 40 #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d 41 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e 42 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f 43 #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20 44 #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21 45 #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22 46 #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23 47 #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 48 #define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0x25 49 #define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0x26 50 #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a 51 #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b 52 #define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d 53 #define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e 54 #define MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET 0x2f 55 #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 56 #define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31 57 #define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32 58 #define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33 59 #define MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE 0x34 60 #define MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET 0x35 61 #define MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET 0x36 62 #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 63 #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a 64 #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b 65 #define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0x3c 66 #define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0x3d 67 #define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0x3e 68 #define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0x3f 69 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 70 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 71 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 72 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 73 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 74 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 75 #define MLXPLAT_CPLD_LPC_REG_BRD_OFFSET 0x47 76 #define MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET 0x48 77 #define MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET 0x49 78 #define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a 79 #define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b 80 #define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c 81 #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 82 #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 83 #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 84 #define MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET 0x53 85 #define MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET 0x54 86 #define MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET 0x55 87 #define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET 0x56 88 #define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET 0x57 89 #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 90 #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 91 #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a 92 #define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 93 #define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 94 #define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 95 #define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70 96 #define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71 97 #define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72 98 #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 99 #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 100 #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a 101 #define MLXPLAT_CPLD_LPC_REG_EROT_OFFSET 0x91 102 #define MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET 0x92 103 #define MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET 0x93 104 #define MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET 0x94 105 #define MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET 0x95 106 #define MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET 0x96 107 #define MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET 0x97 108 #define MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET 0x98 109 #define MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET 0x99 110 #define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0x9a 111 #define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0x9b 112 #define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0x9c 113 #define MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET 0x9d 114 #define MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET 0x9e 115 #define MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET 0x9f 116 #define MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET 0xa0 117 #define MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET 0xa1 118 #define MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET 0xa2 119 #define MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET 0xa3 120 #define MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET 0xa4 121 #define MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET 0xa5 122 #define MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET 0xa6 123 #define MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET 0xa7 124 #define MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET 0xa8 125 #define MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET 0xa9 126 #define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa 127 #define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab 128 #define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 129 #define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2 130 #define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3 131 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 132 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8 133 #define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9 134 #define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb 135 #define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd 136 #define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce 137 #define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf 138 #define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1 139 #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 140 #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 141 #define MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET 0xd9 142 #define MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET 0xdb 143 #define MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET 0xda 144 #define MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET 0xdc 145 #define MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET 0xdd 146 #define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde 147 #define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf 148 #define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 149 #define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1 150 #define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2 151 #define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3 152 #define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4 153 #define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5 154 #define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6 155 #define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7 156 #define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8 157 #define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9 158 #define MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET 0xea 159 #define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb 160 #define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec 161 #define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed 162 #define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee 163 #define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef 164 #define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0 165 #define MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET 0xf1 166 #define MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET 0xf2 167 #define MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET 0xf3 168 #define MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET 0xf4 169 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5 170 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6 171 #define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7 172 #define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8 173 #define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9 174 #define MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET 0xfa 175 #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb 176 #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc 177 #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd 178 #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 179 180 #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL 181 #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 182 MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET) | \ 183 MLXPLAT_CPLD_LPC_PIO_OFFSET) 184 #define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 185 MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET) | \ 186 MLXPLAT_CPLD_LPC_PIO_OFFSET) 187 #define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 188 MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET) | \ 189 MLXPLAT_CPLD_LPC_PIO_OFFSET) 190 #define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 191 MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET) | \ 192 MLXPLAT_CPLD_LPC_PIO_OFFSET) 193 194 /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ 195 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04 196 #define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08 197 #define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08 198 #define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40 199 #define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 200 MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \ 201 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF) 202 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01 203 #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04 204 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) 205 #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3) 206 #define MLXPLAT_CPLD_AGGR_MASK_MODULAR (MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ 207 MLXPLAT_CPLD_AGGR_MASK_COMEX | \ 208 MLXPLAT_CPLD_AGGR_MASK_LC) 209 #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0) 210 #define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1) 211 #define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2) 212 #define MLXPLAT_CPLD_AGGR_MASK_LC_SCRD BIT(3) 213 #define MLXPLAT_CPLD_AGGR_MASK_LC_SYNC BIT(4) 214 #define MLXPLAT_CPLD_AGGR_MASK_LC_ACT BIT(5) 215 #define MLXPLAT_CPLD_AGGR_MASK_LC_SDWN BIT(6) 216 #define MLXPLAT_CPLD_AGGR_MASK_LC_LOW (MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT | \ 217 MLXPLAT_CPLD_AGGR_MASK_LC_RDY | \ 218 MLXPLAT_CPLD_AGGR_MASK_LC_PG | \ 219 MLXPLAT_CPLD_AGGR_MASK_LC_SCRD | \ 220 MLXPLAT_CPLD_AGGR_MASK_LC_SYNC | \ 221 MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \ 222 MLXPLAT_CPLD_AGGR_MASK_LC_SDWN) 223 #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 224 #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) 225 #define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT BIT(4) 226 #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) 227 #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) 228 #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) 229 #define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) 230 #define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0) 231 #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) 232 #define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) 233 #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0) 234 #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) 235 #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) 236 #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) 237 #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) 238 #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) 239 #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) 240 #define MLXPLAT_CPLD_LATCH_RST_MASK BIT(5) 241 #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) 242 #define MLXPLAT_CPLD_THERMAL2_PDB_MASK BIT(4) 243 #define MLXPLAT_CPLD_INTRUSION_MASK BIT(6) 244 #define MLXPLAT_CPLD_PWM_PG_MASK BIT(7) 245 #define MLXPLAT_CPLD_L1_CHA_HEALTH_MASK (MLXPLAT_CPLD_THERMAL1_PDB_MASK | \ 246 MLXPLAT_CPLD_THERMAL2_PDB_MASK | \ 247 MLXPLAT_CPLD_INTRUSION_MASK |\ 248 MLXPLAT_CPLD_PWM_PG_MASK) 249 #define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 250 #define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) 251 252 /* Masks for aggregation for comex carriers */ 253 #define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1) 254 #define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 255 MLXPLAT_CPLD_AGGR_MASK_CARRIER) 256 #define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1 257 258 /* Masks for aggregation for modular systems */ 259 #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) 260 261 #define MLXPLAT_CPLD_HALT_MASK BIT(3) 262 263 /* Default I2C parent bus number */ 264 #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 265 266 /* Maximum number of possible physical buses equipped on system */ 267 #define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 268 #define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 269 270 /* Number of channels in group */ 271 #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 272 273 /* Start channel numbers */ 274 #define MLXPLAT_CPLD_CH1 2 275 #define MLXPLAT_CPLD_CH2 10 276 #define MLXPLAT_CPLD_CH3 18 277 #define MLXPLAT_CPLD_CH2_ETH_MODULAR 3 278 #define MLXPLAT_CPLD_CH3_ETH_MODULAR 43 279 #define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 280 #define MLXPLAT_CPLD_CH2_RACK_SWITCH 18 281 #define MLXPLAT_CPLD_CH2_NG800 34 282 283 /* Number of LPC attached MUX platform devices */ 284 #define MLXPLAT_CPLD_LPC_MUX_DEVS 4 285 286 /* Hotplug devices adapter numbers */ 287 #define MLXPLAT_CPLD_NR_NONE -1 288 #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 289 #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 290 #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 291 #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 292 #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 293 #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 294 #define MLXPLAT_CPLD_NR_ASIC 3 295 #define MLXPLAT_CPLD_NR_LC_BASE 34 296 297 #define MLXPLAT_CPLD_NR_LC_SET(nr) (MLXPLAT_CPLD_NR_LC_BASE + (nr)) 298 #define MLXPLAT_CPLD_LC_ADDR 0x32 299 300 /* Masks and default values for watchdogs */ 301 #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1) 302 #define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1)) 303 304 #define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4) 305 #define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0 306 #define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1) 307 #define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4)) 308 #define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7)) 309 #define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6)) 310 #define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30 311 #define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600 312 #define MLXPLAT_CPLD_WD_MAX_DEVS 2 313 314 #define MLXPLAT_CPLD_LPC_SYSIRQ 17 315 316 /* Minimum power required for turning on Ethernet modular system (WATT) */ 317 #define MLXPLAT_CPLD_ETH_MODULAR_PWR_MIN 50 318 319 /* Default value for PWM control register for rack switch system */ 320 #define MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT 0xf4 321 322 #define MLXPLAT_I2C_MAIN_BUS_NOTIFIED 0x01 323 #define MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED 0x02 324 325 /* mlxplat_priv - platform private data 326 * @pdev_i2c - i2c controller platform device 327 * @pdev_mux - array of mux platform devices 328 * @pdev_hotplug - hotplug platform devices 329 * @pdev_led - led platform devices 330 * @pdev_io_regs - register access platform devices 331 * @pdev_fan - FAN platform devices 332 * @pdev_wd - array of watchdog platform devices 333 * @regmap: device register map 334 * @hotplug_resources: system hotplug resources 335 * @hotplug_resources_size: size of system hotplug resources 336 * @hi2c_main_init_status: init status of I2C main bus 337 */ 338 struct mlxplat_priv { 339 struct platform_device *pdev_i2c; 340 struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS]; 341 struct platform_device *pdev_hotplug; 342 struct platform_device *pdev_led; 343 struct platform_device *pdev_io_regs; 344 struct platform_device *pdev_fan; 345 struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; 346 void *regmap; 347 struct resource *hotplug_resources; 348 unsigned int hotplug_resources_size; 349 u8 i2c_main_init_status; 350 }; 351 352 static struct platform_device *mlxplat_dev; 353 static int mlxplat_i2c_main_complition_notify(void *handle, int id); 354 355 /* Regions for LPC I2C controller and LPC base register space */ 356 static const struct resource mlxplat_lpc_resources[] = { 357 [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR, 358 MLXPLAT_CPLD_LPC_IO_RANGE, 359 "mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO), 360 [1] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR, 361 MLXPLAT_CPLD_LPC_IO_RANGE, 362 "mlxplat_cpld_lpc_regs", 363 IORESOURCE_IO), 364 }; 365 366 /* Platform systems default i2c data */ 367 static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_default_data = { 368 .completion_notify = mlxplat_i2c_main_complition_notify, 369 }; 370 371 /* Platform i2c next generation systems data */ 372 static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = { 373 { 374 .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 375 .mask = MLXPLAT_CPLD_I2C_CAP_MASK, 376 .bit = MLXPLAT_CPLD_I2C_CAP_BIT, 377 }, 378 }; 379 380 static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = { 381 { 382 .data = mlxplat_mlxcpld_i2c_ng_items_data, 383 }, 384 }; 385 386 /* Platform next generation systems i2c data */ 387 static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = { 388 .items = mlxplat_mlxcpld_i2c_ng_items, 389 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 390 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 391 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET, 392 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C, 393 .completion_notify = mlxplat_i2c_main_complition_notify, 394 }; 395 396 /* Platform default channels */ 397 static const int mlxplat_default_channels[][MLXPLAT_CPLD_GRP_CHNL_NUM] = { 398 { 399 MLXPLAT_CPLD_CH1, MLXPLAT_CPLD_CH1 + 1, MLXPLAT_CPLD_CH1 + 2, 400 MLXPLAT_CPLD_CH1 + 3, MLXPLAT_CPLD_CH1 + 4, MLXPLAT_CPLD_CH1 + 401 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7 402 }, 403 { 404 MLXPLAT_CPLD_CH2, MLXPLAT_CPLD_CH2 + 1, MLXPLAT_CPLD_CH2 + 2, 405 MLXPLAT_CPLD_CH2 + 3, MLXPLAT_CPLD_CH2 + 4, MLXPLAT_CPLD_CH2 + 406 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7 407 }, 408 }; 409 410 /* Platform channels for MSN21xx system family */ 411 static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 }; 412 413 /* Platform mux data */ 414 static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { 415 { 416 .parent = 1, 417 .base_nr = MLXPLAT_CPLD_CH1, 418 .write_only = 1, 419 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 420 .reg_size = 1, 421 .idle_in_use = 1, 422 }, 423 { 424 .parent = 1, 425 .base_nr = MLXPLAT_CPLD_CH2, 426 .write_only = 1, 427 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 428 .reg_size = 1, 429 .idle_in_use = 1, 430 }, 431 432 }; 433 434 /* Platform mux configuration variables */ 435 static int mlxplat_max_adap_num; 436 static int mlxplat_mux_num; 437 static struct i2c_mux_reg_platform_data *mlxplat_mux_data; 438 439 /* Platform extended mux data */ 440 static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = { 441 { 442 .parent = 1, 443 .base_nr = MLXPLAT_CPLD_CH1, 444 .write_only = 1, 445 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 446 .reg_size = 1, 447 .idle_in_use = 1, 448 }, 449 { 450 .parent = 1, 451 .base_nr = MLXPLAT_CPLD_CH2, 452 .write_only = 1, 453 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 454 .reg_size = 1, 455 .idle_in_use = 1, 456 }, 457 { 458 .parent = 1, 459 .base_nr = MLXPLAT_CPLD_CH3, 460 .write_only = 1, 461 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 462 .reg_size = 1, 463 .idle_in_use = 1, 464 }, 465 466 }; 467 468 /* Platform channels for modular system family */ 469 static const int mlxplat_modular_upper_channel[] = { 1 }; 470 static const int mlxplat_modular_channels[] = { 471 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 472 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 473 38, 39, 40 474 }; 475 476 /* Platform modular mux data */ 477 static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = { 478 { 479 .parent = 1, 480 .base_nr = MLXPLAT_CPLD_CH1, 481 .write_only = 1, 482 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG4, 483 .reg_size = 1, 484 .idle_in_use = 1, 485 .values = mlxplat_modular_upper_channel, 486 .n_values = ARRAY_SIZE(mlxplat_modular_upper_channel), 487 }, 488 { 489 .parent = 1, 490 .base_nr = MLXPLAT_CPLD_CH2_ETH_MODULAR, 491 .write_only = 1, 492 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 493 .reg_size = 1, 494 .idle_in_use = 1, 495 .values = mlxplat_modular_channels, 496 .n_values = ARRAY_SIZE(mlxplat_modular_channels), 497 }, 498 { 499 .parent = MLXPLAT_CPLD_CH1, 500 .base_nr = MLXPLAT_CPLD_CH3_ETH_MODULAR, 501 .write_only = 1, 502 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 503 .reg_size = 1, 504 .idle_in_use = 1, 505 .values = mlxplat_msn21xx_channels, 506 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 507 }, 508 { 509 .parent = 1, 510 .base_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR, 511 .write_only = 1, 512 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 513 .reg_size = 1, 514 .idle_in_use = 1, 515 .values = mlxplat_msn21xx_channels, 516 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 517 }, 518 }; 519 520 /* Platform channels for rack switch system family */ 521 static const int mlxplat_rack_switch_channels[] = { 522 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 523 }; 524 525 /* Platform rack switch mux data */ 526 static struct i2c_mux_reg_platform_data mlxplat_rack_switch_mux_data[] = { 527 { 528 .parent = 1, 529 .base_nr = MLXPLAT_CPLD_CH1, 530 .write_only = 1, 531 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 532 .reg_size = 1, 533 .idle_in_use = 1, 534 .values = mlxplat_rack_switch_channels, 535 .n_values = ARRAY_SIZE(mlxplat_rack_switch_channels), 536 }, 537 { 538 .parent = 1, 539 .base_nr = MLXPLAT_CPLD_CH2_RACK_SWITCH, 540 .write_only = 1, 541 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 542 .reg_size = 1, 543 .idle_in_use = 1, 544 .values = mlxplat_msn21xx_channels, 545 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 546 }, 547 548 }; 549 550 /* Platform channels for ng800 system family */ 551 static const int mlxplat_ng800_channels[] = { 552 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 553 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 554 }; 555 556 /* Platform ng800 mux data */ 557 static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = { 558 { 559 .parent = 1, 560 .base_nr = MLXPLAT_CPLD_CH1, 561 .write_only = 1, 562 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 563 .reg_size = 1, 564 .idle_in_use = 1, 565 .values = mlxplat_ng800_channels, 566 .n_values = ARRAY_SIZE(mlxplat_ng800_channels), 567 }, 568 { 569 .parent = 1, 570 .base_nr = MLXPLAT_CPLD_CH2_NG800, 571 .write_only = 1, 572 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 573 .reg_size = 1, 574 .idle_in_use = 1, 575 .values = mlxplat_msn21xx_channels, 576 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 577 }, 578 579 }; 580 581 /* Platform hotplug devices */ 582 static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { 583 { 584 I2C_BOARD_INFO("dps460", 0x59), 585 }, 586 { 587 I2C_BOARD_INFO("dps460", 0x58), 588 }, 589 }; 590 591 static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = { 592 { 593 I2C_BOARD_INFO("dps460", 0x5b), 594 }, 595 { 596 I2C_BOARD_INFO("dps460", 0x5a), 597 }, 598 }; 599 600 static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = { 601 { 602 I2C_BOARD_INFO("dps460", 0x59), 603 }, 604 { 605 I2C_BOARD_INFO("dps460", 0x5a), 606 }, 607 }; 608 609 static struct i2c_board_info mlxplat_mlxcpld_fan[] = { 610 { 611 I2C_BOARD_INFO("24c32", 0x50), 612 }, 613 { 614 I2C_BOARD_INFO("24c32", 0x50), 615 }, 616 { 617 I2C_BOARD_INFO("24c32", 0x50), 618 }, 619 { 620 I2C_BOARD_INFO("24c32", 0x50), 621 }, 622 }; 623 624 /* Platform hotplug comex carrier system family data */ 625 static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = { 626 { 627 .label = "psu1", 628 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 629 .mask = BIT(0), 630 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 631 }, 632 { 633 .label = "psu2", 634 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 635 .mask = BIT(1), 636 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 637 }, 638 }; 639 640 /* Platform hotplug default data */ 641 static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = { 642 { 643 .label = "psu1", 644 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 645 .mask = BIT(0), 646 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 647 }, 648 { 649 .label = "psu2", 650 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 651 .mask = BIT(1), 652 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 653 }, 654 }; 655 656 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = { 657 { 658 .label = "pwr1", 659 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 660 .mask = BIT(0), 661 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 662 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 663 }, 664 { 665 .label = "pwr2", 666 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 667 .mask = BIT(1), 668 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 669 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 670 }, 671 }; 672 673 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = { 674 { 675 .label = "pwr1", 676 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 677 .mask = BIT(0), 678 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 679 }, 680 { 681 .label = "pwr2", 682 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 683 .mask = BIT(1), 684 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 685 }, 686 }; 687 688 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = { 689 { 690 .label = "pwr1", 691 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 692 .mask = BIT(0), 693 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[0], 694 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 695 }, 696 { 697 .label = "pwr2", 698 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 699 .mask = BIT(1), 700 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[1], 701 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 702 }, 703 }; 704 705 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = { 706 { 707 .label = "fan1", 708 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 709 .mask = BIT(0), 710 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0], 711 .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR, 712 }, 713 { 714 .label = "fan2", 715 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 716 .mask = BIT(1), 717 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1], 718 .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR, 719 }, 720 { 721 .label = "fan3", 722 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 723 .mask = BIT(2), 724 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2], 725 .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR, 726 }, 727 { 728 .label = "fan4", 729 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 730 .mask = BIT(3), 731 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3], 732 .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR, 733 }, 734 }; 735 736 static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = { 737 { 738 .label = "asic1", 739 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 740 .mask = MLXPLAT_CPLD_ASIC_MASK, 741 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 742 }, 743 }; 744 745 static struct mlxreg_core_data mlxplat_mlxcpld_default_asic2_items_data[] = { 746 { 747 .label = "asic2", 748 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 749 .mask = MLXPLAT_CPLD_ASIC_MASK, 750 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 751 }, 752 }; 753 754 static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = { 755 { 756 .data = mlxplat_mlxcpld_default_psu_items_data, 757 .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF, 758 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 759 .mask = MLXPLAT_CPLD_PSU_MASK, 760 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 761 .inversed = 1, 762 .health = false, 763 }, 764 { 765 .data = mlxplat_mlxcpld_default_pwr_items_data, 766 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 767 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 768 .mask = MLXPLAT_CPLD_PWR_MASK, 769 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 770 .inversed = 0, 771 .health = false, 772 }, 773 { 774 .data = mlxplat_mlxcpld_default_fan_items_data, 775 .aggr_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF, 776 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 777 .mask = MLXPLAT_CPLD_FAN_MASK, 778 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 779 .inversed = 1, 780 .health = false, 781 }, 782 { 783 .data = mlxplat_mlxcpld_default_asic_items_data, 784 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 785 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 786 .mask = MLXPLAT_CPLD_ASIC_MASK, 787 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 788 .inversed = 0, 789 .health = true, 790 }, 791 }; 792 793 static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = { 794 { 795 .data = mlxplat_mlxcpld_comex_psu_items_data, 796 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 797 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 798 .mask = MLXPLAT_CPLD_PSU_MASK, 799 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 800 .inversed = 1, 801 .health = false, 802 }, 803 { 804 .data = mlxplat_mlxcpld_default_pwr_items_data, 805 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 806 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 807 .mask = MLXPLAT_CPLD_PWR_MASK, 808 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 809 .inversed = 0, 810 .health = false, 811 }, 812 { 813 .data = mlxplat_mlxcpld_default_fan_items_data, 814 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 815 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 816 .mask = MLXPLAT_CPLD_FAN_MASK, 817 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 818 .inversed = 1, 819 .health = false, 820 }, 821 { 822 .data = mlxplat_mlxcpld_default_asic_items_data, 823 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 824 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 825 .mask = MLXPLAT_CPLD_ASIC_MASK, 826 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 827 .inversed = 0, 828 .health = true, 829 }, 830 }; 831 832 static 833 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = { 834 .items = mlxplat_mlxcpld_default_items, 835 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_items), 836 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 837 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 838 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 839 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 840 }; 841 842 static struct mlxreg_core_item mlxplat_mlxcpld_default_wc_items[] = { 843 { 844 .data = mlxplat_mlxcpld_comex_psu_items_data, 845 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 846 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 847 .mask = MLXPLAT_CPLD_PSU_MASK, 848 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 849 .inversed = 1, 850 .health = false, 851 }, 852 { 853 .data = mlxplat_mlxcpld_default_pwr_wc_items_data, 854 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 855 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 856 .mask = MLXPLAT_CPLD_PWR_MASK, 857 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 858 .inversed = 0, 859 .health = false, 860 }, 861 { 862 .data = mlxplat_mlxcpld_default_asic_items_data, 863 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 864 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 865 .mask = MLXPLAT_CPLD_ASIC_MASK, 866 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 867 .inversed = 0, 868 .health = true, 869 }, 870 }; 871 872 static 873 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_wc_data = { 874 .items = mlxplat_mlxcpld_default_wc_items, 875 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_wc_items), 876 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 877 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 878 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 879 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 880 }; 881 882 static 883 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = { 884 .items = mlxplat_mlxcpld_comex_items, 885 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_items), 886 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 887 .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF, 888 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET, 889 .mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK, 890 }; 891 892 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = { 893 { 894 .label = "pwr1", 895 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 896 .mask = BIT(0), 897 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 898 }, 899 { 900 .label = "pwr2", 901 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 902 .mask = BIT(1), 903 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 904 }, 905 }; 906 907 /* Platform hotplug MSN21xx system family data */ 908 static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = { 909 { 910 .data = mlxplat_mlxcpld_msn21xx_pwr_items_data, 911 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 912 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 913 .mask = MLXPLAT_CPLD_PWR_MASK, 914 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data), 915 .inversed = 0, 916 .health = false, 917 }, 918 { 919 .data = mlxplat_mlxcpld_default_asic_items_data, 920 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 921 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 922 .mask = MLXPLAT_CPLD_ASIC_MASK, 923 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 924 .inversed = 0, 925 .health = true, 926 }, 927 }; 928 929 static 930 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = { 931 .items = mlxplat_mlxcpld_msn21xx_items, 932 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items), 933 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 934 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 935 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 936 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 937 }; 938 939 /* Platform hotplug msn274x system family data */ 940 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = { 941 { 942 .label = "psu1", 943 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 944 .mask = BIT(0), 945 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 946 }, 947 { 948 .label = "psu2", 949 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 950 .mask = BIT(1), 951 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 952 }, 953 }; 954 955 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = { 956 { 957 .label = "pwr1", 958 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 959 .mask = BIT(0), 960 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 961 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 962 }, 963 { 964 .label = "pwr2", 965 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 966 .mask = BIT(1), 967 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 968 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 969 }, 970 }; 971 972 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = { 973 { 974 .label = "fan1", 975 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 976 .mask = BIT(0), 977 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 978 }, 979 { 980 .label = "fan2", 981 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 982 .mask = BIT(1), 983 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 984 }, 985 { 986 .label = "fan3", 987 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 988 .mask = BIT(2), 989 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 990 }, 991 { 992 .label = "fan4", 993 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 994 .mask = BIT(3), 995 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 996 }, 997 }; 998 999 static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = { 1000 { 1001 .data = mlxplat_mlxcpld_msn274x_psu_items_data, 1002 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1003 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1004 .mask = MLXPLAT_CPLD_PSU_MASK, 1005 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_psu_items_data), 1006 .inversed = 1, 1007 .health = false, 1008 }, 1009 { 1010 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 1011 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1012 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1013 .mask = MLXPLAT_CPLD_PWR_MASK, 1014 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 1015 .inversed = 0, 1016 .health = false, 1017 }, 1018 { 1019 .data = mlxplat_mlxcpld_msn274x_fan_items_data, 1020 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1021 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1022 .mask = MLXPLAT_CPLD_FAN_MASK, 1023 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_fan_items_data), 1024 .inversed = 1, 1025 .health = false, 1026 }, 1027 { 1028 .data = mlxplat_mlxcpld_default_asic_items_data, 1029 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1030 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1031 .mask = MLXPLAT_CPLD_ASIC_MASK, 1032 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1033 .inversed = 0, 1034 .health = true, 1035 }, 1036 }; 1037 1038 static 1039 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = { 1040 .items = mlxplat_mlxcpld_msn274x_items, 1041 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items), 1042 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1043 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1044 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1045 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1046 }; 1047 1048 /* Platform hotplug MSN201x system family data */ 1049 static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = { 1050 { 1051 .label = "pwr1", 1052 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1053 .mask = BIT(0), 1054 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1055 }, 1056 { 1057 .label = "pwr2", 1058 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1059 .mask = BIT(1), 1060 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1061 }, 1062 }; 1063 1064 static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = { 1065 { 1066 .data = mlxplat_mlxcpld_msn201x_pwr_items_data, 1067 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 1068 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1069 .mask = MLXPLAT_CPLD_PWR_MASK, 1070 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_pwr_items_data), 1071 .inversed = 0, 1072 .health = false, 1073 }, 1074 { 1075 .data = mlxplat_mlxcpld_default_asic_items_data, 1076 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 1077 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1078 .mask = MLXPLAT_CPLD_ASIC_MASK, 1079 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1080 .inversed = 0, 1081 .health = true, 1082 }, 1083 }; 1084 1085 static 1086 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = { 1087 .items = mlxplat_mlxcpld_msn201x_items, 1088 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items), 1089 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1090 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 1091 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1092 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1093 }; 1094 1095 /* Platform hotplug next generation system family data */ 1096 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = { 1097 { 1098 .label = "psu1", 1099 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1100 .mask = BIT(0), 1101 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1102 }, 1103 { 1104 .label = "psu2", 1105 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1106 .mask = BIT(1), 1107 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1108 }, 1109 }; 1110 1111 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = { 1112 { 1113 .label = "fan1", 1114 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1115 .mask = BIT(0), 1116 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1117 .bit = BIT(0), 1118 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1119 }, 1120 { 1121 .label = "fan2", 1122 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1123 .mask = BIT(1), 1124 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1125 .bit = BIT(1), 1126 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1127 }, 1128 { 1129 .label = "fan3", 1130 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1131 .mask = BIT(2), 1132 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1133 .bit = BIT(2), 1134 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1135 }, 1136 { 1137 .label = "fan4", 1138 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1139 .mask = BIT(3), 1140 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1141 .bit = BIT(3), 1142 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1143 }, 1144 { 1145 .label = "fan5", 1146 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1147 .mask = BIT(4), 1148 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1149 .bit = BIT(4), 1150 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1151 }, 1152 { 1153 .label = "fan6", 1154 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1155 .mask = BIT(5), 1156 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1157 .bit = BIT(5), 1158 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1159 }, 1160 { 1161 .label = "fan7", 1162 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1163 .mask = BIT(6), 1164 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1165 .bit = BIT(6), 1166 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1167 }, 1168 }; 1169 1170 static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = { 1171 { 1172 .data = mlxplat_mlxcpld_default_ng_psu_items_data, 1173 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1174 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1175 .mask = MLXPLAT_CPLD_PSU_MASK, 1176 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), 1177 .inversed = 1, 1178 .health = false, 1179 }, 1180 { 1181 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 1182 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1183 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1184 .mask = MLXPLAT_CPLD_PWR_MASK, 1185 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 1186 .inversed = 0, 1187 .health = false, 1188 }, 1189 { 1190 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1191 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1192 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1193 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1194 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1195 .inversed = 1, 1196 .health = false, 1197 }, 1198 { 1199 .data = mlxplat_mlxcpld_default_asic_items_data, 1200 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1201 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1202 .mask = MLXPLAT_CPLD_ASIC_MASK, 1203 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1204 .inversed = 0, 1205 .health = true, 1206 }, 1207 }; 1208 1209 static 1210 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = { 1211 .items = mlxplat_mlxcpld_default_ng_items, 1212 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items), 1213 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1214 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1215 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1216 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1217 }; 1218 1219 /* Platform hotplug extended system family data */ 1220 static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = { 1221 { 1222 .label = "psu1", 1223 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1224 .mask = BIT(0), 1225 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1226 }, 1227 { 1228 .label = "psu2", 1229 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1230 .mask = BIT(1), 1231 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1232 }, 1233 { 1234 .label = "psu3", 1235 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1236 .mask = BIT(2), 1237 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1238 }, 1239 { 1240 .label = "psu4", 1241 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1242 .mask = BIT(3), 1243 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1244 }, 1245 }; 1246 1247 static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = { 1248 { 1249 .label = "pwr1", 1250 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1251 .mask = BIT(0), 1252 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1253 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1254 }, 1255 { 1256 .label = "pwr2", 1257 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1258 .mask = BIT(1), 1259 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1260 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1261 }, 1262 { 1263 .label = "pwr3", 1264 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1265 .mask = BIT(2), 1266 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 1267 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1268 }, 1269 { 1270 .label = "pwr4", 1271 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1272 .mask = BIT(3), 1273 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 1274 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1275 }, 1276 }; 1277 1278 static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { 1279 { 1280 .data = mlxplat_mlxcpld_ext_psu_items_data, 1281 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1282 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1283 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 1284 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1285 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 1286 .inversed = 1, 1287 .health = false, 1288 }, 1289 { 1290 .data = mlxplat_mlxcpld_ext_pwr_items_data, 1291 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1292 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1293 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 1294 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1295 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 1296 .inversed = 0, 1297 .health = false, 1298 }, 1299 { 1300 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1301 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1302 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1303 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1304 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1305 .inversed = 1, 1306 .health = false, 1307 }, 1308 { 1309 .data = mlxplat_mlxcpld_default_asic_items_data, 1310 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1311 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1312 .mask = MLXPLAT_CPLD_ASIC_MASK, 1313 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1314 .inversed = 0, 1315 .health = true, 1316 }, 1317 { 1318 .data = mlxplat_mlxcpld_default_asic2_items_data, 1319 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1320 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 1321 .mask = MLXPLAT_CPLD_ASIC_MASK, 1322 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic2_items_data), 1323 .inversed = 0, 1324 .health = true, 1325 } 1326 }; 1327 1328 static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = { 1329 { 1330 .data = mlxplat_mlxcpld_default_ng_psu_items_data, 1331 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1332 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1333 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 1334 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1335 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), 1336 .inversed = 1, 1337 .health = false, 1338 }, 1339 { 1340 .data = mlxplat_mlxcpld_default_pwr_ng800_items_data, 1341 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1342 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1343 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 1344 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1345 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_ng800_items_data), 1346 .inversed = 0, 1347 .health = false, 1348 }, 1349 { 1350 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1351 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1352 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1353 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1354 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1355 .inversed = 1, 1356 .health = false, 1357 }, 1358 { 1359 .data = mlxplat_mlxcpld_default_asic_items_data, 1360 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1361 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1362 .mask = MLXPLAT_CPLD_ASIC_MASK, 1363 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1364 .inversed = 0, 1365 .health = true, 1366 }, 1367 }; 1368 1369 static 1370 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { 1371 .items = mlxplat_mlxcpld_ext_items, 1372 .counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_items), 1373 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1374 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1375 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1376 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, 1377 }; 1378 1379 static 1380 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = { 1381 .items = mlxplat_mlxcpld_ng800_items, 1382 .counter = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items), 1383 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1384 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1385 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1386 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, 1387 }; 1388 1389 static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { 1390 { 1391 .label = "pwr1", 1392 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1393 .mask = BIT(0), 1394 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1395 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1396 }, 1397 { 1398 .label = "pwr2", 1399 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1400 .mask = BIT(1), 1401 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1402 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1403 }, 1404 { 1405 .label = "pwr3", 1406 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1407 .mask = BIT(2), 1408 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 1409 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1410 }, 1411 { 1412 .label = "pwr4", 1413 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1414 .mask = BIT(3), 1415 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 1416 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1417 }, 1418 }; 1419 1420 static 1421 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_lc_act = { 1422 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 1423 }; 1424 1425 static struct mlxreg_core_data mlxplat_mlxcpld_modular_asic_items_data[] = { 1426 { 1427 .label = "asic1", 1428 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1429 .mask = MLXPLAT_CPLD_ASIC_MASK, 1430 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1431 }, 1432 }; 1433 1434 static struct i2c_board_info mlxplat_mlxcpld_lc_i2c_dev[] = { 1435 { 1436 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1437 .platform_data = &mlxplat_mlxcpld_lc_act, 1438 }, 1439 { 1440 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1441 .platform_data = &mlxplat_mlxcpld_lc_act, 1442 }, 1443 { 1444 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1445 .platform_data = &mlxplat_mlxcpld_lc_act, 1446 }, 1447 { 1448 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1449 .platform_data = &mlxplat_mlxcpld_lc_act, 1450 }, 1451 { 1452 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1453 .platform_data = &mlxplat_mlxcpld_lc_act, 1454 }, 1455 { 1456 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1457 .platform_data = &mlxplat_mlxcpld_lc_act, 1458 }, 1459 { 1460 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1461 .platform_data = &mlxplat_mlxcpld_lc_act, 1462 }, 1463 { 1464 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1465 .platform_data = &mlxplat_mlxcpld_lc_act, 1466 }, 1467 }; 1468 1469 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_modular_lc_notifier[] = { 1470 { 1471 .identity = "lc1", 1472 }, 1473 { 1474 .identity = "lc2", 1475 }, 1476 { 1477 .identity = "lc3", 1478 }, 1479 { 1480 .identity = "lc4", 1481 }, 1482 { 1483 .identity = "lc5", 1484 }, 1485 { 1486 .identity = "lc6", 1487 }, 1488 { 1489 .identity = "lc7", 1490 }, 1491 { 1492 .identity = "lc8", 1493 }, 1494 }; 1495 1496 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { 1497 { 1498 .label = "lc1_present", 1499 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1500 .mask = BIT(0), 1501 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1502 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1503 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1504 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1505 .slot = 1, 1506 }, 1507 { 1508 .label = "lc2_present", 1509 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1510 .mask = BIT(1), 1511 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1512 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1513 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1514 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1515 .slot = 2, 1516 }, 1517 { 1518 .label = "lc3_present", 1519 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1520 .mask = BIT(2), 1521 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1522 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1523 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1524 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1525 .slot = 3, 1526 }, 1527 { 1528 .label = "lc4_present", 1529 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1530 .mask = BIT(3), 1531 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1532 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1533 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1534 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1535 .slot = 4, 1536 }, 1537 { 1538 .label = "lc5_present", 1539 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1540 .mask = BIT(4), 1541 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1542 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1543 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1544 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1545 .slot = 5, 1546 }, 1547 { 1548 .label = "lc6_present", 1549 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1550 .mask = BIT(5), 1551 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1552 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1553 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1554 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1555 .slot = 6, 1556 }, 1557 { 1558 .label = "lc7_present", 1559 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1560 .mask = BIT(6), 1561 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1562 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1563 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1564 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1565 .slot = 7, 1566 }, 1567 { 1568 .label = "lc8_present", 1569 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1570 .mask = BIT(7), 1571 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1572 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1573 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1574 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1575 .slot = 8, 1576 }, 1577 }; 1578 1579 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { 1580 { 1581 .label = "lc1_verified", 1582 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1583 .mask = BIT(0), 1584 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1585 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1586 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1587 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1588 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1589 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1590 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1591 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1592 .slot = 1, 1593 }, 1594 { 1595 .label = "lc2_verified", 1596 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1597 .mask = BIT(1), 1598 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1599 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1600 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1601 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1602 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1603 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1604 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1605 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1606 .slot = 2, 1607 }, 1608 { 1609 .label = "lc3_verified", 1610 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1611 .mask = BIT(2), 1612 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1613 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1614 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1615 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1616 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1617 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1618 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1619 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1620 .slot = 3, 1621 }, 1622 { 1623 .label = "lc4_verified", 1624 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1625 .mask = BIT(3), 1626 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1627 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1628 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1629 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1630 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1631 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1632 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1633 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1634 .slot = 4, 1635 }, 1636 { 1637 .label = "lc5_verified", 1638 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1639 .mask = BIT(4), 1640 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1641 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1642 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1643 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1644 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1645 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1646 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1647 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1648 .slot = 5, 1649 }, 1650 { 1651 .label = "lc6_verified", 1652 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1653 .mask = BIT(5), 1654 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1655 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1656 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1657 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1658 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1659 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1660 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1661 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1662 .slot = 6, 1663 }, 1664 { 1665 .label = "lc7_verified", 1666 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1667 .mask = BIT(6), 1668 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1669 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1670 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1671 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1672 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1673 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1674 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1675 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1676 .slot = 7, 1677 }, 1678 { 1679 .label = "lc8_verified", 1680 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1681 .mask = BIT(7), 1682 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1683 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1684 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1685 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1686 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1687 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1688 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1689 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1690 .slot = 8, 1691 }, 1692 }; 1693 1694 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { 1695 { 1696 .label = "lc1_powered", 1697 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1698 .mask = BIT(0), 1699 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1700 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1701 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1702 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1703 .slot = 1, 1704 }, 1705 { 1706 .label = "lc2_powered", 1707 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1708 .mask = BIT(1), 1709 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1710 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1711 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1712 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1713 .slot = 2, 1714 }, 1715 { 1716 .label = "lc3_powered", 1717 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1718 .mask = BIT(2), 1719 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1720 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1721 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1722 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1723 .slot = 3, 1724 }, 1725 { 1726 .label = "lc4_powered", 1727 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1728 .mask = BIT(3), 1729 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1730 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1731 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1732 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1733 .slot = 4, 1734 }, 1735 { 1736 .label = "lc5_powered", 1737 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1738 .mask = BIT(4), 1739 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1740 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1741 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1742 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1743 .slot = 5, 1744 }, 1745 { 1746 .label = "lc6_powered", 1747 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1748 .mask = BIT(5), 1749 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1750 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1751 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1752 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1753 .slot = 6, 1754 }, 1755 { 1756 .label = "lc7_powered", 1757 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1758 .mask = BIT(6), 1759 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1760 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1761 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1762 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1763 .slot = 7, 1764 }, 1765 { 1766 .label = "lc8_powered", 1767 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1768 .mask = BIT(7), 1769 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1770 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1771 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1772 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1773 .slot = 8, 1774 }, 1775 }; 1776 1777 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { 1778 { 1779 .label = "lc1_ready", 1780 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1781 .mask = BIT(0), 1782 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1783 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1784 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1785 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1786 .slot = 1, 1787 }, 1788 { 1789 .label = "lc2_ready", 1790 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1791 .mask = BIT(1), 1792 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1793 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1794 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1795 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1796 .slot = 2, 1797 }, 1798 { 1799 .label = "lc3_ready", 1800 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1801 .mask = BIT(2), 1802 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1803 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1804 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1805 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1806 .slot = 3, 1807 }, 1808 { 1809 .label = "lc4_ready", 1810 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1811 .mask = BIT(3), 1812 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1813 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1814 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1815 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1816 .slot = 4, 1817 }, 1818 { 1819 .label = "lc5_ready", 1820 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1821 .mask = BIT(4), 1822 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1823 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1824 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1825 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1826 .slot = 5, 1827 }, 1828 { 1829 .label = "lc6_ready", 1830 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1831 .mask = BIT(5), 1832 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1833 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1834 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1835 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1836 .slot = 6, 1837 }, 1838 { 1839 .label = "lc7_ready", 1840 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1841 .mask = BIT(6), 1842 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1843 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1844 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1845 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1846 .slot = 7, 1847 }, 1848 { 1849 .label = "lc8_ready", 1850 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1851 .mask = BIT(7), 1852 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1853 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1854 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1855 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1856 .slot = 8, 1857 }, 1858 }; 1859 1860 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { 1861 { 1862 .label = "lc1_synced", 1863 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1864 .mask = BIT(0), 1865 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1866 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1867 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1868 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1869 .slot = 1, 1870 }, 1871 { 1872 .label = "lc2_synced", 1873 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1874 .mask = BIT(1), 1875 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1876 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1877 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1878 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1879 .slot = 2, 1880 }, 1881 { 1882 .label = "lc3_synced", 1883 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1884 .mask = BIT(2), 1885 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1886 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1887 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1888 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1889 .slot = 3, 1890 }, 1891 { 1892 .label = "lc4_synced", 1893 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1894 .mask = BIT(3), 1895 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1896 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1897 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1898 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1899 .slot = 4, 1900 }, 1901 { 1902 .label = "lc5_synced", 1903 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1904 .mask = BIT(4), 1905 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1906 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1907 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1908 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1909 .slot = 5, 1910 }, 1911 { 1912 .label = "lc6_synced", 1913 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1914 .mask = BIT(5), 1915 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1916 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1917 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1918 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1919 .slot = 6, 1920 }, 1921 { 1922 .label = "lc7_synced", 1923 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1924 .mask = BIT(6), 1925 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1926 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1927 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1928 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1929 .slot = 7, 1930 }, 1931 { 1932 .label = "lc8_synced", 1933 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1934 .mask = BIT(7), 1935 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1936 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1937 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1938 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1939 .slot = 8, 1940 }, 1941 }; 1942 1943 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { 1944 { 1945 .label = "lc1_active", 1946 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1947 .mask = BIT(0), 1948 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1949 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1950 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1951 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1952 .slot = 1, 1953 }, 1954 { 1955 .label = "lc2_active", 1956 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1957 .mask = BIT(1), 1958 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1959 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1960 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1961 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1962 .slot = 2, 1963 }, 1964 { 1965 .label = "lc3_active", 1966 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1967 .mask = BIT(2), 1968 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1969 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1970 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1971 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1972 .slot = 3, 1973 }, 1974 { 1975 .label = "lc4_active", 1976 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1977 .mask = BIT(3), 1978 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1979 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1980 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1981 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1982 .slot = 4, 1983 }, 1984 { 1985 .label = "lc5_active", 1986 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1987 .mask = BIT(4), 1988 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1989 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1990 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1991 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1992 .slot = 5, 1993 }, 1994 { 1995 .label = "lc6_active", 1996 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1997 .mask = BIT(5), 1998 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1999 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 2000 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2001 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 2002 .slot = 6, 2003 }, 2004 { 2005 .label = "lc7_active", 2006 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2007 .mask = BIT(6), 2008 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 2009 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 2010 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2011 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 2012 .slot = 7, 2013 }, 2014 { 2015 .label = "lc8_active", 2016 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2017 .mask = BIT(7), 2018 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 2019 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 2020 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2021 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 2022 .slot = 8, 2023 }, 2024 }; 2025 2026 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { 2027 { 2028 .label = "lc1_shutdown", 2029 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2030 .mask = BIT(0), 2031 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 2032 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 2033 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2034 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 2035 .slot = 1, 2036 }, 2037 { 2038 .label = "lc2_shutdown", 2039 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2040 .mask = BIT(1), 2041 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 2042 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 2043 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2044 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 2045 .slot = 2, 2046 }, 2047 { 2048 .label = "lc3_shutdown", 2049 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2050 .mask = BIT(2), 2051 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 2052 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 2053 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2054 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 2055 .slot = 3, 2056 }, 2057 { 2058 .label = "lc4_shutdown", 2059 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2060 .mask = BIT(3), 2061 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 2062 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 2063 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2064 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 2065 .slot = 4, 2066 }, 2067 { 2068 .label = "lc5_shutdown", 2069 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2070 .mask = BIT(4), 2071 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 2072 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 2073 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2074 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 2075 .slot = 5, 2076 }, 2077 { 2078 .label = "lc6_shutdown", 2079 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2080 .mask = BIT(5), 2081 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 2082 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 2083 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2084 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 2085 .slot = 6, 2086 }, 2087 { 2088 .label = "lc7_shutdown", 2089 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2090 .mask = BIT(6), 2091 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 2092 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 2093 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2094 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 2095 .slot = 7, 2096 }, 2097 { 2098 .label = "lc8_shutdown", 2099 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2100 .mask = BIT(7), 2101 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 2102 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 2103 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2104 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 2105 .slot = 8, 2106 }, 2107 }; 2108 2109 static struct mlxreg_core_item mlxplat_mlxcpld_modular_items[] = { 2110 { 2111 .data = mlxplat_mlxcpld_ext_psu_items_data, 2112 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2113 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2114 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 2115 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2116 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 2117 .inversed = 1, 2118 .health = false, 2119 }, 2120 { 2121 .data = mlxplat_mlxcpld_modular_pwr_items_data, 2122 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2123 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2124 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 2125 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2126 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 2127 .inversed = 0, 2128 .health = false, 2129 }, 2130 { 2131 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 2132 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2133 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2134 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 2135 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 2136 .inversed = 1, 2137 .health = false, 2138 }, 2139 { 2140 .data = mlxplat_mlxcpld_modular_asic_items_data, 2141 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2142 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 2143 .mask = MLXPLAT_CPLD_ASIC_MASK, 2144 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_asic_items_data), 2145 .inversed = 0, 2146 .health = true, 2147 }, 2148 { 2149 .data = mlxplat_mlxcpld_modular_lc_pr_items_data, 2150 .kind = MLXREG_HOTPLUG_LC_PRESENT, 2151 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2152 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 2153 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2154 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pr_items_data), 2155 .inversed = 1, 2156 .health = false, 2157 }, 2158 { 2159 .data = mlxplat_mlxcpld_modular_lc_ver_items_data, 2160 .kind = MLXREG_HOTPLUG_LC_VERIFIED, 2161 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2162 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 2163 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2164 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ver_items_data), 2165 .inversed = 0, 2166 .health = false, 2167 }, 2168 { 2169 .data = mlxplat_mlxcpld_modular_lc_pg_data, 2170 .kind = MLXREG_HOTPLUG_LC_POWERED, 2171 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2172 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 2173 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2174 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pg_data), 2175 .inversed = 0, 2176 .health = false, 2177 }, 2178 { 2179 .data = mlxplat_mlxcpld_modular_lc_ready_data, 2180 .kind = MLXREG_HOTPLUG_LC_READY, 2181 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2182 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2183 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2184 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ready_data), 2185 .inversed = 0, 2186 .health = false, 2187 }, 2188 { 2189 .data = mlxplat_mlxcpld_modular_lc_synced_data, 2190 .kind = MLXREG_HOTPLUG_LC_SYNCED, 2191 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2192 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2193 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2194 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_synced_data), 2195 .inversed = 0, 2196 .health = false, 2197 }, 2198 { 2199 .data = mlxplat_mlxcpld_modular_lc_act_data, 2200 .kind = MLXREG_HOTPLUG_LC_ACTIVE, 2201 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2202 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2203 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2204 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_act_data), 2205 .inversed = 0, 2206 .health = false, 2207 }, 2208 { 2209 .data = mlxplat_mlxcpld_modular_lc_sd_data, 2210 .kind = MLXREG_HOTPLUG_LC_THERMAL, 2211 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2212 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2213 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2214 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_sd_data), 2215 .inversed = 0, 2216 .health = false, 2217 }, 2218 }; 2219 2220 static 2221 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = { 2222 .items = mlxplat_mlxcpld_modular_items, 2223 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_items), 2224 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2225 .mask = MLXPLAT_CPLD_AGGR_MASK_MODULAR, 2226 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2227 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2228 }; 2229 2230 /* Platform hotplug for NVLink blade systems family data */ 2231 static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = { 2232 { 2233 .label = "global_wp_grant", 2234 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 2235 .mask = MLXPLAT_CPLD_GWP_MASK, 2236 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2237 }, 2238 }; 2239 2240 static struct mlxreg_core_item mlxplat_mlxcpld_chassis_blade_items[] = { 2241 { 2242 .data = mlxplat_mlxcpld_global_wp_items_data, 2243 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2244 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 2245 .mask = MLXPLAT_CPLD_GWP_MASK, 2246 .count = ARRAY_SIZE(mlxplat_mlxcpld_global_wp_items_data), 2247 .inversed = 0, 2248 .health = false, 2249 }, 2250 }; 2251 2252 static 2253 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_chassis_blade_data = { 2254 .items = mlxplat_mlxcpld_chassis_blade_items, 2255 .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_items), 2256 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2257 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 2258 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2259 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2260 }; 2261 2262 /* Platform hotplug for switch systems family data */ 2263 static struct mlxreg_core_data mlxplat_mlxcpld_erot_ap_items_data[] = { 2264 { 2265 .label = "erot1_ap", 2266 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2267 .mask = BIT(0), 2268 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2269 }, 2270 { 2271 .label = "erot2_ap", 2272 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2273 .mask = BIT(1), 2274 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2275 }, 2276 }; 2277 2278 static struct mlxreg_core_data mlxplat_mlxcpld_erot_error_items_data[] = { 2279 { 2280 .label = "erot1_error", 2281 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2282 .mask = BIT(0), 2283 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2284 }, 2285 { 2286 .label = "erot2_error", 2287 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2288 .mask = BIT(1), 2289 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2290 }, 2291 }; 2292 2293 static struct mlxreg_core_item mlxplat_mlxcpld_rack_switch_items[] = { 2294 { 2295 .data = mlxplat_mlxcpld_ext_psu_items_data, 2296 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2297 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2298 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 2299 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2300 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 2301 .inversed = 1, 2302 .health = false, 2303 }, 2304 { 2305 .data = mlxplat_mlxcpld_ext_pwr_items_data, 2306 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2307 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2308 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 2309 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2310 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 2311 .inversed = 0, 2312 .health = false, 2313 }, 2314 { 2315 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 2316 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2317 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2318 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 2319 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 2320 .inversed = 1, 2321 .health = false, 2322 }, 2323 { 2324 .data = mlxplat_mlxcpld_erot_ap_items_data, 2325 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2326 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2327 .mask = MLXPLAT_CPLD_EROT_MASK, 2328 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), 2329 .inversed = 1, 2330 .health = false, 2331 }, 2332 { 2333 .data = mlxplat_mlxcpld_erot_error_items_data, 2334 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2335 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2336 .mask = MLXPLAT_CPLD_EROT_MASK, 2337 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), 2338 .inversed = 1, 2339 .health = false, 2340 }, 2341 }; 2342 2343 static 2344 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = { 2345 .items = mlxplat_mlxcpld_rack_switch_items, 2346 .counter = ARRAY_SIZE(mlxplat_mlxcpld_rack_switch_items), 2347 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2348 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 2349 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2350 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2351 }; 2352 2353 /* Callback performs graceful shutdown after notification about power button event */ 2354 static int 2355 mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind, 2356 u8 action) 2357 { 2358 dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); 2359 kernel_halt(); 2360 return 0; 2361 } 2362 2363 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_notifier = { 2364 .user_handler = mlxplat_mlxcpld_l1_switch_pwr_events_handler, 2365 }; 2366 2367 /* Platform hotplug for l1 switch systems family data */ 2368 static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = { 2369 { 2370 .label = "power_button", 2371 .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, 2372 .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, 2373 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2374 .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_pwr_events_notifier, 2375 }, 2376 }; 2377 2378 /* Callback activates latch reset flow after notification about intrusion event */ 2379 static int 2380 mlxplat_mlxcpld_l1_switch_intrusion_events_handler(void *handle, enum mlxreg_hotplug_kind kind, 2381 u8 action) 2382 { 2383 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 2384 u32 regval; 2385 int err; 2386 2387 err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val); 2388 if (err) 2389 goto fail_regmap_read; 2390 2391 if (action) { 2392 dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened"); 2393 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2394 regval | MLXPLAT_CPLD_LATCH_RST_MASK); 2395 } else { 2396 dev_info(&mlxplat_dev->dev, "System latch is properly closed"); 2397 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2398 regval & ~MLXPLAT_CPLD_LATCH_RST_MASK); 2399 } 2400 2401 if (err) 2402 goto fail_regmap_write; 2403 2404 return 0; 2405 2406 fail_regmap_read: 2407 fail_regmap_write: 2408 dev_err(&mlxplat_dev->dev, "Register access failed"); 2409 return err; 2410 } 2411 2412 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_intrusion_events_notifier = { 2413 .user_handler = mlxplat_mlxcpld_l1_switch_intrusion_events_handler, 2414 }; 2415 2416 static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_data[] = { 2417 { 2418 .label = "thermal1_pdb", 2419 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2420 .mask = MLXPLAT_CPLD_THERMAL1_PDB_MASK, 2421 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2422 }, 2423 { 2424 .label = "thermal2_pdb", 2425 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2426 .mask = MLXPLAT_CPLD_THERMAL2_PDB_MASK, 2427 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2428 }, 2429 { 2430 .label = "intrusion", 2431 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2432 .mask = MLXPLAT_CPLD_INTRUSION_MASK, 2433 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2434 .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_intrusion_events_notifier, 2435 }, 2436 { 2437 .label = "pwm_pg", 2438 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2439 .mask = MLXPLAT_CPLD_PWM_PG_MASK, 2440 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2441 }, 2442 }; 2443 2444 static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { 2445 { 2446 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 2447 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2448 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2449 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 2450 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 2451 .inversed = 1, 2452 .health = false, 2453 }, 2454 { 2455 .data = mlxplat_mlxcpld_erot_ap_items_data, 2456 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2457 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2458 .mask = MLXPLAT_CPLD_EROT_MASK, 2459 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), 2460 .inversed = 1, 2461 .health = false, 2462 }, 2463 { 2464 .data = mlxplat_mlxcpld_erot_error_items_data, 2465 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2466 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2467 .mask = MLXPLAT_CPLD_EROT_MASK, 2468 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), 2469 .inversed = 1, 2470 .health = false, 2471 }, 2472 { 2473 .data = mlxplat_mlxcpld_l1_switch_pwr_events_items_data, 2474 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2475 .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, 2476 .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, 2477 .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data), 2478 .inversed = 0, 2479 .health = false, 2480 }, 2481 { 2482 .data = mlxplat_mlxcpld_l1_switch_health_events_items_data, 2483 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2484 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2485 .mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK, 2486 .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data), 2487 .inversed = 0, 2488 .health = false, 2489 .ind = 8, 2490 }, 2491 }; 2492 2493 static 2494 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { 2495 .items = mlxplat_mlxcpld_l1_switch_events_items, 2496 .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_events_items), 2497 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2498 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 2499 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2500 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, 2501 }; 2502 2503 /* Platform led default data */ 2504 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { 2505 { 2506 .label = "status:green", 2507 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2508 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2509 }, 2510 { 2511 .label = "status:red", 2512 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2513 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2514 }, 2515 { 2516 .label = "psu:green", 2517 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2518 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2519 }, 2520 { 2521 .label = "psu:red", 2522 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2523 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2524 }, 2525 { 2526 .label = "fan1:green", 2527 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2528 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2529 }, 2530 { 2531 .label = "fan1:red", 2532 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2533 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2534 }, 2535 { 2536 .label = "fan2:green", 2537 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2538 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2539 }, 2540 { 2541 .label = "fan2:red", 2542 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2543 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2544 }, 2545 { 2546 .label = "fan3:green", 2547 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2548 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2549 }, 2550 { 2551 .label = "fan3:red", 2552 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2553 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2554 }, 2555 { 2556 .label = "fan4:green", 2557 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2558 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2559 }, 2560 { 2561 .label = "fan4:red", 2562 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2563 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2564 }, 2565 }; 2566 2567 static struct mlxreg_core_platform_data mlxplat_default_led_data = { 2568 .data = mlxplat_mlxcpld_default_led_data, 2569 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data), 2570 }; 2571 2572 /* Platform led default data for water cooling */ 2573 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_wc_data[] = { 2574 { 2575 .label = "status:green", 2576 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2577 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2578 }, 2579 { 2580 .label = "status:red", 2581 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2582 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2583 }, 2584 { 2585 .label = "psu:green", 2586 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2587 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2588 }, 2589 { 2590 .label = "psu:red", 2591 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2592 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2593 }, 2594 }; 2595 2596 static struct mlxreg_core_platform_data mlxplat_default_led_wc_data = { 2597 .data = mlxplat_mlxcpld_default_led_wc_data, 2598 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_wc_data), 2599 }; 2600 2601 /* Platform led default data for water cooling Ethernet switch blade */ 2602 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_eth_wc_blade_data[] = { 2603 { 2604 .label = "status:green", 2605 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2606 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2607 }, 2608 { 2609 .label = "status:red", 2610 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2611 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2612 }, 2613 }; 2614 2615 static struct mlxreg_core_platform_data mlxplat_default_led_eth_wc_blade_data = { 2616 .data = mlxplat_mlxcpld_default_led_eth_wc_blade_data, 2617 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_eth_wc_blade_data), 2618 }; 2619 2620 /* Platform led MSN21xx system family data */ 2621 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { 2622 { 2623 .label = "status:green", 2624 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2625 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2626 }, 2627 { 2628 .label = "status:red", 2629 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2630 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2631 }, 2632 { 2633 .label = "fan:green", 2634 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2635 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2636 }, 2637 { 2638 .label = "fan:red", 2639 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2640 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2641 }, 2642 { 2643 .label = "psu1:green", 2644 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2645 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2646 }, 2647 { 2648 .label = "psu1:red", 2649 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2650 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2651 }, 2652 { 2653 .label = "psu2:green", 2654 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2655 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2656 }, 2657 { 2658 .label = "psu2:red", 2659 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2660 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2661 }, 2662 { 2663 .label = "uid:blue", 2664 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2665 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2666 }, 2667 }; 2668 2669 static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = { 2670 .data = mlxplat_mlxcpld_msn21xx_led_data, 2671 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data), 2672 }; 2673 2674 /* Platform led for default data for 200GbE systems */ 2675 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { 2676 { 2677 .label = "status:green", 2678 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2679 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2680 }, 2681 { 2682 .label = "status:orange", 2683 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2684 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2685 }, 2686 { 2687 .label = "psu:green", 2688 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2689 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2690 }, 2691 { 2692 .label = "psu:orange", 2693 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2694 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2695 }, 2696 { 2697 .label = "fan1:green", 2698 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2699 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2700 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2701 .bit = BIT(0), 2702 }, 2703 { 2704 .label = "fan1:orange", 2705 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2706 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2707 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2708 .bit = BIT(0), 2709 }, 2710 { 2711 .label = "fan2:green", 2712 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2713 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2714 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2715 .bit = BIT(1), 2716 }, 2717 { 2718 .label = "fan2:orange", 2719 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2720 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2721 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2722 .bit = BIT(1), 2723 }, 2724 { 2725 .label = "fan3:green", 2726 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2727 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2728 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2729 .bit = BIT(2), 2730 }, 2731 { 2732 .label = "fan3:orange", 2733 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2734 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2735 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2736 .bit = BIT(2), 2737 }, 2738 { 2739 .label = "fan4:green", 2740 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2741 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2742 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2743 .bit = BIT(3), 2744 }, 2745 { 2746 .label = "fan4:orange", 2747 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2748 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2749 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2750 .bit = BIT(3), 2751 }, 2752 { 2753 .label = "fan5:green", 2754 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2755 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2756 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2757 .bit = BIT(4), 2758 }, 2759 { 2760 .label = "fan5:orange", 2761 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2762 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2763 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2764 .bit = BIT(4), 2765 }, 2766 { 2767 .label = "fan6:green", 2768 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2769 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2770 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2771 .bit = BIT(5), 2772 }, 2773 { 2774 .label = "fan6:orange", 2775 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2776 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2777 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2778 .bit = BIT(5), 2779 }, 2780 { 2781 .label = "fan7:green", 2782 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2783 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2784 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2785 .bit = BIT(6), 2786 }, 2787 { 2788 .label = "fan7:orange", 2789 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2790 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2791 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2792 .bit = BIT(6), 2793 }, 2794 { 2795 .label = "uid:blue", 2796 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2797 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2798 }, 2799 }; 2800 2801 static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = { 2802 .data = mlxplat_mlxcpld_default_ng_led_data, 2803 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data), 2804 }; 2805 2806 /* Platform led for Comex based 100GbE systems */ 2807 static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = { 2808 { 2809 .label = "status:green", 2810 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2811 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2812 }, 2813 { 2814 .label = "status:red", 2815 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2816 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2817 }, 2818 { 2819 .label = "psu:green", 2820 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2821 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2822 }, 2823 { 2824 .label = "psu:red", 2825 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2826 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2827 }, 2828 { 2829 .label = "fan1:green", 2830 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2831 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2832 }, 2833 { 2834 .label = "fan1:red", 2835 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2836 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2837 }, 2838 { 2839 .label = "fan2:green", 2840 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2841 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2842 }, 2843 { 2844 .label = "fan2:red", 2845 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2846 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2847 }, 2848 { 2849 .label = "fan3:green", 2850 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2851 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2852 }, 2853 { 2854 .label = "fan3:red", 2855 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2856 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2857 }, 2858 { 2859 .label = "fan4:green", 2860 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2861 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2862 }, 2863 { 2864 .label = "fan4:red", 2865 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2866 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2867 }, 2868 { 2869 .label = "uid:blue", 2870 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2871 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2872 }, 2873 }; 2874 2875 static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = { 2876 .data = mlxplat_mlxcpld_comex_100G_led_data, 2877 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data), 2878 }; 2879 2880 /* Platform led for data for modular systems */ 2881 static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = { 2882 { 2883 .label = "status:green", 2884 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2885 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2886 }, 2887 { 2888 .label = "status:orange", 2889 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2890 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2891 }, 2892 { 2893 .label = "psu:green", 2894 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2895 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2896 }, 2897 { 2898 .label = "psu:orange", 2899 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2900 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2901 }, 2902 { 2903 .label = "fan1:green", 2904 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2905 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2906 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2907 .bit = BIT(0), 2908 }, 2909 { 2910 .label = "fan1:orange", 2911 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2912 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2913 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2914 .bit = BIT(0), 2915 }, 2916 { 2917 .label = "fan2:green", 2918 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2919 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2920 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2921 .bit = BIT(1), 2922 }, 2923 { 2924 .label = "fan2:orange", 2925 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2926 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2927 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2928 .bit = BIT(1), 2929 }, 2930 { 2931 .label = "fan3:green", 2932 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2933 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2934 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2935 .bit = BIT(2), 2936 }, 2937 { 2938 .label = "fan3:orange", 2939 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2940 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2941 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2942 .bit = BIT(2), 2943 }, 2944 { 2945 .label = "fan4:green", 2946 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2947 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2948 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2949 .bit = BIT(3), 2950 }, 2951 { 2952 .label = "fan4:orange", 2953 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2954 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2955 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2956 .bit = BIT(3), 2957 }, 2958 { 2959 .label = "fan5:green", 2960 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2961 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2962 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2963 .bit = BIT(4), 2964 }, 2965 { 2966 .label = "fan5:orange", 2967 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2968 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2969 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2970 .bit = BIT(4), 2971 }, 2972 { 2973 .label = "fan6:green", 2974 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2975 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2976 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2977 .bit = BIT(5), 2978 }, 2979 { 2980 .label = "fan6:orange", 2981 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2982 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2983 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2984 .bit = BIT(5), 2985 }, 2986 { 2987 .label = "fan7:green", 2988 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2989 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2990 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2991 .bit = BIT(6), 2992 }, 2993 { 2994 .label = "fan7:orange", 2995 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2996 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2997 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2998 .bit = BIT(6), 2999 }, 3000 { 3001 .label = "uid:blue", 3002 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3003 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3004 }, 3005 { 3006 .label = "fan_front:green", 3007 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3008 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3009 }, 3010 { 3011 .label = "fan_front:orange", 3012 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3013 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3014 }, 3015 { 3016 .label = "mgmt:green", 3017 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3018 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3019 }, 3020 { 3021 .label = "mgmt:orange", 3022 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3023 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3024 }, 3025 }; 3026 3027 static struct mlxreg_core_platform_data mlxplat_modular_led_data = { 3028 .data = mlxplat_mlxcpld_modular_led_data, 3029 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_led_data), 3030 }; 3031 3032 /* Platform led data for chassis system */ 3033 static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { 3034 { 3035 .label = "status:green", 3036 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3037 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3038 }, 3039 { 3040 .label = "status:orange", 3041 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3042 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3043 }, 3044 { 3045 .label = "fan1:green", 3046 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3047 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3048 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3049 .bit = BIT(0), 3050 }, 3051 { 3052 .label = "fan1:orange", 3053 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3054 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3055 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3056 .bit = BIT(0), 3057 }, 3058 { 3059 .label = "fan2:green", 3060 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3061 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3062 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3063 .bit = BIT(1), 3064 }, 3065 { 3066 .label = "fan2:orange", 3067 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3068 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3069 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3070 .bit = BIT(1), 3071 }, 3072 { 3073 .label = "fan3:green", 3074 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3075 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3076 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3077 .bit = BIT(2), 3078 }, 3079 { 3080 .label = "fan3:orange", 3081 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3082 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3083 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3084 .bit = BIT(2), 3085 }, 3086 { 3087 .label = "fan4:green", 3088 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3089 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3090 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3091 .bit = BIT(3), 3092 }, 3093 { 3094 .label = "fan4:orange", 3095 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3096 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3097 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3098 .bit = BIT(3), 3099 }, 3100 { 3101 .label = "fan5:green", 3102 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3103 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3104 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3105 .bit = BIT(4), 3106 }, 3107 { 3108 .label = "fan5:orange", 3109 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3110 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3111 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3112 .bit = BIT(4), 3113 }, 3114 { 3115 .label = "fan6:green", 3116 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3117 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3118 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3119 .bit = BIT(5), 3120 }, 3121 { 3122 .label = "fan6:orange", 3123 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3124 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3125 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3126 .bit = BIT(5), 3127 }, 3128 { 3129 .label = "uid:blue", 3130 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3131 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3132 }, 3133 }; 3134 3135 static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { 3136 .data = mlxplat_mlxcpld_l1_switch_led_data, 3137 .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), 3138 }; 3139 3140 /* Platform register access default */ 3141 static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { 3142 { 3143 .label = "cpld1_version", 3144 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 3145 .bit = GENMASK(7, 0), 3146 .mode = 0444, 3147 }, 3148 { 3149 .label = "cpld2_version", 3150 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 3151 .bit = GENMASK(7, 0), 3152 .mode = 0444, 3153 }, 3154 { 3155 .label = "cpld1_pn", 3156 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 3157 .bit = GENMASK(15, 0), 3158 .mode = 0444, 3159 .regnum = 2, 3160 }, 3161 { 3162 .label = "cpld2_pn", 3163 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 3164 .bit = GENMASK(15, 0), 3165 .mode = 0444, 3166 .regnum = 2, 3167 }, 3168 { 3169 .label = "cpld1_version_min", 3170 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 3171 .bit = GENMASK(7, 0), 3172 .mode = 0444, 3173 }, 3174 { 3175 .label = "cpld2_version_min", 3176 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 3177 .bit = GENMASK(7, 0), 3178 .mode = 0444, 3179 }, 3180 { 3181 .label = "reset_long_pb", 3182 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3183 .mask = GENMASK(7, 0) & ~BIT(0), 3184 .mode = 0444, 3185 }, 3186 { 3187 .label = "reset_short_pb", 3188 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3189 .mask = GENMASK(7, 0) & ~BIT(1), 3190 .mode = 0444, 3191 }, 3192 { 3193 .label = "reset_aux_pwr_or_ref", 3194 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3195 .mask = GENMASK(7, 0) & ~BIT(2), 3196 .mode = 0444, 3197 }, 3198 { 3199 .label = "reset_main_pwr_fail", 3200 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3201 .mask = GENMASK(7, 0) & ~BIT(3), 3202 .mode = 0444, 3203 }, 3204 { 3205 .label = "reset_sw_reset", 3206 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3207 .mask = GENMASK(7, 0) & ~BIT(4), 3208 .mode = 0444, 3209 }, 3210 { 3211 .label = "reset_fw_reset", 3212 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3213 .mask = GENMASK(7, 0) & ~BIT(5), 3214 .mode = 0444, 3215 }, 3216 { 3217 .label = "reset_hotswap_or_wd", 3218 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3219 .mask = GENMASK(7, 0) & ~BIT(6), 3220 .mode = 0444, 3221 }, 3222 { 3223 .label = "reset_asic_thermal", 3224 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3225 .mask = GENMASK(7, 0) & ~BIT(7), 3226 .mode = 0444, 3227 }, 3228 { 3229 .label = "psu1_on", 3230 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3231 .mask = GENMASK(7, 0) & ~BIT(0), 3232 .mode = 0200, 3233 }, 3234 { 3235 .label = "psu2_on", 3236 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3237 .mask = GENMASK(7, 0) & ~BIT(1), 3238 .mode = 0200, 3239 }, 3240 { 3241 .label = "pwr_cycle", 3242 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3243 .mask = GENMASK(7, 0) & ~BIT(2), 3244 .mode = 0200, 3245 }, 3246 { 3247 .label = "pwr_down", 3248 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3249 .mask = GENMASK(7, 0) & ~BIT(3), 3250 .mode = 0200, 3251 }, 3252 { 3253 .label = "select_iio", 3254 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 3255 .mask = GENMASK(7, 0) & ~BIT(6), 3256 .mode = 0644, 3257 }, 3258 { 3259 .label = "asic_health", 3260 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 3261 .mask = MLXPLAT_CPLD_ASIC_MASK, 3262 .bit = 1, 3263 .mode = 0444, 3264 }, 3265 }; 3266 3267 static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = { 3268 .data = mlxplat_mlxcpld_default_regs_io_data, 3269 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data), 3270 }; 3271 3272 /* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ 3273 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { 3274 { 3275 .label = "cpld1_version", 3276 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 3277 .bit = GENMASK(7, 0), 3278 .mode = 0444, 3279 }, 3280 { 3281 .label = "cpld2_version", 3282 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 3283 .bit = GENMASK(7, 0), 3284 .mode = 0444, 3285 }, 3286 { 3287 .label = "cpld1_pn", 3288 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 3289 .bit = GENMASK(15, 0), 3290 .mode = 0444, 3291 .regnum = 2, 3292 }, 3293 { 3294 .label = "cpld2_pn", 3295 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 3296 .bit = GENMASK(15, 0), 3297 .mode = 0444, 3298 .regnum = 2, 3299 }, 3300 { 3301 .label = "cpld1_version_min", 3302 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 3303 .bit = GENMASK(7, 0), 3304 .mode = 0444, 3305 }, 3306 { 3307 .label = "cpld2_version_min", 3308 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 3309 .bit = GENMASK(7, 0), 3310 .mode = 0444, 3311 }, 3312 { 3313 .label = "reset_long_pb", 3314 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3315 .mask = GENMASK(7, 0) & ~BIT(0), 3316 .mode = 0444, 3317 }, 3318 { 3319 .label = "reset_short_pb", 3320 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3321 .mask = GENMASK(7, 0) & ~BIT(1), 3322 .mode = 0444, 3323 }, 3324 { 3325 .label = "reset_aux_pwr_or_ref", 3326 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3327 .mask = GENMASK(7, 0) & ~BIT(2), 3328 .mode = 0444, 3329 }, 3330 { 3331 .label = "reset_sw_reset", 3332 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3333 .mask = GENMASK(7, 0) & ~BIT(3), 3334 .mode = 0444, 3335 }, 3336 { 3337 .label = "reset_main_pwr_fail", 3338 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3339 .mask = GENMASK(7, 0) & ~BIT(4), 3340 .mode = 0444, 3341 }, 3342 { 3343 .label = "reset_asic_thermal", 3344 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3345 .mask = GENMASK(7, 0) & ~BIT(5), 3346 .mode = 0444, 3347 }, 3348 { 3349 .label = "reset_hotswap_or_halt", 3350 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3351 .mask = GENMASK(7, 0) & ~BIT(6), 3352 .mode = 0444, 3353 }, 3354 { 3355 .label = "reset_sff_wd", 3356 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3357 .mask = GENMASK(7, 0) & ~BIT(6), 3358 .mode = 0444, 3359 }, 3360 { 3361 .label = "psu1_on", 3362 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3363 .mask = GENMASK(7, 0) & ~BIT(0), 3364 .mode = 0200, 3365 }, 3366 { 3367 .label = "psu2_on", 3368 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3369 .mask = GENMASK(7, 0) & ~BIT(1), 3370 .mode = 0200, 3371 }, 3372 { 3373 .label = "pwr_cycle", 3374 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3375 .mask = GENMASK(7, 0) & ~BIT(2), 3376 .mode = 0200, 3377 }, 3378 { 3379 .label = "pwr_down", 3380 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3381 .mask = GENMASK(7, 0) & ~BIT(3), 3382 .mode = 0200, 3383 }, 3384 { 3385 .label = "select_iio", 3386 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 3387 .mask = GENMASK(7, 0) & ~BIT(6), 3388 .mode = 0644, 3389 }, 3390 { 3391 .label = "asic_health", 3392 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 3393 .mask = MLXPLAT_CPLD_ASIC_MASK, 3394 .bit = 1, 3395 .mode = 0444, 3396 }, 3397 }; 3398 3399 static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = { 3400 .data = mlxplat_mlxcpld_msn21xx_regs_io_data, 3401 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data), 3402 }; 3403 3404 /* Platform register access for next generation systems families data */ 3405 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 3406 { 3407 .label = "cpld1_version", 3408 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 3409 .bit = GENMASK(7, 0), 3410 .mode = 0444, 3411 }, 3412 { 3413 .label = "cpld2_version", 3414 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 3415 .bit = GENMASK(7, 0), 3416 .mode = 0444, 3417 }, 3418 { 3419 .label = "cpld3_version", 3420 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 3421 .bit = GENMASK(7, 0), 3422 .mode = 0444, 3423 }, 3424 { 3425 .label = "cpld4_version", 3426 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 3427 .bit = GENMASK(7, 0), 3428 .mode = 0444, 3429 }, 3430 { 3431 .label = "cpld1_pn", 3432 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 3433 .bit = GENMASK(15, 0), 3434 .mode = 0444, 3435 .regnum = 2, 3436 }, 3437 { 3438 .label = "cpld2_pn", 3439 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 3440 .bit = GENMASK(15, 0), 3441 .mode = 0444, 3442 .regnum = 2, 3443 }, 3444 { 3445 .label = "cpld3_pn", 3446 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 3447 .bit = GENMASK(15, 0), 3448 .mode = 0444, 3449 .regnum = 2, 3450 }, 3451 { 3452 .label = "cpld4_pn", 3453 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 3454 .bit = GENMASK(15, 0), 3455 .mode = 0444, 3456 .regnum = 2, 3457 }, 3458 { 3459 .label = "cpld1_version_min", 3460 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 3461 .bit = GENMASK(7, 0), 3462 .mode = 0444, 3463 }, 3464 { 3465 .label = "cpld2_version_min", 3466 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 3467 .bit = GENMASK(7, 0), 3468 .mode = 0444, 3469 }, 3470 { 3471 .label = "cpld3_version_min", 3472 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 3473 .bit = GENMASK(7, 0), 3474 .mode = 0444, 3475 }, 3476 { 3477 .label = "cpld4_version_min", 3478 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 3479 .bit = GENMASK(7, 0), 3480 .mode = 0444, 3481 }, 3482 { 3483 .label = "asic_reset", 3484 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 3485 .mask = GENMASK(7, 0) & ~BIT(3), 3486 .mode = 0200, 3487 }, 3488 { 3489 .label = "asic2_reset", 3490 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 3491 .mask = GENMASK(7, 0) & ~BIT(2), 3492 .mode = 0200, 3493 }, 3494 { 3495 .label = "erot1_reset", 3496 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 3497 .mask = GENMASK(7, 0) & ~BIT(6), 3498 .mode = 0644, 3499 }, 3500 { 3501 .label = "erot2_reset", 3502 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 3503 .mask = GENMASK(7, 0) & ~BIT(7), 3504 .mode = 0644, 3505 }, 3506 { 3507 .label = "clk_brd_prog_en", 3508 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 3509 .mask = GENMASK(7, 0) & ~BIT(1), 3510 .mode = 0644, 3511 .secured = 1, 3512 }, 3513 { 3514 .label = "erot1_recovery", 3515 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 3516 .mask = GENMASK(7, 0) & ~BIT(6), 3517 .mode = 0644, 3518 }, 3519 { 3520 .label = "erot2_recovery", 3521 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 3522 .mask = GENMASK(7, 0) & ~BIT(7), 3523 .mode = 0644, 3524 }, 3525 { 3526 .label = "erot1_wp", 3527 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 3528 .mask = GENMASK(7, 0) & ~BIT(4), 3529 .mode = 0644, 3530 .secured = 1, 3531 }, 3532 { 3533 .label = "erot2_wp", 3534 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 3535 .mask = GENMASK(7, 0) & ~BIT(5), 3536 .mode = 0644, 3537 .secured = 1, 3538 }, 3539 { 3540 .label = "reset_long_pb", 3541 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3542 .mask = GENMASK(7, 0) & ~BIT(0), 3543 .mode = 0444, 3544 }, 3545 { 3546 .label = "reset_short_pb", 3547 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3548 .mask = GENMASK(7, 0) & ~BIT(1), 3549 .mode = 0444, 3550 }, 3551 { 3552 .label = "reset_aux_pwr_or_ref", 3553 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3554 .mask = GENMASK(7, 0) & ~BIT(2), 3555 .mode = 0444, 3556 }, 3557 { 3558 .label = "reset_from_comex", 3559 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3560 .mask = GENMASK(7, 0) & ~BIT(4), 3561 .mode = 0444, 3562 }, 3563 { 3564 .label = "reset_from_asic", 3565 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3566 .mask = GENMASK(7, 0) & ~BIT(5), 3567 .mode = 0444, 3568 }, 3569 { 3570 .label = "reset_swb_wd", 3571 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3572 .mask = GENMASK(7, 0) & ~BIT(6), 3573 .mode = 0444, 3574 }, 3575 { 3576 .label = "reset_asic_thermal", 3577 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3578 .mask = GENMASK(7, 0) & ~BIT(7), 3579 .mode = 0444, 3580 }, 3581 { 3582 .label = "reset_comex_pwr_fail", 3583 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3584 .mask = GENMASK(7, 0) & ~BIT(3), 3585 .mode = 0444, 3586 }, 3587 { 3588 .label = "reset_platform", 3589 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3590 .mask = GENMASK(7, 0) & ~BIT(4), 3591 .mode = 0444, 3592 }, 3593 { 3594 .label = "reset_soc", 3595 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3596 .mask = GENMASK(7, 0) & ~BIT(5), 3597 .mode = 0444, 3598 }, 3599 { 3600 .label = "reset_comex_wd", 3601 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3602 .mask = GENMASK(7, 0) & ~BIT(6), 3603 .mode = 0444, 3604 }, 3605 { 3606 .label = "reset_pwr_converter_fail", 3607 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3608 .mask = GENMASK(7, 0) & ~BIT(0), 3609 .mode = 0444, 3610 }, 3611 { 3612 .label = "reset_system", 3613 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3614 .mask = GENMASK(7, 0) & ~BIT(1), 3615 .mode = 0444, 3616 }, 3617 { 3618 .label = "reset_sw_pwr_off", 3619 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3620 .mask = GENMASK(7, 0) & ~BIT(2), 3621 .mode = 0444, 3622 }, 3623 { 3624 .label = "reset_comex_thermal", 3625 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3626 .mask = GENMASK(7, 0) & ~BIT(3), 3627 .mode = 0444, 3628 }, 3629 { 3630 .label = "reset_reload_bios", 3631 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3632 .mask = GENMASK(7, 0) & ~BIT(5), 3633 .mode = 0444, 3634 }, 3635 { 3636 .label = "reset_ac_pwr_fail", 3637 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3638 .mask = GENMASK(7, 0) & ~BIT(6), 3639 .mode = 0444, 3640 }, 3641 { 3642 .label = "reset_ac_ok_fail", 3643 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3644 .mask = GENMASK(7, 0) & ~BIT(7), 3645 .mode = 0444, 3646 }, 3647 { 3648 .label = "psu1_on", 3649 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3650 .mask = GENMASK(7, 0) & ~BIT(0), 3651 .mode = 0200, 3652 }, 3653 { 3654 .label = "psu2_on", 3655 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3656 .mask = GENMASK(7, 0) & ~BIT(1), 3657 .mode = 0200, 3658 }, 3659 { 3660 .label = "pwr_cycle", 3661 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3662 .mask = GENMASK(7, 0) & ~BIT(2), 3663 .mode = 0200, 3664 }, 3665 { 3666 .label = "pwr_down", 3667 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3668 .mask = GENMASK(7, 0) & ~BIT(3), 3669 .mode = 0200, 3670 }, 3671 { 3672 .label = "deep_pwr_cycle", 3673 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3674 .mask = GENMASK(7, 0) & ~BIT(5), 3675 .mode = 0200, 3676 }, 3677 { 3678 .label = "latch_reset", 3679 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3680 .mask = GENMASK(7, 0) & ~BIT(5), 3681 .mode = 0200, 3682 }, 3683 { 3684 .label = "jtag_enable", 3685 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 3686 .mask = GENMASK(7, 0) & ~BIT(4), 3687 .mode = 0644, 3688 }, 3689 { 3690 .label = "dbg1", 3691 .reg = MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET, 3692 .bit = GENMASK(7, 0), 3693 .mode = 0644, 3694 }, 3695 { 3696 .label = "dbg2", 3697 .reg = MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET, 3698 .bit = GENMASK(7, 0), 3699 .mode = 0644, 3700 }, 3701 { 3702 .label = "dbg3", 3703 .reg = MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET, 3704 .bit = GENMASK(7, 0), 3705 .mode = 0644, 3706 }, 3707 { 3708 .label = "dbg4", 3709 .reg = MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET, 3710 .bit = GENMASK(7, 0), 3711 .mode = 0644, 3712 }, 3713 { 3714 .label = "asic_health", 3715 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 3716 .mask = MLXPLAT_CPLD_ASIC_MASK, 3717 .bit = 1, 3718 .mode = 0444, 3719 }, 3720 { 3721 .label = "asic2_health", 3722 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 3723 .mask = MLXPLAT_CPLD_ASIC_MASK, 3724 .bit = 1, 3725 .mode = 0444, 3726 }, 3727 { 3728 .label = "fan_dir", 3729 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 3730 .bit = GENMASK(7, 0), 3731 .mode = 0444, 3732 }, 3733 { 3734 .label = "bios_safe_mode", 3735 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3736 .mask = GENMASK(7, 0) & ~BIT(4), 3737 .mode = 0444, 3738 }, 3739 { 3740 .label = "bios_active_image", 3741 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3742 .mask = GENMASK(7, 0) & ~BIT(5), 3743 .mode = 0444, 3744 }, 3745 { 3746 .label = "bios_auth_fail", 3747 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3748 .mask = GENMASK(7, 0) & ~BIT(6), 3749 .mode = 0444, 3750 }, 3751 { 3752 .label = "bios_upgrade_fail", 3753 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3754 .mask = GENMASK(7, 0) & ~BIT(7), 3755 .mode = 0444, 3756 }, 3757 { 3758 .label = "voltreg_update_status", 3759 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 3760 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 3761 .bit = 5, 3762 .mode = 0444, 3763 }, 3764 { 3765 .label = "pwr_converter_prog_en", 3766 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3767 .mask = GENMASK(7, 0) & ~BIT(0), 3768 .mode = 0644, 3769 .secured = 1, 3770 }, 3771 { 3772 .label = "vpd_wp", 3773 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3774 .mask = GENMASK(7, 0) & ~BIT(3), 3775 .mode = 0644, 3776 }, 3777 { 3778 .label = "pcie_asic_reset_dis", 3779 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3780 .mask = GENMASK(7, 0) & ~BIT(4), 3781 .mode = 0644, 3782 }, 3783 { 3784 .label = "erot1_ap_reset", 3785 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 3786 .mask = GENMASK(7, 0) & ~BIT(0), 3787 .mode = 0444, 3788 }, 3789 { 3790 .label = "erot2_ap_reset", 3791 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 3792 .mask = GENMASK(7, 0) & ~BIT(1), 3793 .mode = 0444, 3794 }, 3795 { 3796 .label = "clk_brd1_boot_fail", 3797 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 3798 .mask = GENMASK(7, 0) & ~BIT(4), 3799 .mode = 0444, 3800 }, 3801 { 3802 .label = "clk_brd2_boot_fail", 3803 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 3804 .mask = GENMASK(7, 0) & ~BIT(5), 3805 .mode = 0444, 3806 }, 3807 { 3808 .label = "clk_brd_fail", 3809 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 3810 .mask = GENMASK(7, 0) & ~BIT(6), 3811 .mode = 0444, 3812 }, 3813 { 3814 .label = "asic_pg_fail", 3815 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 3816 .mask = GENMASK(7, 0) & ~BIT(7), 3817 .mode = 0444, 3818 }, 3819 { 3820 .label = "spi_chnl_select", 3821 .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, 3822 .mask = GENMASK(7, 0), 3823 .bit = 1, 3824 .mode = 0644, 3825 }, 3826 { 3827 .label = "config1", 3828 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 3829 .bit = GENMASK(7, 0), 3830 .mode = 0444, 3831 }, 3832 { 3833 .label = "config2", 3834 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 3835 .bit = GENMASK(7, 0), 3836 .mode = 0444, 3837 }, 3838 { 3839 .label = "config3", 3840 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 3841 .bit = GENMASK(7, 0), 3842 .mode = 0444, 3843 }, 3844 { 3845 .label = "ufm_version", 3846 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 3847 .bit = GENMASK(7, 0), 3848 .mode = 0444, 3849 }, 3850 }; 3851 3852 static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { 3853 .data = mlxplat_mlxcpld_default_ng_regs_io_data, 3854 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), 3855 }; 3856 3857 /* Platform register access for modular systems families data */ 3858 static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { 3859 { 3860 .label = "cpld1_version", 3861 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 3862 .bit = GENMASK(7, 0), 3863 .mode = 0444, 3864 }, 3865 { 3866 .label = "cpld2_version", 3867 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 3868 .bit = GENMASK(7, 0), 3869 .mode = 0444, 3870 }, 3871 { 3872 .label = "cpld3_version", 3873 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 3874 .bit = GENMASK(7, 0), 3875 .mode = 0444, 3876 }, 3877 { 3878 .label = "cpld4_version", 3879 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 3880 .bit = GENMASK(7, 0), 3881 .mode = 0444, 3882 }, 3883 { 3884 .label = "cpld1_pn", 3885 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 3886 .bit = GENMASK(15, 0), 3887 .mode = 0444, 3888 .regnum = 2, 3889 }, 3890 { 3891 .label = "cpld2_pn", 3892 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 3893 .bit = GENMASK(15, 0), 3894 .mode = 0444, 3895 .regnum = 2, 3896 }, 3897 { 3898 .label = "cpld3_pn", 3899 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 3900 .bit = GENMASK(15, 0), 3901 .mode = 0444, 3902 .regnum = 2, 3903 }, 3904 { 3905 .label = "cpld4_pn", 3906 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 3907 .bit = GENMASK(15, 0), 3908 .mode = 0444, 3909 .regnum = 2, 3910 }, 3911 { 3912 .label = "cpld1_version_min", 3913 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 3914 .bit = GENMASK(7, 0), 3915 .mode = 0444, 3916 }, 3917 { 3918 .label = "cpld2_version_min", 3919 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 3920 .bit = GENMASK(7, 0), 3921 .mode = 0444, 3922 }, 3923 { 3924 .label = "cpld3_version_min", 3925 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 3926 .bit = GENMASK(7, 0), 3927 .mode = 0444, 3928 }, 3929 { 3930 .label = "cpld4_version_min", 3931 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 3932 .bit = GENMASK(7, 0), 3933 .mode = 0444, 3934 }, 3935 { 3936 .label = "lc1_enable", 3937 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3938 .mask = GENMASK(7, 0) & ~BIT(0), 3939 .mode = 0644, 3940 }, 3941 { 3942 .label = "lc2_enable", 3943 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3944 .mask = GENMASK(7, 0) & ~BIT(1), 3945 .mode = 0644, 3946 }, 3947 { 3948 .label = "lc3_enable", 3949 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3950 .mask = GENMASK(7, 0) & ~BIT(2), 3951 .mode = 0644, 3952 }, 3953 { 3954 .label = "lc4_enable", 3955 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3956 .mask = GENMASK(7, 0) & ~BIT(3), 3957 .mode = 0644, 3958 }, 3959 { 3960 .label = "lc5_enable", 3961 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3962 .mask = GENMASK(7, 0) & ~BIT(4), 3963 .mode = 0644, 3964 }, 3965 { 3966 .label = "lc6_enable", 3967 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3968 .mask = GENMASK(7, 0) & ~BIT(5), 3969 .mode = 0644, 3970 }, 3971 { 3972 .label = "lc7_enable", 3973 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3974 .mask = GENMASK(7, 0) & ~BIT(6), 3975 .mode = 0644, 3976 }, 3977 { 3978 .label = "lc8_enable", 3979 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3980 .mask = GENMASK(7, 0) & ~BIT(7), 3981 .mode = 0644, 3982 }, 3983 { 3984 .label = "reset_long_pb", 3985 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3986 .mask = GENMASK(7, 0) & ~BIT(0), 3987 .mode = 0444, 3988 }, 3989 { 3990 .label = "reset_short_pb", 3991 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3992 .mask = GENMASK(7, 0) & ~BIT(1), 3993 .mode = 0444, 3994 }, 3995 { 3996 .label = "reset_aux_pwr_or_fu", 3997 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3998 .mask = GENMASK(7, 0) & ~BIT(2), 3999 .mode = 0444, 4000 }, 4001 { 4002 .label = "reset_mgmt_dc_dc_pwr_fail", 4003 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4004 .mask = GENMASK(7, 0) & ~BIT(3), 4005 .mode = 0444, 4006 }, 4007 { 4008 .label = "reset_sys_comex_bios", 4009 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4010 .mask = GENMASK(7, 0) & ~BIT(5), 4011 .mode = 0444, 4012 }, 4013 { 4014 .label = "reset_sw_reset", 4015 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4016 .mask = GENMASK(7, 0) & ~BIT(0), 4017 .mode = 0444, 4018 }, 4019 { 4020 .label = "reset_aux_pwr_or_reload", 4021 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4022 .mask = GENMASK(7, 0) & ~BIT(2), 4023 .mode = 0444, 4024 }, 4025 { 4026 .label = "reset_comex_pwr_fail", 4027 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4028 .mask = GENMASK(7, 0) & ~BIT(3), 4029 .mode = 0444, 4030 }, 4031 { 4032 .label = "reset_platform", 4033 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4034 .mask = GENMASK(7, 0) & ~BIT(4), 4035 .mode = 0444, 4036 }, 4037 { 4038 .label = "reset_soc", 4039 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4040 .mask = GENMASK(7, 0) & ~BIT(5), 4041 .mode = 0444, 4042 }, 4043 { 4044 .label = "reset_pwr_off_from_carrier", 4045 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4046 .mask = GENMASK(7, 0) & ~BIT(7), 4047 .mode = 0444, 4048 }, 4049 { 4050 .label = "reset_swb_wd", 4051 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4052 .mask = GENMASK(7, 0) & ~BIT(0), 4053 .mode = 0444, 4054 }, 4055 { 4056 .label = "reset_swb_aux_pwr_or_fu", 4057 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4058 .mask = GENMASK(7, 0) & ~BIT(2), 4059 .mode = 0444, 4060 }, 4061 { 4062 .label = "reset_swb_dc_dc_pwr_fail", 4063 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4064 .mask = GENMASK(7, 0) & ~BIT(3), 4065 .mode = 0444, 4066 }, 4067 { 4068 .label = "reset_swb_12v_fail", 4069 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4070 .mask = GENMASK(7, 0) & ~BIT(4), 4071 .mode = 0444, 4072 }, 4073 { 4074 .label = "reset_system", 4075 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4076 .mask = GENMASK(7, 0) & ~BIT(5), 4077 .mode = 0444, 4078 }, 4079 { 4080 .label = "reset_thermal_spc_or_pciesw", 4081 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4082 .mask = GENMASK(7, 0) & ~BIT(7), 4083 .mode = 0444, 4084 }, 4085 { 4086 .label = "bios_safe_mode", 4087 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4088 .mask = GENMASK(7, 0) & ~BIT(4), 4089 .mode = 0444, 4090 }, 4091 { 4092 .label = "bios_active_image", 4093 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4094 .mask = GENMASK(7, 0) & ~BIT(5), 4095 .mode = 0444, 4096 }, 4097 { 4098 .label = "bios_auth_fail", 4099 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4100 .mask = GENMASK(7, 0) & ~BIT(6), 4101 .mode = 0444, 4102 }, 4103 { 4104 .label = "bios_upgrade_fail", 4105 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4106 .mask = GENMASK(7, 0) & ~BIT(7), 4107 .mode = 0444, 4108 }, 4109 { 4110 .label = "voltreg_update_status", 4111 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 4112 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 4113 .bit = 5, 4114 .mode = 0444, 4115 }, 4116 { 4117 .label = "vpd_wp", 4118 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4119 .mask = GENMASK(7, 0) & ~BIT(3), 4120 .mode = 0644, 4121 }, 4122 { 4123 .label = "pcie_asic_reset_dis", 4124 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4125 .mask = GENMASK(7, 0) & ~BIT(4), 4126 .mode = 0644, 4127 }, 4128 { 4129 .label = "shutdown_unlock", 4130 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4131 .mask = GENMASK(7, 0) & ~BIT(5), 4132 .mode = 0644, 4133 }, 4134 { 4135 .label = "lc1_rst_mask", 4136 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4137 .mask = GENMASK(7, 0) & ~BIT(0), 4138 .mode = 0200, 4139 }, 4140 { 4141 .label = "lc2_rst_mask", 4142 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4143 .mask = GENMASK(7, 0) & ~BIT(1), 4144 .mode = 0200, 4145 }, 4146 { 4147 .label = "lc3_rst_mask", 4148 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4149 .mask = GENMASK(7, 0) & ~BIT(2), 4150 .mode = 0200, 4151 }, 4152 { 4153 .label = "lc4_rst_mask", 4154 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4155 .mask = GENMASK(7, 0) & ~BIT(3), 4156 .mode = 0200, 4157 }, 4158 { 4159 .label = "lc5_rst_mask", 4160 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4161 .mask = GENMASK(7, 0) & ~BIT(4), 4162 .mode = 0200, 4163 }, 4164 { 4165 .label = "lc6_rst_mask", 4166 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4167 .mask = GENMASK(7, 0) & ~BIT(5), 4168 .mode = 0200, 4169 }, 4170 { 4171 .label = "lc7_rst_mask", 4172 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4173 .mask = GENMASK(7, 0) & ~BIT(6), 4174 .mode = 0200, 4175 }, 4176 { 4177 .label = "lc8_rst_mask", 4178 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4179 .mask = GENMASK(7, 0) & ~BIT(7), 4180 .mode = 0200, 4181 }, 4182 { 4183 .label = "psu1_on", 4184 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4185 .mask = GENMASK(7, 0) & ~BIT(0), 4186 .mode = 0200, 4187 }, 4188 { 4189 .label = "psu2_on", 4190 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4191 .mask = GENMASK(7, 0) & ~BIT(1), 4192 .mode = 0200, 4193 }, 4194 { 4195 .label = "pwr_cycle", 4196 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4197 .mask = GENMASK(7, 0) & ~BIT(2), 4198 .mode = 0200, 4199 }, 4200 { 4201 .label = "pwr_down", 4202 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4203 .mask = GENMASK(7, 0) & ~BIT(3), 4204 .mode = 0200, 4205 }, 4206 { 4207 .label = "psu3_on", 4208 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4209 .mask = GENMASK(7, 0) & ~BIT(4), 4210 .mode = 0200, 4211 }, 4212 { 4213 .label = "psu4_on", 4214 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4215 .mask = GENMASK(7, 0) & ~BIT(5), 4216 .mode = 0200, 4217 }, 4218 { 4219 .label = "auto_power_mode", 4220 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4221 .mask = GENMASK(7, 0) & ~BIT(6), 4222 .mode = 0644, 4223 }, 4224 { 4225 .label = "pm_mgmt_en", 4226 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4227 .mask = GENMASK(7, 0) & ~BIT(7), 4228 .mode = 0644, 4229 }, 4230 { 4231 .label = "jtag_enable", 4232 .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, 4233 .mask = GENMASK(3, 0), 4234 .bit = 1, 4235 .mode = 0644, 4236 }, 4237 { 4238 .label = "safe_bios_dis", 4239 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 4240 .mask = GENMASK(7, 0) & ~BIT(5), 4241 .mode = 0644, 4242 }, 4243 { 4244 .label = "safe_bios_dis_wp", 4245 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET, 4246 .mask = GENMASK(7, 0) & ~BIT(5), 4247 .mode = 0644, 4248 }, 4249 { 4250 .label = "asic_health", 4251 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 4252 .mask = MLXPLAT_CPLD_ASIC_MASK, 4253 .bit = 1, 4254 .mode = 0444, 4255 }, 4256 { 4257 .label = "fan_dir", 4258 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 4259 .bit = GENMASK(7, 0), 4260 .mode = 0444, 4261 }, 4262 { 4263 .label = "lc1_pwr", 4264 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4265 .mask = GENMASK(7, 0) & ~BIT(0), 4266 .mode = 0644, 4267 }, 4268 { 4269 .label = "lc2_pwr", 4270 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4271 .mask = GENMASK(7, 0) & ~BIT(1), 4272 .mode = 0644, 4273 }, 4274 { 4275 .label = "lc3_pwr", 4276 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4277 .mask = GENMASK(7, 0) & ~BIT(2), 4278 .mode = 0644, 4279 }, 4280 { 4281 .label = "lc4_pwr", 4282 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4283 .mask = GENMASK(7, 0) & ~BIT(3), 4284 .mode = 0644, 4285 }, 4286 { 4287 .label = "lc5_pwr", 4288 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4289 .mask = GENMASK(7, 0) & ~BIT(4), 4290 .mode = 0644, 4291 }, 4292 { 4293 .label = "lc6_pwr", 4294 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4295 .mask = GENMASK(7, 0) & ~BIT(5), 4296 .mode = 0644, 4297 }, 4298 { 4299 .label = "lc7_pwr", 4300 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4301 .mask = GENMASK(7, 0) & ~BIT(6), 4302 .mode = 0644, 4303 }, 4304 { 4305 .label = "lc8_pwr", 4306 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4307 .mask = GENMASK(7, 0) & ~BIT(7), 4308 .mode = 0644, 4309 }, 4310 { 4311 .label = "config1", 4312 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 4313 .bit = GENMASK(7, 0), 4314 .mode = 0444, 4315 }, 4316 { 4317 .label = "config2", 4318 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 4319 .bit = GENMASK(7, 0), 4320 .mode = 0444, 4321 }, 4322 { 4323 .label = "config3", 4324 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 4325 .bit = GENMASK(7, 0), 4326 .mode = 0444, 4327 }, 4328 { 4329 .label = "ufm_version", 4330 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 4331 .bit = GENMASK(7, 0), 4332 .mode = 0444, 4333 }, 4334 }; 4335 4336 static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { 4337 .data = mlxplat_mlxcpld_modular_regs_io_data, 4338 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), 4339 }; 4340 4341 /* Platform register access for chassis blade systems family data */ 4342 static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { 4343 { 4344 .label = "cpld1_version", 4345 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 4346 .bit = GENMASK(7, 0), 4347 .mode = 0444, 4348 }, 4349 { 4350 .label = "cpld1_pn", 4351 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 4352 .bit = GENMASK(15, 0), 4353 .mode = 0444, 4354 .regnum = 2, 4355 }, 4356 { 4357 .label = "cpld1_version_min", 4358 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 4359 .bit = GENMASK(7, 0), 4360 .mode = 0444, 4361 }, 4362 { 4363 .label = "reset_aux_pwr_or_ref", 4364 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4365 .mask = GENMASK(7, 0) & ~BIT(2), 4366 .mode = 0444, 4367 }, 4368 { 4369 .label = "reset_from_comex", 4370 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4371 .mask = GENMASK(7, 0) & ~BIT(4), 4372 .mode = 0444, 4373 }, 4374 { 4375 .label = "reset_comex_pwr_fail", 4376 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4377 .mask = GENMASK(7, 0) & ~BIT(3), 4378 .mode = 0444, 4379 }, 4380 { 4381 .label = "reset_platform", 4382 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4383 .mask = GENMASK(7, 0) & ~BIT(4), 4384 .mode = 0444, 4385 }, 4386 { 4387 .label = "reset_soc", 4388 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4389 .mask = GENMASK(7, 0) & ~BIT(5), 4390 .mode = 0444, 4391 }, 4392 { 4393 .label = "reset_comex_wd", 4394 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4395 .mask = GENMASK(7, 0) & ~BIT(6), 4396 .mode = 0444, 4397 }, 4398 { 4399 .label = "reset_voltmon_upgrade_fail", 4400 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4401 .mask = GENMASK(7, 0) & ~BIT(0), 4402 .mode = 0444, 4403 }, 4404 { 4405 .label = "reset_system", 4406 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4407 .mask = GENMASK(7, 0) & ~BIT(1), 4408 .mode = 0444, 4409 }, 4410 { 4411 .label = "reset_sw_pwr_off", 4412 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4413 .mask = GENMASK(7, 0) & ~BIT(2), 4414 .mode = 0444, 4415 }, 4416 { 4417 .label = "reset_comex_thermal", 4418 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4419 .mask = GENMASK(7, 0) & ~BIT(3), 4420 .mode = 0444, 4421 }, 4422 { 4423 .label = "reset_reload_bios", 4424 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4425 .mask = GENMASK(7, 0) & ~BIT(5), 4426 .mode = 0444, 4427 }, 4428 { 4429 .label = "reset_ac_pwr_fail", 4430 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4431 .mask = GENMASK(7, 0) & ~BIT(6), 4432 .mode = 0444, 4433 }, 4434 { 4435 .label = "pwr_cycle", 4436 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4437 .mask = GENMASK(7, 0) & ~BIT(2), 4438 .mode = 0200, 4439 }, 4440 { 4441 .label = "pwr_down", 4442 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4443 .mask = GENMASK(7, 0) & ~BIT(3), 4444 .mode = 0200, 4445 }, 4446 { 4447 .label = "global_wp_request", 4448 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 4449 .mask = GENMASK(7, 0) & ~BIT(0), 4450 .mode = 0644, 4451 }, 4452 { 4453 .label = "jtag_enable", 4454 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 4455 .mask = GENMASK(7, 0) & ~BIT(4), 4456 .mode = 0644, 4457 }, 4458 { 4459 .label = "comm_chnl_ready", 4460 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 4461 .mask = GENMASK(7, 0) & ~BIT(6), 4462 .mode = 0200, 4463 }, 4464 { 4465 .label = "bios_safe_mode", 4466 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4467 .mask = GENMASK(7, 0) & ~BIT(4), 4468 .mode = 0444, 4469 }, 4470 { 4471 .label = "bios_active_image", 4472 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4473 .mask = GENMASK(7, 0) & ~BIT(5), 4474 .mode = 0444, 4475 }, 4476 { 4477 .label = "bios_auth_fail", 4478 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4479 .mask = GENMASK(7, 0) & ~BIT(6), 4480 .mode = 0444, 4481 }, 4482 { 4483 .label = "bios_upgrade_fail", 4484 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4485 .mask = GENMASK(7, 0) & ~BIT(7), 4486 .mode = 0444, 4487 }, 4488 { 4489 .label = "voltreg_update_status", 4490 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 4491 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 4492 .bit = 5, 4493 .mode = 0444, 4494 }, 4495 { 4496 .label = "vpd_wp", 4497 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4498 .mask = GENMASK(7, 0) & ~BIT(3), 4499 .mode = 0644, 4500 }, 4501 { 4502 .label = "pcie_asic_reset_dis", 4503 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4504 .mask = GENMASK(7, 0) & ~BIT(4), 4505 .mode = 0644, 4506 }, 4507 { 4508 .label = "global_wp_response", 4509 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 4510 .mask = GENMASK(7, 0) & ~BIT(0), 4511 .mode = 0444, 4512 }, 4513 { 4514 .label = "config1", 4515 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 4516 .bit = GENMASK(7, 0), 4517 .mode = 0444, 4518 }, 4519 { 4520 .label = "config2", 4521 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 4522 .bit = GENMASK(7, 0), 4523 .mode = 0444, 4524 }, 4525 { 4526 .label = "config3", 4527 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 4528 .bit = GENMASK(7, 0), 4529 .mode = 0444, 4530 }, 4531 { 4532 .label = "ufm_version", 4533 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 4534 .bit = GENMASK(7, 0), 4535 .mode = 0444, 4536 }, 4537 }; 4538 4539 static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = { 4540 .data = mlxplat_mlxcpld_chassis_blade_regs_io_data, 4541 .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_regs_io_data), 4542 }; 4543 4544 /* Platform FAN default */ 4545 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { 4546 { 4547 .label = "pwm1", 4548 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, 4549 }, 4550 { 4551 .label = "pwm2", 4552 .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 4553 }, 4554 { 4555 .label = "pwm3", 4556 .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 4557 }, 4558 { 4559 .label = "pwm4", 4560 .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 4561 }, 4562 { 4563 .label = "tacho1", 4564 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, 4565 .mask = GENMASK(7, 0), 4566 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4567 .bit = BIT(0), 4568 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4569 4570 }, 4571 { 4572 .label = "tacho2", 4573 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, 4574 .mask = GENMASK(7, 0), 4575 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4576 .bit = BIT(1), 4577 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4578 }, 4579 { 4580 .label = "tacho3", 4581 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, 4582 .mask = GENMASK(7, 0), 4583 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4584 .bit = BIT(2), 4585 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4586 }, 4587 { 4588 .label = "tacho4", 4589 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, 4590 .mask = GENMASK(7, 0), 4591 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4592 .bit = BIT(3), 4593 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4594 }, 4595 { 4596 .label = "tacho5", 4597 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, 4598 .mask = GENMASK(7, 0), 4599 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4600 .bit = BIT(4), 4601 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4602 }, 4603 { 4604 .label = "tacho6", 4605 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, 4606 .mask = GENMASK(7, 0), 4607 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4608 .bit = BIT(5), 4609 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4610 }, 4611 { 4612 .label = "tacho7", 4613 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, 4614 .mask = GENMASK(7, 0), 4615 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4616 .bit = BIT(6), 4617 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4618 }, 4619 { 4620 .label = "tacho8", 4621 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, 4622 .mask = GENMASK(7, 0), 4623 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4624 .bit = BIT(7), 4625 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4626 }, 4627 { 4628 .label = "tacho9", 4629 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, 4630 .mask = GENMASK(7, 0), 4631 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 4632 .bit = BIT(0), 4633 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4634 }, 4635 { 4636 .label = "tacho10", 4637 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, 4638 .mask = GENMASK(7, 0), 4639 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 4640 .bit = BIT(1), 4641 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4642 }, 4643 { 4644 .label = "tacho11", 4645 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, 4646 .mask = GENMASK(7, 0), 4647 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 4648 .bit = BIT(2), 4649 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4650 }, 4651 { 4652 .label = "tacho12", 4653 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, 4654 .mask = GENMASK(7, 0), 4655 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 4656 .bit = BIT(3), 4657 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4658 }, 4659 { 4660 .label = "tacho13", 4661 .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET, 4662 .mask = GENMASK(7, 0), 4663 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 4664 .bit = BIT(4), 4665 }, 4666 { 4667 .label = "tacho14", 4668 .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET, 4669 .mask = GENMASK(7, 0), 4670 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 4671 .bit = BIT(5), 4672 }, 4673 { 4674 .label = "conf", 4675 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, 4676 }, 4677 }; 4678 4679 static struct mlxreg_core_platform_data mlxplat_default_fan_data = { 4680 .data = mlxplat_mlxcpld_default_fan_data, 4681 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data), 4682 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 4683 }; 4684 4685 /* Watchdog type1: hardware implementation version1 4686 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). 4687 */ 4688 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = { 4689 { 4690 .label = "action", 4691 .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 4692 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4693 .bit = 0, 4694 }, 4695 { 4696 .label = "timeout", 4697 .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET, 4698 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 4699 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 4700 }, 4701 { 4702 .label = "ping", 4703 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 4704 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 4705 .bit = 0, 4706 }, 4707 { 4708 .label = "reset", 4709 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4710 .mask = GENMASK(7, 0) & ~BIT(6), 4711 .bit = 6, 4712 }, 4713 }; 4714 4715 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = { 4716 { 4717 .label = "action", 4718 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4719 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4720 .bit = 4, 4721 }, 4722 { 4723 .label = "timeout", 4724 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 4725 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 4726 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 4727 }, 4728 { 4729 .label = "ping", 4730 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 4731 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 4732 .bit = 1, 4733 }, 4734 }; 4735 4736 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = { 4737 { 4738 .data = mlxplat_mlxcpld_wd_main_regs_type1, 4739 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1), 4740 .version = MLX_WDT_TYPE1, 4741 .identity = "mlx-wdt-main", 4742 }, 4743 { 4744 .data = mlxplat_mlxcpld_wd_aux_regs_type1, 4745 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1), 4746 .version = MLX_WDT_TYPE1, 4747 .identity = "mlx-wdt-aux", 4748 }, 4749 }; 4750 4751 /* Watchdog type2: hardware implementation version 2 4752 * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140). 4753 */ 4754 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = { 4755 { 4756 .label = "action", 4757 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4758 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4759 .bit = 0, 4760 }, 4761 { 4762 .label = "timeout", 4763 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 4764 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4765 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 4766 }, 4767 { 4768 .label = "timeleft", 4769 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET, 4770 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4771 }, 4772 { 4773 .label = "ping", 4774 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4775 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4776 .bit = 0, 4777 }, 4778 { 4779 .label = "reset", 4780 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4781 .mask = GENMASK(7, 0) & ~BIT(6), 4782 .bit = 6, 4783 }, 4784 }; 4785 4786 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = { 4787 { 4788 .label = "action", 4789 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 4790 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4791 .bit = 4, 4792 }, 4793 { 4794 .label = "timeout", 4795 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 4796 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4797 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 4798 }, 4799 { 4800 .label = "timeleft", 4801 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET, 4802 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4803 }, 4804 { 4805 .label = "ping", 4806 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 4807 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4808 .bit = 4, 4809 }, 4810 }; 4811 4812 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = { 4813 { 4814 .data = mlxplat_mlxcpld_wd_main_regs_type2, 4815 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2), 4816 .version = MLX_WDT_TYPE2, 4817 .identity = "mlx-wdt-main", 4818 }, 4819 { 4820 .data = mlxplat_mlxcpld_wd_aux_regs_type2, 4821 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2), 4822 .version = MLX_WDT_TYPE2, 4823 .identity = "mlx-wdt-aux", 4824 }, 4825 }; 4826 4827 /* Watchdog type3: hardware implementation version 3 4828 * Can be on all systems. It's differentiated by WD capability bit. 4829 * Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140) 4830 * still have only one main watchdog. 4831 */ 4832 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = { 4833 { 4834 .label = "action", 4835 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4836 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4837 .bit = 0, 4838 }, 4839 { 4840 .label = "timeout", 4841 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 4842 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4843 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 4844 }, 4845 { 4846 .label = "timeleft", 4847 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 4848 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4849 }, 4850 { 4851 .label = "ping", 4852 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4853 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4854 .bit = 0, 4855 }, 4856 { 4857 .label = "reset", 4858 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4859 .mask = GENMASK(7, 0) & ~BIT(6), 4860 .bit = 6, 4861 }, 4862 }; 4863 4864 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = { 4865 { 4866 .label = "action", 4867 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 4868 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4869 .bit = 4, 4870 }, 4871 { 4872 .label = "timeout", 4873 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 4874 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4875 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 4876 }, 4877 { 4878 .label = "timeleft", 4879 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 4880 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4881 }, 4882 { 4883 .label = "ping", 4884 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 4885 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4886 .bit = 4, 4887 }, 4888 }; 4889 4890 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = { 4891 { 4892 .data = mlxplat_mlxcpld_wd_main_regs_type3, 4893 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type3), 4894 .version = MLX_WDT_TYPE3, 4895 .identity = "mlx-wdt-main", 4896 }, 4897 { 4898 .data = mlxplat_mlxcpld_wd_aux_regs_type3, 4899 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type3), 4900 .version = MLX_WDT_TYPE3, 4901 .identity = "mlx-wdt-aux", 4902 }, 4903 }; 4904 4905 static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) 4906 { 4907 switch (reg) { 4908 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 4909 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 4910 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 4911 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 4912 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 4913 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 4914 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 4915 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 4916 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 4917 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 4918 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 4919 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 4920 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 4921 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 4922 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 4923 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 4924 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 4925 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 4926 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: 4927 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: 4928 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: 4929 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: 4930 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 4931 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 4932 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 4933 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 4934 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 4935 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: 4936 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: 4937 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: 4938 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 4939 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 4940 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 4941 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 4942 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 4943 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 4944 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 4945 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 4946 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 4947 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 4948 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: 4949 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: 4950 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: 4951 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: 4952 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: 4953 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: 4954 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 4955 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 4956 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 4957 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 4958 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 4959 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 4960 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 4961 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 4962 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 4963 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 4964 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 4965 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 4966 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 4967 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 4968 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 4969 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 4970 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 4971 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: 4972 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 4973 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 4974 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 4975 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 4976 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 4977 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 4978 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 4979 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 4980 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 4981 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 4982 case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: 4983 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: 4984 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: 4985 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: 4986 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: 4987 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 4988 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 4989 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 4990 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 4991 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 4992 return true; 4993 } 4994 return false; 4995 } 4996 4997 static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) 4998 { 4999 switch (reg) { 5000 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 5001 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 5002 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 5003 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 5004 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 5005 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: 5006 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 5007 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: 5008 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 5009 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: 5010 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 5011 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: 5012 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 5013 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 5014 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 5015 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 5016 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 5017 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 5018 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 5019 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 5020 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 5021 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 5022 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 5023 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 5024 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 5025 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: 5026 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 5027 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 5028 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 5029 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 5030 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 5031 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 5032 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 5033 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 5034 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 5035 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 5036 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 5037 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: 5038 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: 5039 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: 5040 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: 5041 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 5042 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 5043 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 5044 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 5045 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 5046 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 5047 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: 5048 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 5049 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 5050 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: 5051 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: 5052 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: 5053 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 5054 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 5055 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 5056 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: 5057 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 5058 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 5059 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 5060 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 5061 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 5062 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 5063 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 5064 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 5065 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 5066 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 5067 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 5068 case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: 5069 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: 5070 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: 5071 case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: 5072 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: 5073 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: 5074 case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET: 5075 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: 5076 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: 5077 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: 5078 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 5079 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: 5080 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 5081 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 5082 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: 5083 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 5084 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 5085 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 5086 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 5087 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 5088 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: 5089 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 5090 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 5091 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: 5092 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 5093 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 5094 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: 5095 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 5096 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 5097 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: 5098 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 5099 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 5100 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 5101 case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET: 5102 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: 5103 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 5104 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 5105 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 5106 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 5107 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 5108 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 5109 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 5110 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 5111 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 5112 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 5113 case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: 5114 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: 5115 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: 5116 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: 5117 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: 5118 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 5119 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 5120 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 5121 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 5122 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 5123 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 5124 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 5125 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 5126 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 5127 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 5128 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 5129 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 5130 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 5131 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 5132 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 5133 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 5134 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 5135 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 5136 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 5137 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 5138 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: 5139 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: 5140 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 5141 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 5142 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 5143 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 5144 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 5145 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 5146 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: 5147 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 5148 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 5149 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: 5150 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 5151 return true; 5152 } 5153 return false; 5154 } 5155 5156 static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) 5157 { 5158 switch (reg) { 5159 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 5160 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 5161 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 5162 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 5163 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 5164 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: 5165 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 5166 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: 5167 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 5168 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: 5169 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 5170 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: 5171 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 5172 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 5173 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 5174 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 5175 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 5176 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 5177 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 5178 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 5179 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 5180 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 5181 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 5182 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 5183 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 5184 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: 5185 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 5186 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 5187 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 5188 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 5189 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 5190 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 5191 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 5192 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 5193 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 5194 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: 5195 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: 5196 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: 5197 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: 5198 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 5199 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 5200 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 5201 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 5202 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 5203 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 5204 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: 5205 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 5206 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 5207 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: 5208 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: 5209 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: 5210 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 5211 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 5212 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 5213 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: 5214 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 5215 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 5216 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 5217 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 5218 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 5219 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 5220 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 5221 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 5222 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 5223 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 5224 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 5225 case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: 5226 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: 5227 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: 5228 case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: 5229 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: 5230 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: 5231 case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET: 5232 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: 5233 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: 5234 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: 5235 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 5236 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: 5237 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 5238 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 5239 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: 5240 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 5241 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 5242 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 5243 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 5244 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 5245 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: 5246 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 5247 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 5248 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: 5249 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 5250 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 5251 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: 5252 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 5253 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 5254 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: 5255 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 5256 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 5257 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 5258 case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET: 5259 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: 5260 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 5261 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 5262 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 5263 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 5264 case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: 5265 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: 5266 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: 5267 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: 5268 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: 5269 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 5270 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 5271 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 5272 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 5273 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 5274 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 5275 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 5276 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 5277 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 5278 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 5279 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 5280 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 5281 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 5282 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 5283 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 5284 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 5285 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 5286 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 5287 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 5288 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 5289 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: 5290 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: 5291 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 5292 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 5293 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 5294 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 5295 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 5296 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 5297 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: 5298 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 5299 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 5300 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: 5301 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 5302 return true; 5303 } 5304 return false; 5305 } 5306 5307 static const struct reg_default mlxplat_mlxcpld_regmap_default[] = { 5308 { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 }, 5309 { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 }, 5310 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 5311 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 5312 }; 5313 5314 static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = { 5315 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 5316 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 5317 }; 5318 5319 static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = { 5320 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, 5321 MLXPLAT_CPLD_LOW_AGGRCX_MASK }, 5322 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 5323 }; 5324 5325 static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { 5326 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 5327 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 5328 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 5329 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 5330 }; 5331 5332 static const struct reg_default mlxplat_mlxcpld_regmap_rack_switch[] = { 5333 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT }, 5334 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 5335 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 5336 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 5337 }; 5338 5339 static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = { 5340 { MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0x61 }, 5341 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 5342 { MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 0x00 }, 5343 { MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 0x00 }, 5344 { MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 0x00 }, 5345 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 5346 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 5347 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 5348 { MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET, 5349 MLXPLAT_CPLD_AGGR_MASK_LC_LOW }, 5350 }; 5351 5352 struct mlxplat_mlxcpld_regmap_context { 5353 void __iomem *base; 5354 }; 5355 5356 static struct mlxplat_mlxcpld_regmap_context mlxplat_mlxcpld_regmap_ctx; 5357 5358 static int 5359 mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val) 5360 { 5361 struct mlxplat_mlxcpld_regmap_context *ctx = context; 5362 5363 *val = ioread8(ctx->base + reg); 5364 return 0; 5365 } 5366 5367 static int 5368 mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val) 5369 { 5370 struct mlxplat_mlxcpld_regmap_context *ctx = context; 5371 5372 iowrite8(val, ctx->base + reg); 5373 return 0; 5374 } 5375 5376 static const struct regmap_config mlxplat_mlxcpld_regmap_config = { 5377 .reg_bits = 8, 5378 .val_bits = 8, 5379 .max_register = 255, 5380 .cache_type = REGCACHE_FLAT, 5381 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 5382 .readable_reg = mlxplat_mlxcpld_readable_reg, 5383 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 5384 .reg_defaults = mlxplat_mlxcpld_regmap_default, 5385 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default), 5386 .reg_read = mlxplat_mlxcpld_reg_read, 5387 .reg_write = mlxplat_mlxcpld_reg_write, 5388 }; 5389 5390 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = { 5391 .reg_bits = 8, 5392 .val_bits = 8, 5393 .max_register = 255, 5394 .cache_type = REGCACHE_FLAT, 5395 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 5396 .readable_reg = mlxplat_mlxcpld_readable_reg, 5397 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 5398 .reg_defaults = mlxplat_mlxcpld_regmap_ng, 5399 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng), 5400 .reg_read = mlxplat_mlxcpld_reg_read, 5401 .reg_write = mlxplat_mlxcpld_reg_write, 5402 }; 5403 5404 static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = { 5405 .reg_bits = 8, 5406 .val_bits = 8, 5407 .max_register = 255, 5408 .cache_type = REGCACHE_FLAT, 5409 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 5410 .readable_reg = mlxplat_mlxcpld_readable_reg, 5411 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 5412 .reg_defaults = mlxplat_mlxcpld_regmap_comex_default, 5413 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default), 5414 .reg_read = mlxplat_mlxcpld_reg_read, 5415 .reg_write = mlxplat_mlxcpld_reg_write, 5416 }; 5417 5418 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = { 5419 .reg_bits = 8, 5420 .val_bits = 8, 5421 .max_register = 255, 5422 .cache_type = REGCACHE_FLAT, 5423 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 5424 .readable_reg = mlxplat_mlxcpld_readable_reg, 5425 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 5426 .reg_defaults = mlxplat_mlxcpld_regmap_ng400, 5427 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400), 5428 .reg_read = mlxplat_mlxcpld_reg_read, 5429 .reg_write = mlxplat_mlxcpld_reg_write, 5430 }; 5431 5432 static const struct regmap_config mlxplat_mlxcpld_regmap_config_rack_switch = { 5433 .reg_bits = 8, 5434 .val_bits = 8, 5435 .max_register = 255, 5436 .cache_type = REGCACHE_FLAT, 5437 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 5438 .readable_reg = mlxplat_mlxcpld_readable_reg, 5439 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 5440 .reg_defaults = mlxplat_mlxcpld_regmap_rack_switch, 5441 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_rack_switch), 5442 .reg_read = mlxplat_mlxcpld_reg_read, 5443 .reg_write = mlxplat_mlxcpld_reg_write, 5444 }; 5445 5446 static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { 5447 .reg_bits = 8, 5448 .val_bits = 8, 5449 .max_register = 255, 5450 .cache_type = REGCACHE_FLAT, 5451 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 5452 .readable_reg = mlxplat_mlxcpld_readable_reg, 5453 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 5454 .reg_defaults = mlxplat_mlxcpld_regmap_eth_modular, 5455 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_eth_modular), 5456 .reg_read = mlxplat_mlxcpld_reg_read, 5457 .reg_write = mlxplat_mlxcpld_reg_write, 5458 }; 5459 5460 static struct resource mlxplat_mlxcpld_resources[] = { 5461 [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), 5462 }; 5463 5464 static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c; 5465 static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug; 5466 static struct mlxreg_core_platform_data *mlxplat_led; 5467 static struct mlxreg_core_platform_data *mlxplat_regs_io; 5468 static struct mlxreg_core_platform_data *mlxplat_fan; 5469 static struct mlxreg_core_platform_data 5470 *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; 5471 static const struct regmap_config *mlxplat_regmap_config; 5472 5473 /* Platform default poweroff function */ 5474 static void mlxplat_poweroff(void) 5475 { 5476 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 5477 5478 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK); 5479 } 5480 5481 static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) 5482 { 5483 int i; 5484 5485 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5486 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5487 mlxplat_mux_data = mlxplat_default_mux_data; 5488 for (i = 0; i < mlxplat_mux_num; i++) { 5489 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 5490 mlxplat_mux_data[i].n_values = 5491 ARRAY_SIZE(mlxplat_default_channels[i]); 5492 } 5493 mlxplat_hotplug = &mlxplat_mlxcpld_default_data; 5494 mlxplat_hotplug->deferred_nr = 5495 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5496 mlxplat_led = &mlxplat_default_led_data; 5497 mlxplat_regs_io = &mlxplat_default_regs_io_data; 5498 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 5499 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 5500 5501 return 1; 5502 } 5503 5504 static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi) 5505 { 5506 int i; 5507 5508 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5509 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5510 mlxplat_mux_data = mlxplat_default_mux_data; 5511 for (i = 0; i < mlxplat_mux_num; i++) { 5512 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 5513 mlxplat_mux_data[i].n_values = 5514 ARRAY_SIZE(mlxplat_default_channels[i]); 5515 } 5516 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data; 5517 mlxplat_hotplug->deferred_nr = 5518 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5519 mlxplat_led = &mlxplat_default_led_wc_data; 5520 mlxplat_regs_io = &mlxplat_default_regs_io_data; 5521 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 5522 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 5523 5524 return 1; 5525 } 5526 5527 static int __init mlxplat_dmi_default_eth_wc_blade_matched(const struct dmi_system_id *dmi) 5528 { 5529 int i; 5530 5531 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5532 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5533 mlxplat_mux_data = mlxplat_default_mux_data; 5534 for (i = 0; i < mlxplat_mux_num; i++) { 5535 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5536 mlxplat_mux_data[i].n_values = 5537 ARRAY_SIZE(mlxplat_msn21xx_channels); 5538 } 5539 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data; 5540 mlxplat_hotplug->deferred_nr = 5541 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5542 mlxplat_led = &mlxplat_default_led_eth_wc_blade_data; 5543 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5544 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5545 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5546 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5547 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 5548 5549 return 1; 5550 } 5551 5552 static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) 5553 { 5554 int i; 5555 5556 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5557 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5558 mlxplat_mux_data = mlxplat_default_mux_data; 5559 for (i = 0; i < mlxplat_mux_num; i++) { 5560 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5561 mlxplat_mux_data[i].n_values = 5562 ARRAY_SIZE(mlxplat_msn21xx_channels); 5563 } 5564 mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data; 5565 mlxplat_hotplug->deferred_nr = 5566 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5567 mlxplat_led = &mlxplat_msn21xx_led_data; 5568 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 5569 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 5570 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 5571 5572 return 1; 5573 } 5574 5575 static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) 5576 { 5577 int i; 5578 5579 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5580 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5581 mlxplat_mux_data = mlxplat_default_mux_data; 5582 for (i = 0; i < mlxplat_mux_num; i++) { 5583 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5584 mlxplat_mux_data[i].n_values = 5585 ARRAY_SIZE(mlxplat_msn21xx_channels); 5586 } 5587 mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data; 5588 mlxplat_hotplug->deferred_nr = 5589 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5590 mlxplat_led = &mlxplat_default_led_data; 5591 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 5592 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 5593 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 5594 5595 return 1; 5596 } 5597 5598 static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) 5599 { 5600 int i; 5601 5602 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5603 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5604 mlxplat_mux_data = mlxplat_default_mux_data; 5605 for (i = 0; i < mlxplat_mux_num; i++) { 5606 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5607 mlxplat_mux_data[i].n_values = 5608 ARRAY_SIZE(mlxplat_msn21xx_channels); 5609 } 5610 mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data; 5611 mlxplat_hotplug->deferred_nr = 5612 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5613 mlxplat_led = &mlxplat_msn21xx_led_data; 5614 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 5615 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 5616 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 5617 5618 return 1; 5619 } 5620 5621 static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi) 5622 { 5623 int i; 5624 5625 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5626 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5627 mlxplat_mux_data = mlxplat_default_mux_data; 5628 for (i = 0; i < mlxplat_mux_num; i++) { 5629 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5630 mlxplat_mux_data[i].n_values = 5631 ARRAY_SIZE(mlxplat_msn21xx_channels); 5632 } 5633 mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data; 5634 mlxplat_hotplug->deferred_nr = 5635 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5636 mlxplat_led = &mlxplat_default_ng_led_data; 5637 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5638 mlxplat_fan = &mlxplat_default_fan_data; 5639 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5640 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5641 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5642 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 5643 5644 return 1; 5645 } 5646 5647 static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) 5648 { 5649 int i; 5650 5651 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 5652 mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data); 5653 mlxplat_mux_data = mlxplat_extended_mux_data; 5654 for (i = 0; i < mlxplat_mux_num; i++) { 5655 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5656 mlxplat_mux_data[i].n_values = 5657 ARRAY_SIZE(mlxplat_msn21xx_channels); 5658 } 5659 mlxplat_hotplug = &mlxplat_mlxcpld_comex_data; 5660 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 5661 mlxplat_led = &mlxplat_comex_100G_led_data; 5662 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5663 mlxplat_fan = &mlxplat_default_fan_data; 5664 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5665 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5666 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 5667 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex; 5668 5669 return 1; 5670 } 5671 5672 static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) 5673 { 5674 int i; 5675 5676 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5677 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5678 mlxplat_mux_data = mlxplat_default_mux_data; 5679 for (i = 0; i < mlxplat_mux_num; i++) { 5680 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5681 mlxplat_mux_data[i].n_values = 5682 ARRAY_SIZE(mlxplat_msn21xx_channels); 5683 } 5684 mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; 5685 mlxplat_hotplug->deferred_nr = 5686 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5687 mlxplat_led = &mlxplat_default_ng_led_data; 5688 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5689 mlxplat_fan = &mlxplat_default_fan_data; 5690 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5691 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5692 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5693 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 5694 5695 return 1; 5696 } 5697 5698 static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) 5699 { 5700 int i; 5701 5702 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5703 mlxplat_mux_num = ARRAY_SIZE(mlxplat_modular_mux_data); 5704 mlxplat_mux_data = mlxplat_modular_mux_data; 5705 mlxplat_hotplug = &mlxplat_mlxcpld_modular_data; 5706 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR; 5707 mlxplat_led = &mlxplat_modular_led_data; 5708 mlxplat_regs_io = &mlxplat_modular_regs_io_data; 5709 mlxplat_fan = &mlxplat_default_fan_data; 5710 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5711 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5712 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5713 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_eth_modular; 5714 5715 return 1; 5716 } 5717 5718 static int __init mlxplat_dmi_chassis_blade_matched(const struct dmi_system_id *dmi) 5719 { 5720 int i; 5721 5722 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5723 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5724 mlxplat_mux_data = mlxplat_default_mux_data; 5725 mlxplat_hotplug = &mlxplat_mlxcpld_chassis_blade_data; 5726 mlxplat_hotplug->deferred_nr = 5727 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5728 for (i = 0; i < mlxplat_mux_num; i++) { 5729 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5730 mlxplat_mux_data[i].n_values = 5731 ARRAY_SIZE(mlxplat_msn21xx_channels); 5732 } 5733 mlxplat_regs_io = &mlxplat_chassis_blade_regs_io_data; 5734 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5735 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 5736 5737 return 1; 5738 } 5739 5740 static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dmi) 5741 { 5742 int i; 5743 5744 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5745 mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data); 5746 mlxplat_mux_data = mlxplat_rack_switch_mux_data; 5747 mlxplat_hotplug = &mlxplat_mlxcpld_rack_switch_data; 5748 mlxplat_hotplug->deferred_nr = 5749 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5750 mlxplat_led = &mlxplat_default_ng_led_data; 5751 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5752 mlxplat_fan = &mlxplat_default_fan_data; 5753 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5754 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5755 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5756 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; 5757 5758 return 1; 5759 } 5760 5761 static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi) 5762 { 5763 int i; 5764 5765 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5766 mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); 5767 mlxplat_mux_data = mlxplat_ng800_mux_data; 5768 mlxplat_hotplug = &mlxplat_mlxcpld_ng800_data; 5769 mlxplat_hotplug->deferred_nr = 5770 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5771 mlxplat_led = &mlxplat_default_ng_led_data; 5772 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5773 mlxplat_fan = &mlxplat_default_fan_data; 5774 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5775 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5776 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5777 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 5778 5779 return 1; 5780 } 5781 5782 static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) 5783 { 5784 int i; 5785 5786 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5787 mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data); 5788 mlxplat_mux_data = mlxplat_rack_switch_mux_data; 5789 mlxplat_hotplug = &mlxplat_mlxcpld_l1_switch_data; 5790 mlxplat_hotplug->deferred_nr = 5791 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5792 mlxplat_led = &mlxplat_l1_switch_led_data; 5793 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5794 mlxplat_fan = &mlxplat_default_fan_data; 5795 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5796 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5797 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5798 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; 5799 pm_power_off = mlxplat_poweroff; 5800 5801 return 1; 5802 } 5803 5804 static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { 5805 { 5806 .callback = mlxplat_dmi_default_wc_matched, 5807 .matches = { 5808 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 5809 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI138"), 5810 }, 5811 }, 5812 { 5813 .callback = mlxplat_dmi_default_matched, 5814 .matches = { 5815 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 5816 }, 5817 }, 5818 { 5819 .callback = mlxplat_dmi_msn21xx_matched, 5820 .matches = { 5821 DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"), 5822 }, 5823 }, 5824 { 5825 .callback = mlxplat_dmi_msn274x_matched, 5826 .matches = { 5827 DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"), 5828 }, 5829 }, 5830 { 5831 .callback = mlxplat_dmi_msn201x_matched, 5832 .matches = { 5833 DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"), 5834 }, 5835 }, 5836 { 5837 .callback = mlxplat_dmi_default_eth_wc_blade_matched, 5838 .matches = { 5839 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 5840 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI139"), 5841 }, 5842 }, 5843 { 5844 .callback = mlxplat_dmi_qmb7xx_matched, 5845 .matches = { 5846 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 5847 }, 5848 }, 5849 { 5850 .callback = mlxplat_dmi_qmb7xx_matched, 5851 .matches = { 5852 DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"), 5853 }, 5854 }, 5855 { 5856 .callback = mlxplat_dmi_comex_matched, 5857 .matches = { 5858 DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"), 5859 }, 5860 }, 5861 { 5862 .callback = mlxplat_dmi_rack_switch_matched, 5863 .matches = { 5864 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 5865 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI142"), 5866 }, 5867 }, 5868 { 5869 .callback = mlxplat_dmi_ng400_matched, 5870 .matches = { 5871 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 5872 }, 5873 }, 5874 { 5875 .callback = mlxplat_dmi_modular_matched, 5876 .matches = { 5877 DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"), 5878 }, 5879 }, 5880 { 5881 .callback = mlxplat_dmi_ng800_matched, 5882 .matches = { 5883 DMI_MATCH(DMI_BOARD_NAME, "VMOD0013"), 5884 }, 5885 }, 5886 { 5887 .callback = mlxplat_dmi_chassis_blade_matched, 5888 .matches = { 5889 DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"), 5890 }, 5891 }, 5892 { 5893 .callback = mlxplat_dmi_l1_switch_matched, 5894 .matches = { 5895 DMI_MATCH(DMI_BOARD_NAME, "VMOD0017"), 5896 }, 5897 }, 5898 { 5899 .callback = mlxplat_dmi_msn274x_matched, 5900 .matches = { 5901 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5902 DMI_MATCH(DMI_PRODUCT_NAME, "MSN274"), 5903 }, 5904 }, 5905 { 5906 .callback = mlxplat_dmi_default_matched, 5907 .matches = { 5908 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5909 DMI_MATCH(DMI_PRODUCT_NAME, "MSN24"), 5910 }, 5911 }, 5912 { 5913 .callback = mlxplat_dmi_default_matched, 5914 .matches = { 5915 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5916 DMI_MATCH(DMI_PRODUCT_NAME, "MSN27"), 5917 }, 5918 }, 5919 { 5920 .callback = mlxplat_dmi_default_matched, 5921 .matches = { 5922 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5923 DMI_MATCH(DMI_PRODUCT_NAME, "MSB"), 5924 }, 5925 }, 5926 { 5927 .callback = mlxplat_dmi_default_matched, 5928 .matches = { 5929 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5930 DMI_MATCH(DMI_PRODUCT_NAME, "MSX"), 5931 }, 5932 }, 5933 { 5934 .callback = mlxplat_dmi_msn21xx_matched, 5935 .matches = { 5936 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5937 DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"), 5938 }, 5939 }, 5940 { 5941 .callback = mlxplat_dmi_msn201x_matched, 5942 .matches = { 5943 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5944 DMI_MATCH(DMI_PRODUCT_NAME, "MSN201"), 5945 }, 5946 }, 5947 { 5948 .callback = mlxplat_dmi_qmb7xx_matched, 5949 .matches = { 5950 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5951 DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"), 5952 }, 5953 }, 5954 { 5955 .callback = mlxplat_dmi_qmb7xx_matched, 5956 .matches = { 5957 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5958 DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"), 5959 }, 5960 }, 5961 { 5962 .callback = mlxplat_dmi_qmb7xx_matched, 5963 .matches = { 5964 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5965 DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"), 5966 }, 5967 }, 5968 { 5969 .callback = mlxplat_dmi_qmb7xx_matched, 5970 .matches = { 5971 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5972 DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"), 5973 }, 5974 }, 5975 { } 5976 }; 5977 5978 MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table); 5979 5980 static int mlxplat_mlxcpld_verify_bus_topology(int *nr) 5981 { 5982 struct i2c_adapter *search_adap; 5983 int i, shift = 0; 5984 5985 /* Scan adapters from expected id to verify it is free. */ 5986 *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; 5987 for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i < 5988 mlxplat_max_adap_num; i++) { 5989 search_adap = i2c_get_adapter(i); 5990 if (search_adap) { 5991 i2c_put_adapter(search_adap); 5992 continue; 5993 } 5994 5995 /* Return if expected parent adapter is free. */ 5996 if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR) 5997 return 0; 5998 break; 5999 } 6000 6001 /* Return with error if free id for adapter is not found. */ 6002 if (i == mlxplat_max_adap_num) 6003 return -ENODEV; 6004 6005 /* Shift adapter ids, since expected parent adapter is not free. */ 6006 *nr = i; 6007 for (i = 0; i < mlxplat_mux_num; i++) { 6008 shift = *nr - mlxplat_mux_data[i].parent; 6009 mlxplat_mux_data[i].parent = *nr; 6010 mlxplat_mux_data[i].base_nr += shift; 6011 } 6012 6013 if (shift > 0) 6014 mlxplat_hotplug->shift_nr = shift; 6015 6016 return 0; 6017 } 6018 6019 static int mlxplat_mlxcpld_check_wd_capability(void *regmap) 6020 { 6021 u32 regval; 6022 int i, rc; 6023 6024 rc = regmap_read(regmap, MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 6025 ®val); 6026 if (rc) 6027 return rc; 6028 6029 if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) { 6030 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) { 6031 if (mlxplat_wd_data[i]) 6032 mlxplat_wd_data[i] = 6033 &mlxplat_mlxcpld_wd_set_type3[i]; 6034 } 6035 } 6036 6037 return 0; 6038 } 6039 6040 static int mlxplat_lpc_cpld_device_init(struct resource **hotplug_resources, 6041 unsigned int *hotplug_resources_size) 6042 { 6043 int err; 6044 6045 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, PLATFORM_DEVID_NONE, 6046 mlxplat_lpc_resources, 6047 ARRAY_SIZE(mlxplat_lpc_resources)); 6048 if (IS_ERR(mlxplat_dev)) 6049 return PTR_ERR(mlxplat_dev); 6050 6051 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, 6052 mlxplat_lpc_resources[1].start, 1); 6053 if (!mlxplat_mlxcpld_regmap_ctx.base) { 6054 err = -ENOMEM; 6055 goto fail_devm_ioport_map; 6056 } 6057 6058 *hotplug_resources = mlxplat_mlxcpld_resources; 6059 *hotplug_resources_size = ARRAY_SIZE(mlxplat_mlxcpld_resources); 6060 6061 return 0; 6062 6063 fail_devm_ioport_map: 6064 platform_device_unregister(mlxplat_dev); 6065 return err; 6066 } 6067 6068 static void mlxplat_lpc_cpld_device_exit(void) 6069 { 6070 platform_device_unregister(mlxplat_dev); 6071 } 6072 6073 static int 6074 mlxplat_pre_init(struct resource **hotplug_resources, unsigned int *hotplug_resources_size) 6075 { 6076 return mlxplat_lpc_cpld_device_init(hotplug_resources, hotplug_resources_size); 6077 } 6078 6079 static void mlxplat_post_exit(void) 6080 { 6081 mlxplat_lpc_cpld_device_exit(); 6082 } 6083 6084 static int mlxplat_post_init(struct mlxplat_priv *priv) 6085 { 6086 int i = 0, err; 6087 6088 /* Add hotplug driver */ 6089 if (mlxplat_hotplug) { 6090 mlxplat_hotplug->regmap = priv->regmap; 6091 priv->pdev_hotplug = 6092 platform_device_register_resndata(&mlxplat_dev->dev, 6093 "mlxreg-hotplug", PLATFORM_DEVID_NONE, 6094 priv->hotplug_resources, 6095 priv->hotplug_resources_size, 6096 mlxplat_hotplug, sizeof(*mlxplat_hotplug)); 6097 if (IS_ERR(priv->pdev_hotplug)) { 6098 err = PTR_ERR(priv->pdev_hotplug); 6099 goto fail_platform_hotplug_register; 6100 } 6101 } 6102 6103 /* Add LED driver. */ 6104 if (mlxplat_led) { 6105 mlxplat_led->regmap = priv->regmap; 6106 priv->pdev_led = 6107 platform_device_register_resndata(&mlxplat_dev->dev, "leds-mlxreg", 6108 PLATFORM_DEVID_NONE, NULL, 0, mlxplat_led, 6109 sizeof(*mlxplat_led)); 6110 if (IS_ERR(priv->pdev_led)) { 6111 err = PTR_ERR(priv->pdev_led); 6112 goto fail_platform_leds_register; 6113 } 6114 } 6115 6116 /* Add registers io access driver. */ 6117 if (mlxplat_regs_io) { 6118 mlxplat_regs_io->regmap = priv->regmap; 6119 priv->pdev_io_regs = platform_device_register_resndata(&mlxplat_dev->dev, 6120 "mlxreg-io", 6121 PLATFORM_DEVID_NONE, NULL, 6122 0, mlxplat_regs_io, 6123 sizeof(*mlxplat_regs_io)); 6124 if (IS_ERR(priv->pdev_io_regs)) { 6125 err = PTR_ERR(priv->pdev_io_regs); 6126 goto fail_platform_io_register; 6127 } 6128 } 6129 6130 /* Add FAN driver. */ 6131 if (mlxplat_fan) { 6132 mlxplat_fan->regmap = priv->regmap; 6133 priv->pdev_fan = platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-fan", 6134 PLATFORM_DEVID_NONE, NULL, 0, 6135 mlxplat_fan, 6136 sizeof(*mlxplat_fan)); 6137 if (IS_ERR(priv->pdev_fan)) { 6138 err = PTR_ERR(priv->pdev_fan); 6139 goto fail_platform_fan_register; 6140 } 6141 } 6142 6143 /* Add WD drivers. */ 6144 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); 6145 if (err) 6146 goto fail_platform_wd_register; 6147 for (i = 0; i < MLXPLAT_CPLD_WD_MAX_DEVS; i++) { 6148 if (mlxplat_wd_data[i]) { 6149 mlxplat_wd_data[i]->regmap = priv->regmap; 6150 priv->pdev_wd[i] = 6151 platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", i, 6152 NULL, 0, mlxplat_wd_data[i], 6153 sizeof(*mlxplat_wd_data[i])); 6154 if (IS_ERR(priv->pdev_wd[i])) { 6155 err = PTR_ERR(priv->pdev_wd[i]); 6156 goto fail_platform_wd_register; 6157 } 6158 } 6159 } 6160 6161 return 0; 6162 6163 fail_platform_wd_register: 6164 while (--i >= 0) 6165 platform_device_unregister(priv->pdev_wd[i]); 6166 fail_platform_fan_register: 6167 if (mlxplat_regs_io) 6168 platform_device_unregister(priv->pdev_io_regs); 6169 fail_platform_io_register: 6170 if (mlxplat_led) 6171 platform_device_unregister(priv->pdev_led); 6172 fail_platform_leds_register: 6173 if (mlxplat_hotplug) 6174 platform_device_unregister(priv->pdev_hotplug); 6175 fail_platform_hotplug_register: 6176 return err; 6177 } 6178 6179 static void mlxplat_pre_exit(struct mlxplat_priv *priv) 6180 { 6181 int i; 6182 6183 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) 6184 platform_device_unregister(priv->pdev_wd[i]); 6185 if (priv->pdev_fan) 6186 platform_device_unregister(priv->pdev_fan); 6187 if (priv->pdev_io_regs) 6188 platform_device_unregister(priv->pdev_io_regs); 6189 if (priv->pdev_led) 6190 platform_device_unregister(priv->pdev_led); 6191 if (priv->pdev_hotplug) 6192 platform_device_unregister(priv->pdev_hotplug); 6193 } 6194 6195 static int 6196 mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent, 6197 struct i2c_adapter *adapters[]) 6198 { 6199 struct mlxplat_priv *priv = handle; 6200 6201 return mlxplat_post_init(priv); 6202 } 6203 6204 static int mlxplat_i2c_mux_topolgy_init(struct mlxplat_priv *priv) 6205 { 6206 int i, err; 6207 6208 if (!priv->pdev_i2c) { 6209 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_NOTIFIED; 6210 return 0; 6211 } 6212 6213 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED; 6214 for (i = 0; i < mlxplat_mux_num; i++) { 6215 priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, 6216 "i2c-mux-reg", i, NULL, 0, 6217 &mlxplat_mux_data[i], 6218 sizeof(mlxplat_mux_data[i])); 6219 if (IS_ERR(priv->pdev_mux[i])) { 6220 err = PTR_ERR(priv->pdev_mux[i]); 6221 goto fail_platform_mux_register; 6222 } 6223 } 6224 6225 return mlxplat_i2c_mux_complition_notify(priv, NULL, NULL); 6226 6227 fail_platform_mux_register: 6228 while (--i >= 0) 6229 platform_device_unregister(priv->pdev_mux[i]); 6230 return err; 6231 } 6232 6233 static void mlxplat_i2c_mux_topolgy_exit(struct mlxplat_priv *priv) 6234 { 6235 int i; 6236 6237 for (i = mlxplat_mux_num - 1; i >= 0 ; i--) { 6238 if (priv->pdev_mux[i]) 6239 platform_device_unregister(priv->pdev_mux[i]); 6240 } 6241 6242 mlxplat_post_exit(); 6243 } 6244 6245 static int mlxplat_i2c_main_complition_notify(void *handle, int id) 6246 { 6247 struct mlxplat_priv *priv = handle; 6248 6249 return mlxplat_i2c_mux_topolgy_init(priv); 6250 } 6251 6252 static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) 6253 { 6254 int nr, err; 6255 6256 if (!mlxplat_i2c) 6257 return 0; 6258 6259 err = mlxplat_mlxcpld_verify_bus_topology(&nr); 6260 if (nr < 0) 6261 goto fail_mlxplat_mlxcpld_verify_bus_topology; 6262 6263 nr = (nr == mlxplat_max_adap_num) ? -1 : nr; 6264 mlxplat_i2c->regmap = priv->regmap; 6265 mlxplat_i2c->handle = priv; 6266 6267 priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", 6268 nr, priv->hotplug_resources, 6269 priv->hotplug_resources_size, 6270 mlxplat_i2c, sizeof(*mlxplat_i2c)); 6271 if (IS_ERR(priv->pdev_i2c)) { 6272 err = PTR_ERR(priv->pdev_i2c); 6273 goto fail_platform_i2c_register; 6274 } 6275 6276 if (priv->i2c_main_init_status == MLXPLAT_I2C_MAIN_BUS_NOTIFIED) { 6277 err = mlxplat_i2c_mux_topolgy_init(priv); 6278 if (err) 6279 goto fail_mlxplat_i2c_mux_topolgy_init; 6280 } 6281 6282 return 0; 6283 6284 fail_mlxplat_i2c_mux_topolgy_init: 6285 fail_platform_i2c_register: 6286 fail_mlxplat_mlxcpld_verify_bus_topology: 6287 return err; 6288 } 6289 6290 static void mlxplat_i2c_main_exit(struct mlxplat_priv *priv) 6291 { 6292 mlxplat_i2c_mux_topolgy_exit(priv); 6293 if (priv->pdev_i2c) 6294 platform_device_unregister(priv->pdev_i2c); 6295 } 6296 6297 static int __init mlxplat_init(void) 6298 { 6299 unsigned int hotplug_resources_size; 6300 struct resource *hotplug_resources; 6301 struct mlxplat_priv *priv; 6302 int i, err; 6303 6304 if (!dmi_check_system(mlxplat_dmi_table)) 6305 return -ENODEV; 6306 6307 err = mlxplat_pre_init(&hotplug_resources, &hotplug_resources_size); 6308 if (err) 6309 return err; 6310 6311 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), 6312 GFP_KERNEL); 6313 if (!priv) { 6314 err = -ENOMEM; 6315 goto fail_alloc; 6316 } 6317 platform_set_drvdata(mlxplat_dev, priv); 6318 priv->hotplug_resources = hotplug_resources; 6319 priv->hotplug_resources_size = hotplug_resources_size; 6320 6321 if (!mlxplat_regmap_config) 6322 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; 6323 6324 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, 6325 &mlxplat_mlxcpld_regmap_ctx, 6326 mlxplat_regmap_config); 6327 if (IS_ERR(priv->regmap)) { 6328 err = PTR_ERR(priv->regmap); 6329 goto fail_alloc; 6330 } 6331 6332 /* Set default registers. */ 6333 for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) { 6334 err = regmap_write(priv->regmap, 6335 mlxplat_regmap_config->reg_defaults[i].reg, 6336 mlxplat_regmap_config->reg_defaults[i].def); 6337 if (err) 6338 goto fail_regmap_write; 6339 } 6340 6341 err = mlxplat_i2c_main_init(priv); 6342 if (err) 6343 goto fail_mlxplat_i2c_main_init; 6344 6345 /* Sync registers with hardware. */ 6346 regcache_mark_dirty(priv->regmap); 6347 err = regcache_sync(priv->regmap); 6348 if (err) 6349 goto fail_regcache_sync; 6350 6351 return 0; 6352 6353 fail_regcache_sync: 6354 mlxplat_pre_exit(priv); 6355 fail_mlxplat_i2c_main_init: 6356 fail_regmap_write: 6357 fail_alloc: 6358 mlxplat_post_exit(); 6359 6360 return err; 6361 } 6362 module_init(mlxplat_init); 6363 6364 static void __exit mlxplat_exit(void) 6365 { 6366 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 6367 6368 if (pm_power_off) 6369 pm_power_off = NULL; 6370 mlxplat_pre_exit(priv); 6371 mlxplat_i2c_main_exit(priv); 6372 } 6373 module_exit(mlxplat_exit); 6374 6375 MODULE_AUTHOR("Vadim Pasternak (vadimp@mellanox.com)"); 6376 MODULE_DESCRIPTION("Mellanox platform driver"); 6377 MODULE_LICENSE("Dual BSD/GPL"); 6378