1 /* 2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism 3 * 4 * (C) Copyright 2008-2010 Intel Corporation 5 * Author: Sreedhara DS (sreedhara.ds@intel.com) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 * 12 * SCU running in ARC processor communicates with other entity running in IA 13 * core through IPC mechanism which in turn messaging between IA core ad SCU. 14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and 15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with 16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC) 17 * along with other APIs. 18 */ 19 #include <linux/delay.h> 20 #include <linux/errno.h> 21 #include <linux/init.h> 22 #include <linux/device.h> 23 #include <linux/pm.h> 24 #include <linux/pci.h> 25 #include <linux/interrupt.h> 26 #include <linux/sfi.h> 27 #include <linux/module.h> 28 #include <asm/mrst.h> 29 #include <asm/intel_scu_ipc.h> 30 31 /* IPC defines the following message types */ 32 #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */ 33 #define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */ 34 #define IPCMSG_FW_UPDATE 0xFE /* Firmware update */ 35 #define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */ 36 #define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */ 37 38 /* Command id associated with message IPCMSG_PCNTRL */ 39 #define IPC_CMD_PCNTRL_W 0 /* Register write */ 40 #define IPC_CMD_PCNTRL_R 1 /* Register read */ 41 #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */ 42 43 /* 44 * IPC register summary 45 * 46 * IPC register blocks are memory mapped at fixed address of 0xFF11C000 47 * To read or write information to the SCU, driver writes to IPC-1 memory 48 * mapped registers (base address 0xFF11C000). The following is the IPC 49 * mechanism 50 * 51 * 1. IA core cDMI interface claims this transaction and converts it to a 52 * Transaction Layer Packet (TLP) message which is sent across the cDMI. 53 * 54 * 2. South Complex cDMI block receives this message and writes it to 55 * the IPC-1 register block, causing an interrupt to the SCU 56 * 57 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate 58 * message handler is called within firmware. 59 */ 60 61 #define IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */ 62 #define IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */ 63 #define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */ 64 #define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */ 65 #define IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */ 66 #define IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */ 67 68 static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id); 69 static void ipc_remove(struct pci_dev *pdev); 70 71 struct intel_scu_ipc_dev { 72 struct pci_dev *pdev; 73 void __iomem *ipc_base; 74 void __iomem *i2c_base; 75 }; 76 77 static struct intel_scu_ipc_dev ipcdev; /* Only one for now */ 78 79 static int platform; /* Platform type */ 80 81 /* 82 * IPC Read Buffer (Read Only): 83 * 16 byte buffer for receiving data from SCU, if IPC command 84 * processing results in response data 85 */ 86 #define IPC_READ_BUFFER 0x90 87 88 #define IPC_I2C_CNTRL_ADDR 0 89 #define I2C_DATA_ADDR 0x04 90 91 static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */ 92 93 /* 94 * Command Register (Write Only): 95 * A write to this register results in an interrupt to the SCU core processor 96 * Format: 97 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)| 98 */ 99 static inline void ipc_command(u32 cmd) /* Send ipc command */ 100 { 101 writel(cmd, ipcdev.ipc_base); 102 } 103 104 /* 105 * IPC Write Buffer (Write Only): 106 * 16-byte buffer for sending data associated with IPC command to 107 * SCU. Size of the data is specified in the IPC_COMMAND_REG register 108 */ 109 static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */ 110 { 111 writel(data, ipcdev.ipc_base + 0x80 + offset); 112 } 113 114 /* 115 * Status Register (Read Only): 116 * Driver will read this register to get the ready/busy status of the IPC 117 * block and error status of the IPC command that was just processed by SCU 118 * Format: 119 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)| 120 */ 121 122 static inline u8 ipc_read_status(void) 123 { 124 return __raw_readl(ipcdev.ipc_base + 0x04); 125 } 126 127 static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */ 128 { 129 return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset); 130 } 131 132 static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */ 133 { 134 return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset); 135 } 136 137 static inline int busy_loop(void) /* Wait till scu status is busy */ 138 { 139 u32 status = 0; 140 u32 loop_count = 0; 141 142 status = ipc_read_status(); 143 while (status & 1) { 144 udelay(1); /* scu processing time is in few u secods */ 145 status = ipc_read_status(); 146 loop_count++; 147 /* break if scu doesn't reset busy bit after huge retry */ 148 if (loop_count > 100000) { 149 dev_err(&ipcdev.pdev->dev, "IPC timed out"); 150 return -ETIMEDOUT; 151 } 152 } 153 if ((status >> 1) & 1) 154 return -EIO; 155 156 return 0; 157 } 158 159 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */ 160 static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id) 161 { 162 int nc; 163 u32 offset = 0; 164 int err; 165 u8 cbuf[IPC_WWBUF_SIZE] = { }; 166 u32 *wbuf = (u32 *)&cbuf; 167 168 mutex_lock(&ipclock); 169 170 memset(cbuf, 0, sizeof(cbuf)); 171 172 if (ipcdev.pdev == NULL) { 173 mutex_unlock(&ipclock); 174 return -ENODEV; 175 } 176 177 for (nc = 0; nc < count; nc++, offset += 2) { 178 cbuf[offset] = addr[nc]; 179 cbuf[offset + 1] = addr[nc] >> 8; 180 } 181 182 if (id == IPC_CMD_PCNTRL_R) { 183 for (nc = 0, offset = 0; nc < count; nc++, offset += 4) 184 ipc_data_writel(wbuf[nc], offset); 185 ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op); 186 } else if (id == IPC_CMD_PCNTRL_W) { 187 for (nc = 0; nc < count; nc++, offset += 1) 188 cbuf[offset] = data[nc]; 189 for (nc = 0, offset = 0; nc < count; nc++, offset += 4) 190 ipc_data_writel(wbuf[nc], offset); 191 ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op); 192 } else if (id == IPC_CMD_PCNTRL_M) { 193 cbuf[offset] = data[0]; 194 cbuf[offset + 1] = data[1]; 195 ipc_data_writel(wbuf[0], 0); /* Write wbuff */ 196 ipc_command(4 << 16 | id << 12 | 0 << 8 | op); 197 } 198 199 err = busy_loop(); 200 if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */ 201 /* Workaround: values are read as 0 without memcpy_fromio */ 202 memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16); 203 for (nc = 0; nc < count; nc++) 204 data[nc] = ipc_data_readb(nc); 205 } 206 mutex_unlock(&ipclock); 207 return err; 208 } 209 210 /** 211 * intel_scu_ipc_ioread8 - read a word via the SCU 212 * @addr: register on SCU 213 * @data: return pointer for read byte 214 * 215 * Read a single register. Returns 0 on success or an error code. All 216 * locking between SCU accesses is handled for the caller. 217 * 218 * This function may sleep. 219 */ 220 int intel_scu_ipc_ioread8(u16 addr, u8 *data) 221 { 222 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 223 } 224 EXPORT_SYMBOL(intel_scu_ipc_ioread8); 225 226 /** 227 * intel_scu_ipc_ioread16 - read a word via the SCU 228 * @addr: register on SCU 229 * @data: return pointer for read word 230 * 231 * Read a register pair. Returns 0 on success or an error code. All 232 * locking between SCU accesses is handled for the caller. 233 * 234 * This function may sleep. 235 */ 236 int intel_scu_ipc_ioread16(u16 addr, u16 *data) 237 { 238 u16 x[2] = {addr, addr + 1 }; 239 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 240 } 241 EXPORT_SYMBOL(intel_scu_ipc_ioread16); 242 243 /** 244 * intel_scu_ipc_ioread32 - read a dword via the SCU 245 * @addr: register on SCU 246 * @data: return pointer for read dword 247 * 248 * Read four registers. Returns 0 on success or an error code. All 249 * locking between SCU accesses is handled for the caller. 250 * 251 * This function may sleep. 252 */ 253 int intel_scu_ipc_ioread32(u16 addr, u32 *data) 254 { 255 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; 256 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 257 } 258 EXPORT_SYMBOL(intel_scu_ipc_ioread32); 259 260 /** 261 * intel_scu_ipc_iowrite8 - write a byte via the SCU 262 * @addr: register on SCU 263 * @data: byte to write 264 * 265 * Write a single register. Returns 0 on success or an error code. All 266 * locking between SCU accesses is handled for the caller. 267 * 268 * This function may sleep. 269 */ 270 int intel_scu_ipc_iowrite8(u16 addr, u8 data) 271 { 272 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 273 } 274 EXPORT_SYMBOL(intel_scu_ipc_iowrite8); 275 276 /** 277 * intel_scu_ipc_iowrite16 - write a word via the SCU 278 * @addr: register on SCU 279 * @data: word to write 280 * 281 * Write two registers. Returns 0 on success or an error code. All 282 * locking between SCU accesses is handled for the caller. 283 * 284 * This function may sleep. 285 */ 286 int intel_scu_ipc_iowrite16(u16 addr, u16 data) 287 { 288 u16 x[2] = {addr, addr + 1 }; 289 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 290 } 291 EXPORT_SYMBOL(intel_scu_ipc_iowrite16); 292 293 /** 294 * intel_scu_ipc_iowrite32 - write a dword via the SCU 295 * @addr: register on SCU 296 * @data: dword to write 297 * 298 * Write four registers. Returns 0 on success or an error code. All 299 * locking between SCU accesses is handled for the caller. 300 * 301 * This function may sleep. 302 */ 303 int intel_scu_ipc_iowrite32(u16 addr, u32 data) 304 { 305 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; 306 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 307 } 308 EXPORT_SYMBOL(intel_scu_ipc_iowrite32); 309 310 /** 311 * intel_scu_ipc_readvv - read a set of registers 312 * @addr: register list 313 * @data: bytes to return 314 * @len: length of array 315 * 316 * Read registers. Returns 0 on success or an error code. All 317 * locking between SCU accesses is handled for the caller. 318 * 319 * The largest array length permitted by the hardware is 5 items. 320 * 321 * This function may sleep. 322 */ 323 int intel_scu_ipc_readv(u16 *addr, u8 *data, int len) 324 { 325 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 326 } 327 EXPORT_SYMBOL(intel_scu_ipc_readv); 328 329 /** 330 * intel_scu_ipc_writev - write a set of registers 331 * @addr: register list 332 * @data: bytes to write 333 * @len: length of array 334 * 335 * Write registers. Returns 0 on success or an error code. All 336 * locking between SCU accesses is handled for the caller. 337 * 338 * The largest array length permitted by the hardware is 5 items. 339 * 340 * This function may sleep. 341 * 342 */ 343 int intel_scu_ipc_writev(u16 *addr, u8 *data, int len) 344 { 345 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 346 } 347 EXPORT_SYMBOL(intel_scu_ipc_writev); 348 349 350 /** 351 * intel_scu_ipc_update_register - r/m/w a register 352 * @addr: register address 353 * @bits: bits to update 354 * @mask: mask of bits to update 355 * 356 * Read-modify-write power control unit register. The first data argument 357 * must be register value and second is mask value 358 * mask is a bitmap that indicates which bits to update. 359 * 0 = masked. Don't modify this bit, 1 = modify this bit. 360 * returns 0 on success or an error code. 361 * 362 * This function may sleep. Locking between SCU accesses is handled 363 * for the caller. 364 */ 365 int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask) 366 { 367 u8 data[2] = { bits, mask }; 368 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M); 369 } 370 EXPORT_SYMBOL(intel_scu_ipc_update_register); 371 372 /** 373 * intel_scu_ipc_simple_command - send a simple command 374 * @cmd: command 375 * @sub: sub type 376 * 377 * Issue a simple command to the SCU. Do not use this interface if 378 * you must then access data as any data values may be overwritten 379 * by another SCU access by the time this function returns. 380 * 381 * This function may sleep. Locking for SCU accesses is handled for 382 * the caller. 383 */ 384 int intel_scu_ipc_simple_command(int cmd, int sub) 385 { 386 int err; 387 388 mutex_lock(&ipclock); 389 if (ipcdev.pdev == NULL) { 390 mutex_unlock(&ipclock); 391 return -ENODEV; 392 } 393 ipc_command(sub << 12 | cmd); 394 err = busy_loop(); 395 mutex_unlock(&ipclock); 396 return err; 397 } 398 EXPORT_SYMBOL(intel_scu_ipc_simple_command); 399 400 /** 401 * intel_scu_ipc_command - command with data 402 * @cmd: command 403 * @sub: sub type 404 * @in: input data 405 * @inlen: input length in dwords 406 * @out: output data 407 * @outlein: output length in dwords 408 * 409 * Issue a command to the SCU which involves data transfers. Do the 410 * data copies under the lock but leave it for the caller to interpret 411 */ 412 413 int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen, 414 u32 *out, int outlen) 415 { 416 int i, err; 417 418 mutex_lock(&ipclock); 419 if (ipcdev.pdev == NULL) { 420 mutex_unlock(&ipclock); 421 return -ENODEV; 422 } 423 424 for (i = 0; i < inlen; i++) 425 ipc_data_writel(*in++, 4 * i); 426 427 ipc_command((inlen << 16) | (sub << 12) | cmd); 428 err = busy_loop(); 429 430 for (i = 0; i < outlen; i++) 431 *out++ = ipc_data_readl(4 * i); 432 433 mutex_unlock(&ipclock); 434 return err; 435 } 436 EXPORT_SYMBOL(intel_scu_ipc_command); 437 438 /*I2C commands */ 439 #define IPC_I2C_WRITE 1 /* I2C Write command */ 440 #define IPC_I2C_READ 2 /* I2C Read command */ 441 442 /** 443 * intel_scu_ipc_i2c_cntrl - I2C read/write operations 444 * @addr: I2C address + command bits 445 * @data: data to read/write 446 * 447 * Perform an an I2C read/write operation via the SCU. All locking is 448 * handled for the caller. This function may sleep. 449 * 450 * Returns an error code or 0 on success. 451 * 452 * This has to be in the IPC driver for the locking. 453 */ 454 int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data) 455 { 456 u32 cmd = 0; 457 458 mutex_lock(&ipclock); 459 if (ipcdev.pdev == NULL) { 460 mutex_unlock(&ipclock); 461 return -ENODEV; 462 } 463 cmd = (addr >> 24) & 0xFF; 464 if (cmd == IPC_I2C_READ) { 465 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); 466 /* Write not getting updated without delay */ 467 mdelay(1); 468 *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR); 469 } else if (cmd == IPC_I2C_WRITE) { 470 writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR); 471 mdelay(1); 472 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); 473 } else { 474 dev_err(&ipcdev.pdev->dev, 475 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd); 476 477 mutex_unlock(&ipclock); 478 return -EIO; 479 } 480 mutex_unlock(&ipclock); 481 return 0; 482 } 483 EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl); 484 485 /* 486 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1 487 * When ioc bit is set to 1, caller api must wait for interrupt handler called 488 * which in turn unlocks the caller api. Currently this is not used 489 * 490 * This is edge triggered so we need take no action to clear anything 491 */ 492 static irqreturn_t ioc(int irq, void *dev_id) 493 { 494 return IRQ_HANDLED; 495 } 496 497 /** 498 * ipc_probe - probe an Intel SCU IPC 499 * @dev: the PCI device matching 500 * @id: entry in the match table 501 * 502 * Enable and install an intel SCU IPC. This appears in the PCI space 503 * but uses some hard coded addresses as well. 504 */ 505 static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id) 506 { 507 int err; 508 resource_size_t pci_resource; 509 510 if (ipcdev.pdev) /* We support only one SCU */ 511 return -EBUSY; 512 513 ipcdev.pdev = pci_dev_get(dev); 514 515 err = pci_enable_device(dev); 516 if (err) 517 return err; 518 519 err = pci_request_regions(dev, "intel_scu_ipc"); 520 if (err) 521 return err; 522 523 pci_resource = pci_resource_start(dev, 0); 524 if (!pci_resource) 525 return -ENOMEM; 526 527 if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev)) 528 return -EBUSY; 529 530 ipcdev.ipc_base = ioremap_nocache(IPC_BASE_ADDR, IPC_MAX_ADDR); 531 if (!ipcdev.ipc_base) 532 return -ENOMEM; 533 534 ipcdev.i2c_base = ioremap_nocache(IPC_I2C_BASE, IPC_I2C_MAX_ADDR); 535 if (!ipcdev.i2c_base) { 536 iounmap(ipcdev.ipc_base); 537 return -ENOMEM; 538 } 539 540 intel_scu_devices_create(); 541 542 return 0; 543 } 544 545 /** 546 * ipc_remove - remove a bound IPC device 547 * @pdev: PCI device 548 * 549 * In practice the SCU is not removable but this function is also 550 * called for each device on a module unload or cleanup which is the 551 * path that will get used. 552 * 553 * Free up the mappings and release the PCI resources 554 */ 555 static void ipc_remove(struct pci_dev *pdev) 556 { 557 free_irq(pdev->irq, &ipcdev); 558 pci_release_regions(pdev); 559 pci_dev_put(ipcdev.pdev); 560 iounmap(ipcdev.ipc_base); 561 iounmap(ipcdev.i2c_base); 562 ipcdev.pdev = NULL; 563 intel_scu_devices_destroy(); 564 } 565 566 static DEFINE_PCI_DEVICE_TABLE(pci_ids) = { 567 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)}, 568 { 0,} 569 }; 570 MODULE_DEVICE_TABLE(pci, pci_ids); 571 572 static struct pci_driver ipc_driver = { 573 .name = "intel_scu_ipc", 574 .id_table = pci_ids, 575 .probe = ipc_probe, 576 .remove = ipc_remove, 577 }; 578 579 580 static int __init intel_scu_ipc_init(void) 581 { 582 platform = mrst_identify_cpu(); 583 if (platform == 0) 584 return -ENODEV; 585 return pci_register_driver(&ipc_driver); 586 } 587 588 static void __exit intel_scu_ipc_exit(void) 589 { 590 pci_unregister_driver(&ipc_driver); 591 } 592 593 MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>"); 594 MODULE_DESCRIPTION("Intel SCU IPC driver"); 595 MODULE_LICENSE("GPL"); 596 597 module_init(intel_scu_ipc_init); 598 module_exit(intel_scu_ipc_exit); 599