1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Intel SCU IPC mechanism 4 * 5 * (C) Copyright 2008-2010,2015 Intel Corporation 6 * Author: Sreedhara DS (sreedhara.ds@intel.com) 7 * 8 * SCU running in ARC processor communicates with other entity running in IA 9 * core through IPC mechanism which in turn messaging between IA core ad SCU. 10 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and 11 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with 12 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC) 13 * along with other APIs. 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/pci.h> 22 #include <linux/pm.h> 23 #include <linux/sfi.h> 24 25 #include <asm/intel-mid.h> 26 #include <asm/intel_scu_ipc.h> 27 28 /* IPC defines the following message types */ 29 #define IPCMSG_PCNTRL 0xff /* Power controller unit read/write */ 30 31 /* Command id associated with message IPCMSG_PCNTRL */ 32 #define IPC_CMD_PCNTRL_W 0 /* Register write */ 33 #define IPC_CMD_PCNTRL_R 1 /* Register read */ 34 #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */ 35 36 /* 37 * IPC register summary 38 * 39 * IPC register blocks are memory mapped at fixed address of PCI BAR 0. 40 * To read or write information to the SCU, driver writes to IPC-1 memory 41 * mapped registers. The following is the IPC mechanism 42 * 43 * 1. IA core cDMI interface claims this transaction and converts it to a 44 * Transaction Layer Packet (TLP) message which is sent across the cDMI. 45 * 46 * 2. South Complex cDMI block receives this message and writes it to 47 * the IPC-1 register block, causing an interrupt to the SCU 48 * 49 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate 50 * message handler is called within firmware. 51 */ 52 53 #define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */ 54 #define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */ 55 #define IPC_IOC 0x100 /* IPC command register IOC bit */ 56 57 struct intel_scu_ipc_dev { 58 struct device *dev; 59 void __iomem *ipc_base; 60 struct completion cmd_complete; 61 u8 irq_mode; 62 }; 63 64 static struct intel_scu_ipc_dev ipcdev; /* Only one for now */ 65 66 #define IPC_STATUS 0x04 67 #define IPC_STATUS_IRQ BIT(2) 68 #define IPC_STATUS_ERR BIT(1) 69 #define IPC_STATUS_BUSY BIT(0) 70 71 /* 72 * IPC Write/Read Buffers: 73 * 16 byte buffer for sending and receiving data to and from SCU. 74 */ 75 #define IPC_WRITE_BUFFER 0x80 76 #define IPC_READ_BUFFER 0x90 77 78 /* Timeout in jiffies */ 79 #define IPC_TIMEOUT (3 * HZ) 80 81 static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */ 82 83 /* 84 * Send ipc command 85 * Command Register (Write Only): 86 * A write to this register results in an interrupt to the SCU core processor 87 * Format: 88 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)| 89 */ 90 static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd) 91 { 92 reinit_completion(&scu->cmd_complete); 93 writel(cmd | IPC_IOC, scu->ipc_base); 94 } 95 96 /* 97 * Write ipc data 98 * IPC Write Buffer (Write Only): 99 * 16-byte buffer for sending data associated with IPC command to 100 * SCU. Size of the data is specified in the IPC_COMMAND_REG register 101 */ 102 static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset) 103 { 104 writel(data, scu->ipc_base + IPC_WRITE_BUFFER + offset); 105 } 106 107 /* 108 * Status Register (Read Only): 109 * Driver will read this register to get the ready/busy status of the IPC 110 * block and error status of the IPC command that was just processed by SCU 111 * Format: 112 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)| 113 */ 114 static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu) 115 { 116 return __raw_readl(scu->ipc_base + IPC_STATUS); 117 } 118 119 /* Read ipc byte data */ 120 static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset) 121 { 122 return readb(scu->ipc_base + IPC_READ_BUFFER + offset); 123 } 124 125 /* Read ipc u32 data */ 126 static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset) 127 { 128 return readl(scu->ipc_base + IPC_READ_BUFFER + offset); 129 } 130 131 /* Wait till scu status is busy */ 132 static inline int busy_loop(struct intel_scu_ipc_dev *scu) 133 { 134 unsigned long end = jiffies + msecs_to_jiffies(IPC_TIMEOUT); 135 136 do { 137 u32 status; 138 139 status = ipc_read_status(scu); 140 if (!(status & IPC_STATUS_BUSY)) 141 return (status & IPC_STATUS_ERR) ? -EIO : 0; 142 143 usleep_range(50, 100); 144 } while (time_before(jiffies, end)); 145 146 dev_err(scu->dev, "IPC timed out"); 147 return -ETIMEDOUT; 148 } 149 150 /* Wait till ipc ioc interrupt is received or timeout in 3 HZ */ 151 static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu) 152 { 153 int status; 154 155 if (!wait_for_completion_timeout(&scu->cmd_complete, IPC_TIMEOUT)) { 156 dev_err(scu->dev, "IPC timed out\n"); 157 return -ETIMEDOUT; 158 } 159 160 status = ipc_read_status(scu); 161 if (status & IPC_STATUS_ERR) 162 return -EIO; 163 164 return 0; 165 } 166 167 static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu) 168 { 169 return scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu); 170 } 171 172 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */ 173 static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id) 174 { 175 struct intel_scu_ipc_dev *scu = &ipcdev; 176 int nc; 177 u32 offset = 0; 178 int err; 179 u8 cbuf[IPC_WWBUF_SIZE]; 180 u32 *wbuf = (u32 *)&cbuf; 181 182 memset(cbuf, 0, sizeof(cbuf)); 183 184 mutex_lock(&ipclock); 185 186 if (scu->dev == NULL) { 187 mutex_unlock(&ipclock); 188 return -ENODEV; 189 } 190 191 for (nc = 0; nc < count; nc++, offset += 2) { 192 cbuf[offset] = addr[nc]; 193 cbuf[offset + 1] = addr[nc] >> 8; 194 } 195 196 if (id == IPC_CMD_PCNTRL_R) { 197 for (nc = 0, offset = 0; nc < count; nc++, offset += 4) 198 ipc_data_writel(scu, wbuf[nc], offset); 199 ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op); 200 } else if (id == IPC_CMD_PCNTRL_W) { 201 for (nc = 0; nc < count; nc++, offset += 1) 202 cbuf[offset] = data[nc]; 203 for (nc = 0, offset = 0; nc < count; nc++, offset += 4) 204 ipc_data_writel(scu, wbuf[nc], offset); 205 ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op); 206 } else if (id == IPC_CMD_PCNTRL_M) { 207 cbuf[offset] = data[0]; 208 cbuf[offset + 1] = data[1]; 209 ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */ 210 ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op); 211 } 212 213 err = intel_scu_ipc_check_status(scu); 214 if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */ 215 /* Workaround: values are read as 0 without memcpy_fromio */ 216 memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16); 217 for (nc = 0; nc < count; nc++) 218 data[nc] = ipc_data_readb(scu, nc); 219 } 220 mutex_unlock(&ipclock); 221 return err; 222 } 223 224 /** 225 * intel_scu_ipc_ioread8 - read a word via the SCU 226 * @addr: Register on SCU 227 * @data: Return pointer for read byte 228 * 229 * Read a single register. Returns %0 on success or an error code. All 230 * locking between SCU accesses is handled for the caller. 231 * 232 * This function may sleep. 233 */ 234 int intel_scu_ipc_ioread8(u16 addr, u8 *data) 235 { 236 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 237 } 238 EXPORT_SYMBOL(intel_scu_ipc_ioread8); 239 240 /** 241 * intel_scu_ipc_iowrite8 - write a byte via the SCU 242 * @addr: Register on SCU 243 * @data: Byte to write 244 * 245 * Write a single register. Returns %0 on success or an error code. All 246 * locking between SCU accesses is handled for the caller. 247 * 248 * This function may sleep. 249 */ 250 int intel_scu_ipc_iowrite8(u16 addr, u8 data) 251 { 252 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 253 } 254 EXPORT_SYMBOL(intel_scu_ipc_iowrite8); 255 256 /** 257 * intel_scu_ipc_readvv - read a set of registers 258 * @addr: Register list 259 * @data: Bytes to return 260 * @len: Length of array 261 * 262 * Read registers. Returns %0 on success or an error code. All locking 263 * between SCU accesses is handled for the caller. 264 * 265 * The largest array length permitted by the hardware is 5 items. 266 * 267 * This function may sleep. 268 */ 269 int intel_scu_ipc_readv(u16 *addr, u8 *data, int len) 270 { 271 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 272 } 273 EXPORT_SYMBOL(intel_scu_ipc_readv); 274 275 /** 276 * intel_scu_ipc_writev - write a set of registers 277 * @addr: Register list 278 * @data: Bytes to write 279 * @len: Length of array 280 * 281 * Write registers. Returns %0 on success or an error code. All locking 282 * between SCU accesses is handled for the caller. 283 * 284 * The largest array length permitted by the hardware is 5 items. 285 * 286 * This function may sleep. 287 */ 288 int intel_scu_ipc_writev(u16 *addr, u8 *data, int len) 289 { 290 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 291 } 292 EXPORT_SYMBOL(intel_scu_ipc_writev); 293 294 /** 295 * intel_scu_ipc_update_register - r/m/w a register 296 * @addr: Register address 297 * @bits: Bits to update 298 * @mask: Mask of bits to update 299 * 300 * Read-modify-write power control unit register. The first data argument 301 * must be register value and second is mask value mask is a bitmap that 302 * indicates which bits to update. %0 = masked. Don't modify this bit, %1 = 303 * modify this bit. returns %0 on success or an error code. 304 * 305 * This function may sleep. Locking between SCU accesses is handled 306 * for the caller. 307 */ 308 int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask) 309 { 310 u8 data[2] = { bits, mask }; 311 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M); 312 } 313 EXPORT_SYMBOL(intel_scu_ipc_update_register); 314 315 /** 316 * intel_scu_ipc_simple_command - send a simple command 317 * @cmd: Command 318 * @sub: Sub type 319 * 320 * Issue a simple command to the SCU. Do not use this interface if you must 321 * then access data as any data values may be overwritten by another SCU 322 * access by the time this function returns. 323 * 324 * This function may sleep. Locking for SCU accesses is handled for the 325 * caller. 326 */ 327 int intel_scu_ipc_simple_command(int cmd, int sub) 328 { 329 struct intel_scu_ipc_dev *scu = &ipcdev; 330 int err; 331 332 mutex_lock(&ipclock); 333 if (scu->dev == NULL) { 334 mutex_unlock(&ipclock); 335 return -ENODEV; 336 } 337 ipc_command(scu, sub << 12 | cmd); 338 err = intel_scu_ipc_check_status(scu); 339 mutex_unlock(&ipclock); 340 return err; 341 } 342 EXPORT_SYMBOL(intel_scu_ipc_simple_command); 343 344 /** 345 * intel_scu_ipc_command - command with data 346 * @cmd: Command 347 * @sub: Sub type 348 * @in: Input data 349 * @inlen: Input length in dwords 350 * @out: Output data 351 * @outlen: Output length in dwords 352 * 353 * Issue a command to the SCU which involves data transfers. Do the 354 * data copies under the lock but leave it for the caller to interpret. 355 */ 356 int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen, 357 u32 *out, int outlen) 358 { 359 struct intel_scu_ipc_dev *scu = &ipcdev; 360 int i, err; 361 362 mutex_lock(&ipclock); 363 if (scu->dev == NULL) { 364 mutex_unlock(&ipclock); 365 return -ENODEV; 366 } 367 368 for (i = 0; i < inlen; i++) 369 ipc_data_writel(scu, *in++, 4 * i); 370 371 ipc_command(scu, (inlen << 16) | (sub << 12) | cmd); 372 err = intel_scu_ipc_check_status(scu); 373 374 if (!err) { 375 for (i = 0; i < outlen; i++) 376 *out++ = ipc_data_readl(scu, 4 * i); 377 } 378 379 mutex_unlock(&ipclock); 380 return err; 381 } 382 EXPORT_SYMBOL(intel_scu_ipc_command); 383 384 /* 385 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1 386 * When ioc bit is set to 1, caller api must wait for interrupt handler called 387 * which in turn unlocks the caller api. Currently this is not used 388 * 389 * This is edge triggered so we need take no action to clear anything 390 */ 391 static irqreturn_t ioc(int irq, void *dev_id) 392 { 393 struct intel_scu_ipc_dev *scu = dev_id; 394 int status = ipc_read_status(scu); 395 396 writel(status | IPC_STATUS_IRQ, scu->ipc_base + IPC_STATUS); 397 complete(&scu->cmd_complete); 398 399 return IRQ_HANDLED; 400 } 401 402 /** 403 * ipc_probe - probe an Intel SCU IPC 404 * @pdev: the PCI device matching 405 * @id: entry in the match table 406 * 407 * Enable and install an intel SCU IPC. This appears in the PCI space 408 * but uses some hard coded addresses as well. 409 */ 410 static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id) 411 { 412 int err; 413 struct intel_scu_ipc_dev *scu = &ipcdev; 414 415 if (scu->dev) /* We support only one SCU */ 416 return -EBUSY; 417 418 err = pcim_enable_device(pdev); 419 if (err) 420 return err; 421 422 err = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev)); 423 if (err) 424 return err; 425 426 init_completion(&scu->cmd_complete); 427 428 scu->ipc_base = pcim_iomap_table(pdev)[0]; 429 430 err = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_scu_ipc", 431 scu); 432 if (err) 433 return err; 434 435 /* Assign device at last */ 436 scu->dev = &pdev->dev; 437 438 intel_scu_devices_create(); 439 440 pci_set_drvdata(pdev, scu); 441 return 0; 442 } 443 444 static const struct pci_device_id pci_ids[] = { 445 { PCI_VDEVICE(INTEL, 0x080e) }, 446 { PCI_VDEVICE(INTEL, 0x08ea) }, 447 { PCI_VDEVICE(INTEL, 0x11a0) }, 448 {} 449 }; 450 451 static struct pci_driver ipc_driver = { 452 .driver = { 453 .suppress_bind_attrs = true, 454 }, 455 .name = "intel_scu_ipc", 456 .id_table = pci_ids, 457 .probe = ipc_probe, 458 }; 459 builtin_pci_driver(ipc_driver); 460