1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Vendor Specific Extended Capabilities auxiliary bus driver 4 * 5 * Copyright (c) 2021, Intel Corporation. 6 * All Rights Reserved. 7 * 8 * Author: David E. Box <david.e.box@linux.intel.com> 9 * 10 * This driver discovers and creates auxiliary devices for Intel defined PCIe 11 * "Vendor Specific" and "Designated Vendor Specific" Extended Capabilities, 12 * VSEC and DVSEC respectively. The driver supports features on specific PCIe 13 * endpoints that exist primarily to expose them. 14 */ 15 16 #include <linux/auxiliary_bus.h> 17 #include <linux/bits.h> 18 #include <linux/delay.h> 19 #include <linux/kernel.h> 20 #include <linux/idr.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 #include <linux/types.h> 24 25 #include "vsec.h" 26 27 /* Intel DVSEC offsets */ 28 #define INTEL_DVSEC_ENTRIES 0xA 29 #define INTEL_DVSEC_SIZE 0xB 30 #define INTEL_DVSEC_TABLE 0xC 31 #define INTEL_DVSEC_TABLE_BAR(x) ((x) & GENMASK(2, 0)) 32 #define INTEL_DVSEC_TABLE_OFFSET(x) ((x) & GENMASK(31, 3)) 33 #define TABLE_OFFSET_SHIFT 3 34 #define PMT_XA_START 0 35 #define PMT_XA_MAX INT_MAX 36 #define PMT_XA_LIMIT XA_LIMIT(PMT_XA_START, PMT_XA_MAX) 37 38 static DEFINE_IDA(intel_vsec_ida); 39 static DEFINE_IDA(intel_vsec_sdsi_ida); 40 static DEFINE_XARRAY_ALLOC(auxdev_array); 41 42 /** 43 * struct intel_vsec_header - Common fields of Intel VSEC and DVSEC registers. 44 * @rev: Revision ID of the VSEC/DVSEC register space 45 * @length: Length of the VSEC/DVSEC register space 46 * @id: ID of the feature 47 * @num_entries: Number of instances of the feature 48 * @entry_size: Size of the discovery table for each feature 49 * @tbir: BAR containing the discovery tables 50 * @offset: BAR offset of start of the first discovery table 51 */ 52 struct intel_vsec_header { 53 u8 rev; 54 u16 length; 55 u16 id; 56 u8 num_entries; 57 u8 entry_size; 58 u8 tbir; 59 u32 offset; 60 }; 61 62 enum intel_vsec_id { 63 VSEC_ID_TELEMETRY = 2, 64 VSEC_ID_WATCHER = 3, 65 VSEC_ID_CRASHLOG = 4, 66 VSEC_ID_SDSI = 65, 67 VSEC_ID_TPMI = 66, 68 }; 69 70 static enum intel_vsec_id intel_vsec_allow_list[] = { 71 VSEC_ID_TELEMETRY, 72 VSEC_ID_WATCHER, 73 VSEC_ID_CRASHLOG, 74 VSEC_ID_SDSI, 75 VSEC_ID_TPMI, 76 }; 77 78 static const char *intel_vsec_name(enum intel_vsec_id id) 79 { 80 switch (id) { 81 case VSEC_ID_TELEMETRY: 82 return "telemetry"; 83 84 case VSEC_ID_WATCHER: 85 return "watcher"; 86 87 case VSEC_ID_CRASHLOG: 88 return "crashlog"; 89 90 case VSEC_ID_SDSI: 91 return "sdsi"; 92 93 case VSEC_ID_TPMI: 94 return "tpmi"; 95 96 default: 97 return NULL; 98 } 99 } 100 101 static bool intel_vsec_allowed(u16 id) 102 { 103 int i; 104 105 for (i = 0; i < ARRAY_SIZE(intel_vsec_allow_list); i++) 106 if (intel_vsec_allow_list[i] == id) 107 return true; 108 109 return false; 110 } 111 112 static bool intel_vsec_disabled(u16 id, unsigned long quirks) 113 { 114 switch (id) { 115 case VSEC_ID_WATCHER: 116 return !!(quirks & VSEC_QUIRK_NO_WATCHER); 117 118 case VSEC_ID_CRASHLOG: 119 return !!(quirks & VSEC_QUIRK_NO_CRASHLOG); 120 121 default: 122 return false; 123 } 124 } 125 126 static void intel_vsec_remove_aux(void *data) 127 { 128 auxiliary_device_delete(data); 129 auxiliary_device_uninit(data); 130 } 131 132 static DEFINE_MUTEX(vsec_ida_lock); 133 134 static void intel_vsec_dev_release(struct device *dev) 135 { 136 struct intel_vsec_device *intel_vsec_dev = dev_to_ivdev(dev); 137 138 mutex_lock(&vsec_ida_lock); 139 ida_free(intel_vsec_dev->ida, intel_vsec_dev->auxdev.id); 140 mutex_unlock(&vsec_ida_lock); 141 142 kfree(intel_vsec_dev->resource); 143 kfree(intel_vsec_dev); 144 } 145 146 int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent, 147 struct intel_vsec_device *intel_vsec_dev, 148 const char *name) 149 { 150 struct auxiliary_device *auxdev = &intel_vsec_dev->auxdev; 151 int ret, id; 152 153 mutex_lock(&vsec_ida_lock); 154 ret = ida_alloc(intel_vsec_dev->ida, GFP_KERNEL); 155 mutex_unlock(&vsec_ida_lock); 156 if (ret < 0) { 157 kfree(intel_vsec_dev->resource); 158 kfree(intel_vsec_dev); 159 return ret; 160 } 161 162 if (!parent) 163 parent = &pdev->dev; 164 165 auxdev->id = ret; 166 auxdev->name = name; 167 auxdev->dev.parent = parent; 168 auxdev->dev.release = intel_vsec_dev_release; 169 170 ret = auxiliary_device_init(auxdev); 171 if (ret < 0) { 172 mutex_lock(&vsec_ida_lock); 173 ida_free(intel_vsec_dev->ida, auxdev->id); 174 mutex_unlock(&vsec_ida_lock); 175 kfree(intel_vsec_dev->resource); 176 kfree(intel_vsec_dev); 177 return ret; 178 } 179 180 ret = auxiliary_device_add(auxdev); 181 if (ret < 0) { 182 auxiliary_device_uninit(auxdev); 183 return ret; 184 } 185 186 ret = devm_add_action_or_reset(parent, intel_vsec_remove_aux, 187 auxdev); 188 if (ret < 0) 189 return ret; 190 191 /* Add auxdev to list */ 192 ret = xa_alloc(&auxdev_array, &id, intel_vsec_dev, PMT_XA_LIMIT, 193 GFP_KERNEL); 194 if (ret) 195 return ret; 196 197 return 0; 198 } 199 EXPORT_SYMBOL_NS_GPL(intel_vsec_add_aux, INTEL_VSEC); 200 201 static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *header, 202 struct intel_vsec_platform_info *info) 203 { 204 struct intel_vsec_device *intel_vsec_dev; 205 struct resource *res, *tmp; 206 unsigned long quirks = info->quirks; 207 int i; 208 209 if (!intel_vsec_allowed(header->id) || intel_vsec_disabled(header->id, quirks)) 210 return -EINVAL; 211 212 if (!header->num_entries) { 213 dev_dbg(&pdev->dev, "Invalid 0 entry count for header id %d\n", header->id); 214 return -EINVAL; 215 } 216 217 if (!header->entry_size) { 218 dev_dbg(&pdev->dev, "Invalid 0 entry size for header id %d\n", header->id); 219 return -EINVAL; 220 } 221 222 intel_vsec_dev = kzalloc(sizeof(*intel_vsec_dev), GFP_KERNEL); 223 if (!intel_vsec_dev) 224 return -ENOMEM; 225 226 res = kcalloc(header->num_entries, sizeof(*res), GFP_KERNEL); 227 if (!res) { 228 kfree(intel_vsec_dev); 229 return -ENOMEM; 230 } 231 232 if (quirks & VSEC_QUIRK_TABLE_SHIFT) 233 header->offset >>= TABLE_OFFSET_SHIFT; 234 235 /* 236 * The DVSEC/VSEC contains the starting offset and count for a block of 237 * discovery tables. Create a resource array of these tables to the 238 * auxiliary device driver. 239 */ 240 for (i = 0, tmp = res; i < header->num_entries; i++, tmp++) { 241 tmp->start = pdev->resource[header->tbir].start + 242 header->offset + i * (header->entry_size * sizeof(u32)); 243 tmp->end = tmp->start + (header->entry_size * sizeof(u32)) - 1; 244 tmp->flags = IORESOURCE_MEM; 245 } 246 247 intel_vsec_dev->pcidev = pdev; 248 intel_vsec_dev->resource = res; 249 intel_vsec_dev->num_resources = header->num_entries; 250 intel_vsec_dev->info = info; 251 252 if (header->id == VSEC_ID_SDSI) 253 intel_vsec_dev->ida = &intel_vsec_sdsi_ida; 254 else 255 intel_vsec_dev->ida = &intel_vsec_ida; 256 257 return intel_vsec_add_aux(pdev, NULL, intel_vsec_dev, 258 intel_vsec_name(header->id)); 259 } 260 261 static bool intel_vsec_walk_header(struct pci_dev *pdev, 262 struct intel_vsec_platform_info *info) 263 { 264 struct intel_vsec_header **header = info->capabilities; 265 bool have_devices = false; 266 int ret; 267 268 for ( ; *header; header++) { 269 ret = intel_vsec_add_dev(pdev, *header, info); 270 if (ret) 271 dev_info(&pdev->dev, "Could not add device for DVSEC id %d\n", 272 (*header)->id); 273 else 274 have_devices = true; 275 } 276 277 return have_devices; 278 } 279 280 static bool intel_vsec_walk_dvsec(struct pci_dev *pdev, 281 struct intel_vsec_platform_info *info) 282 { 283 bool have_devices = false; 284 int pos = 0; 285 286 do { 287 struct intel_vsec_header header; 288 u32 table, hdr; 289 u16 vid; 290 int ret; 291 292 pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_DVSEC); 293 if (!pos) 294 break; 295 296 pci_read_config_dword(pdev, pos + PCI_DVSEC_HEADER1, &hdr); 297 vid = PCI_DVSEC_HEADER1_VID(hdr); 298 if (vid != PCI_VENDOR_ID_INTEL) 299 continue; 300 301 /* Support only revision 1 */ 302 header.rev = PCI_DVSEC_HEADER1_REV(hdr); 303 if (header.rev != 1) { 304 dev_info(&pdev->dev, "Unsupported DVSEC revision %d\n", header.rev); 305 continue; 306 } 307 308 header.length = PCI_DVSEC_HEADER1_LEN(hdr); 309 310 pci_read_config_byte(pdev, pos + INTEL_DVSEC_ENTRIES, &header.num_entries); 311 pci_read_config_byte(pdev, pos + INTEL_DVSEC_SIZE, &header.entry_size); 312 pci_read_config_dword(pdev, pos + INTEL_DVSEC_TABLE, &table); 313 314 header.tbir = INTEL_DVSEC_TABLE_BAR(table); 315 header.offset = INTEL_DVSEC_TABLE_OFFSET(table); 316 317 pci_read_config_dword(pdev, pos + PCI_DVSEC_HEADER2, &hdr); 318 header.id = PCI_DVSEC_HEADER2_ID(hdr); 319 320 ret = intel_vsec_add_dev(pdev, &header, info); 321 if (ret) 322 continue; 323 324 have_devices = true; 325 } while (true); 326 327 return have_devices; 328 } 329 330 static bool intel_vsec_walk_vsec(struct pci_dev *pdev, 331 struct intel_vsec_platform_info *info) 332 { 333 bool have_devices = false; 334 int pos = 0; 335 336 do { 337 struct intel_vsec_header header; 338 u32 table, hdr; 339 int ret; 340 341 pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_VNDR); 342 if (!pos) 343 break; 344 345 pci_read_config_dword(pdev, pos + PCI_VNDR_HEADER, &hdr); 346 347 /* Support only revision 1 */ 348 header.rev = PCI_VNDR_HEADER_REV(hdr); 349 if (header.rev != 1) { 350 dev_info(&pdev->dev, "Unsupported VSEC revision %d\n", header.rev); 351 continue; 352 } 353 354 header.id = PCI_VNDR_HEADER_ID(hdr); 355 header.length = PCI_VNDR_HEADER_LEN(hdr); 356 357 /* entry, size, and table offset are the same as DVSEC */ 358 pci_read_config_byte(pdev, pos + INTEL_DVSEC_ENTRIES, &header.num_entries); 359 pci_read_config_byte(pdev, pos + INTEL_DVSEC_SIZE, &header.entry_size); 360 pci_read_config_dword(pdev, pos + INTEL_DVSEC_TABLE, &table); 361 362 header.tbir = INTEL_DVSEC_TABLE_BAR(table); 363 header.offset = INTEL_DVSEC_TABLE_OFFSET(table); 364 365 ret = intel_vsec_add_dev(pdev, &header, info); 366 if (ret) 367 continue; 368 369 have_devices = true; 370 } while (true); 371 372 return have_devices; 373 } 374 375 static int intel_vsec_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 376 { 377 struct intel_vsec_platform_info *info; 378 bool have_devices = false; 379 int ret; 380 381 ret = pcim_enable_device(pdev); 382 if (ret) 383 return ret; 384 385 pci_save_state(pdev); 386 info = (struct intel_vsec_platform_info *)id->driver_data; 387 if (!info) 388 return -EINVAL; 389 390 if (intel_vsec_walk_dvsec(pdev, info)) 391 have_devices = true; 392 393 if (intel_vsec_walk_vsec(pdev, info)) 394 have_devices = true; 395 396 if (info && (info->quirks & VSEC_QUIRK_NO_DVSEC) && 397 intel_vsec_walk_header(pdev, info)) 398 have_devices = true; 399 400 if (!have_devices) 401 return -ENODEV; 402 403 return 0; 404 } 405 406 /* TGL info */ 407 static const struct intel_vsec_platform_info tgl_info = { 408 .quirks = VSEC_QUIRK_NO_WATCHER | VSEC_QUIRK_NO_CRASHLOG | 409 VSEC_QUIRK_TABLE_SHIFT | VSEC_QUIRK_EARLY_HW, 410 }; 411 412 /* DG1 info */ 413 static struct intel_vsec_header dg1_telemetry = { 414 .length = 0x10, 415 .id = 2, 416 .num_entries = 1, 417 .entry_size = 3, 418 .tbir = 0, 419 .offset = 0x466000, 420 }; 421 422 static struct intel_vsec_header *dg1_capabilities[] = { 423 &dg1_telemetry, 424 NULL 425 }; 426 427 static const struct intel_vsec_platform_info dg1_info = { 428 .capabilities = dg1_capabilities, 429 .quirks = VSEC_QUIRK_NO_DVSEC | VSEC_QUIRK_EARLY_HW, 430 }; 431 432 /* MTL info */ 433 static const struct intel_vsec_platform_info mtl_info = { 434 .quirks = VSEC_QUIRK_NO_WATCHER | VSEC_QUIRK_NO_CRASHLOG, 435 }; 436 437 #define PCI_DEVICE_ID_INTEL_VSEC_ADL 0x467d 438 #define PCI_DEVICE_ID_INTEL_VSEC_DG1 0x490e 439 #define PCI_DEVICE_ID_INTEL_VSEC_MTL_M 0x7d0d 440 #define PCI_DEVICE_ID_INTEL_VSEC_MTL_S 0xad0d 441 #define PCI_DEVICE_ID_INTEL_VSEC_OOBMSM 0x09a7 442 #define PCI_DEVICE_ID_INTEL_VSEC_RPL 0xa77d 443 #define PCI_DEVICE_ID_INTEL_VSEC_TGL 0x9a0d 444 static const struct pci_device_id intel_vsec_pci_ids[] = { 445 { PCI_DEVICE_DATA(INTEL, VSEC_ADL, &tgl_info) }, 446 { PCI_DEVICE_DATA(INTEL, VSEC_DG1, &dg1_info) }, 447 { PCI_DEVICE_DATA(INTEL, VSEC_MTL_M, &mtl_info) }, 448 { PCI_DEVICE_DATA(INTEL, VSEC_MTL_S, &mtl_info) }, 449 { PCI_DEVICE_DATA(INTEL, VSEC_OOBMSM, &(struct intel_vsec_platform_info) {}) }, 450 { PCI_DEVICE_DATA(INTEL, VSEC_RPL, &tgl_info) }, 451 { PCI_DEVICE_DATA(INTEL, VSEC_TGL, &tgl_info) }, 452 { } 453 }; 454 MODULE_DEVICE_TABLE(pci, intel_vsec_pci_ids); 455 456 static pci_ers_result_t intel_vsec_pci_error_detected(struct pci_dev *pdev, 457 pci_channel_state_t state) 458 { 459 pci_ers_result_t status = PCI_ERS_RESULT_NEED_RESET; 460 461 dev_info(&pdev->dev, "PCI error detected, state %d", state); 462 463 if (state == pci_channel_io_perm_failure) 464 status = PCI_ERS_RESULT_DISCONNECT; 465 else 466 pci_disable_device(pdev); 467 468 return status; 469 } 470 471 static pci_ers_result_t intel_vsec_pci_slot_reset(struct pci_dev *pdev) 472 { 473 struct intel_vsec_device *intel_vsec_dev; 474 pci_ers_result_t status = PCI_ERS_RESULT_DISCONNECT; 475 const struct pci_device_id *pci_dev_id; 476 unsigned long index; 477 478 dev_info(&pdev->dev, "Resetting PCI slot\n"); 479 480 msleep(2000); 481 if (pci_enable_device(pdev)) { 482 dev_info(&pdev->dev, 483 "Failed to re-enable PCI device after reset.\n"); 484 goto out; 485 } 486 487 status = PCI_ERS_RESULT_RECOVERED; 488 489 xa_for_each(&auxdev_array, index, intel_vsec_dev) { 490 /* check if pdev doesn't match */ 491 if (pdev != intel_vsec_dev->pcidev) 492 continue; 493 devm_release_action(&pdev->dev, intel_vsec_remove_aux, 494 &intel_vsec_dev->auxdev); 495 } 496 pci_disable_device(pdev); 497 pci_restore_state(pdev); 498 pci_dev_id = pci_match_id(intel_vsec_pci_ids, pdev); 499 intel_vsec_pci_probe(pdev, pci_dev_id); 500 501 out: 502 return status; 503 } 504 505 static void intel_vsec_pci_resume(struct pci_dev *pdev) 506 { 507 dev_info(&pdev->dev, "Done resuming PCI device\n"); 508 } 509 510 static const struct pci_error_handlers intel_vsec_pci_err_handlers = { 511 .error_detected = intel_vsec_pci_error_detected, 512 .slot_reset = intel_vsec_pci_slot_reset, 513 .resume = intel_vsec_pci_resume, 514 }; 515 516 static struct pci_driver intel_vsec_pci_driver = { 517 .name = "intel_vsec", 518 .id_table = intel_vsec_pci_ids, 519 .probe = intel_vsec_pci_probe, 520 .err_handler = &intel_vsec_pci_err_handlers, 521 }; 522 module_pci_driver(intel_vsec_pci_driver); 523 524 MODULE_AUTHOR("David E. Box <david.e.box@linux.intel.com>"); 525 MODULE_DESCRIPTION("Intel Extended Capabilities auxiliary bus driver"); 526 MODULE_LICENSE("GPL v2"); 527