1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Vendor Specific Extended Capabilities auxiliary bus driver 4 * 5 * Copyright (c) 2021, Intel Corporation. 6 * All Rights Reserved. 7 * 8 * Author: David E. Box <david.e.box@linux.intel.com> 9 * 10 * This driver discovers and creates auxiliary devices for Intel defined PCIe 11 * "Vendor Specific" and "Designated Vendor Specific" Extended Capabilities, 12 * VSEC and DVSEC respectively. The driver supports features on specific PCIe 13 * endpoints that exist primarily to expose them. 14 */ 15 16 #include <linux/auxiliary_bus.h> 17 #include <linux/bits.h> 18 #include <linux/delay.h> 19 #include <linux/kernel.h> 20 #include <linux/idr.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 #include <linux/types.h> 24 25 #include "vsec.h" 26 27 /* Intel DVSEC offsets */ 28 #define INTEL_DVSEC_ENTRIES 0xA 29 #define INTEL_DVSEC_SIZE 0xB 30 #define INTEL_DVSEC_TABLE 0xC 31 #define INTEL_DVSEC_TABLE_BAR(x) ((x) & GENMASK(2, 0)) 32 #define INTEL_DVSEC_TABLE_OFFSET(x) ((x) & GENMASK(31, 3)) 33 #define TABLE_OFFSET_SHIFT 3 34 #define PMT_XA_START 0 35 #define PMT_XA_MAX INT_MAX 36 #define PMT_XA_LIMIT XA_LIMIT(PMT_XA_START, PMT_XA_MAX) 37 38 static DEFINE_IDA(intel_vsec_ida); 39 static DEFINE_IDA(intel_vsec_sdsi_ida); 40 static DEFINE_XARRAY_ALLOC(auxdev_array); 41 42 /** 43 * struct intel_vsec_header - Common fields of Intel VSEC and DVSEC registers. 44 * @rev: Revision ID of the VSEC/DVSEC register space 45 * @length: Length of the VSEC/DVSEC register space 46 * @id: ID of the feature 47 * @num_entries: Number of instances of the feature 48 * @entry_size: Size of the discovery table for each feature 49 * @tbir: BAR containing the discovery tables 50 * @offset: BAR offset of start of the first discovery table 51 */ 52 struct intel_vsec_header { 53 u8 rev; 54 u16 length; 55 u16 id; 56 u8 num_entries; 57 u8 entry_size; 58 u8 tbir; 59 u32 offset; 60 }; 61 62 enum intel_vsec_id { 63 VSEC_ID_TELEMETRY = 2, 64 VSEC_ID_WATCHER = 3, 65 VSEC_ID_CRASHLOG = 4, 66 VSEC_ID_SDSI = 65, 67 VSEC_ID_TPMI = 66, 68 }; 69 70 static const char *intel_vsec_name(enum intel_vsec_id id) 71 { 72 switch (id) { 73 case VSEC_ID_TELEMETRY: 74 return "telemetry"; 75 76 case VSEC_ID_WATCHER: 77 return "watcher"; 78 79 case VSEC_ID_CRASHLOG: 80 return "crashlog"; 81 82 case VSEC_ID_SDSI: 83 return "sdsi"; 84 85 case VSEC_ID_TPMI: 86 return "tpmi"; 87 88 default: 89 return NULL; 90 } 91 } 92 93 static bool intel_vsec_supported(u16 id, unsigned long caps) 94 { 95 switch (id) { 96 case VSEC_ID_TELEMETRY: 97 return !!(caps & VSEC_CAP_TELEMETRY); 98 case VSEC_ID_WATCHER: 99 return !!(caps & VSEC_CAP_WATCHER); 100 case VSEC_ID_CRASHLOG: 101 return !!(caps & VSEC_CAP_CRASHLOG); 102 case VSEC_ID_SDSI: 103 return !!(caps & VSEC_CAP_SDSI); 104 case VSEC_ID_TPMI: 105 return !!(caps & VSEC_CAP_TPMI); 106 default: 107 return false; 108 } 109 } 110 111 static void intel_vsec_remove_aux(void *data) 112 { 113 auxiliary_device_delete(data); 114 auxiliary_device_uninit(data); 115 } 116 117 static DEFINE_MUTEX(vsec_ida_lock); 118 119 static void intel_vsec_dev_release(struct device *dev) 120 { 121 struct intel_vsec_device *intel_vsec_dev = dev_to_ivdev(dev); 122 123 mutex_lock(&vsec_ida_lock); 124 ida_free(intel_vsec_dev->ida, intel_vsec_dev->auxdev.id); 125 mutex_unlock(&vsec_ida_lock); 126 127 kfree(intel_vsec_dev->resource); 128 kfree(intel_vsec_dev); 129 } 130 131 int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent, 132 struct intel_vsec_device *intel_vsec_dev, 133 const char *name) 134 { 135 struct auxiliary_device *auxdev = &intel_vsec_dev->auxdev; 136 int ret, id; 137 138 mutex_lock(&vsec_ida_lock); 139 ret = ida_alloc(intel_vsec_dev->ida, GFP_KERNEL); 140 mutex_unlock(&vsec_ida_lock); 141 if (ret < 0) { 142 kfree(intel_vsec_dev->resource); 143 kfree(intel_vsec_dev); 144 return ret; 145 } 146 147 if (!parent) 148 parent = &pdev->dev; 149 150 auxdev->id = ret; 151 auxdev->name = name; 152 auxdev->dev.parent = parent; 153 auxdev->dev.release = intel_vsec_dev_release; 154 155 ret = auxiliary_device_init(auxdev); 156 if (ret < 0) { 157 intel_vsec_dev_release(&auxdev->dev); 158 return ret; 159 } 160 161 ret = auxiliary_device_add(auxdev); 162 if (ret < 0) { 163 auxiliary_device_uninit(auxdev); 164 return ret; 165 } 166 167 ret = devm_add_action_or_reset(parent, intel_vsec_remove_aux, 168 auxdev); 169 if (ret < 0) 170 return ret; 171 172 /* Add auxdev to list */ 173 ret = xa_alloc(&auxdev_array, &id, intel_vsec_dev, PMT_XA_LIMIT, 174 GFP_KERNEL); 175 if (ret) 176 return ret; 177 178 return 0; 179 } 180 EXPORT_SYMBOL_NS_GPL(intel_vsec_add_aux, INTEL_VSEC); 181 182 static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *header, 183 struct intel_vsec_platform_info *info) 184 { 185 struct intel_vsec_device *intel_vsec_dev; 186 struct resource *res, *tmp; 187 unsigned long quirks = info->quirks; 188 int i; 189 190 if (!intel_vsec_supported(header->id, info->caps)) 191 return -EINVAL; 192 193 if (!header->num_entries) { 194 dev_dbg(&pdev->dev, "Invalid 0 entry count for header id %d\n", header->id); 195 return -EINVAL; 196 } 197 198 if (!header->entry_size) { 199 dev_dbg(&pdev->dev, "Invalid 0 entry size for header id %d\n", header->id); 200 return -EINVAL; 201 } 202 203 intel_vsec_dev = kzalloc(sizeof(*intel_vsec_dev), GFP_KERNEL); 204 if (!intel_vsec_dev) 205 return -ENOMEM; 206 207 res = kcalloc(header->num_entries, sizeof(*res), GFP_KERNEL); 208 if (!res) { 209 kfree(intel_vsec_dev); 210 return -ENOMEM; 211 } 212 213 if (quirks & VSEC_QUIRK_TABLE_SHIFT) 214 header->offset >>= TABLE_OFFSET_SHIFT; 215 216 /* 217 * The DVSEC/VSEC contains the starting offset and count for a block of 218 * discovery tables. Create a resource array of these tables to the 219 * auxiliary device driver. 220 */ 221 for (i = 0, tmp = res; i < header->num_entries; i++, tmp++) { 222 tmp->start = pdev->resource[header->tbir].start + 223 header->offset + i * (header->entry_size * sizeof(u32)); 224 tmp->end = tmp->start + (header->entry_size * sizeof(u32)) - 1; 225 tmp->flags = IORESOURCE_MEM; 226 } 227 228 intel_vsec_dev->pcidev = pdev; 229 intel_vsec_dev->resource = res; 230 intel_vsec_dev->num_resources = header->num_entries; 231 intel_vsec_dev->info = info; 232 233 if (header->id == VSEC_ID_SDSI) 234 intel_vsec_dev->ida = &intel_vsec_sdsi_ida; 235 else 236 intel_vsec_dev->ida = &intel_vsec_ida; 237 238 return intel_vsec_add_aux(pdev, NULL, intel_vsec_dev, 239 intel_vsec_name(header->id)); 240 } 241 242 static bool intel_vsec_walk_header(struct pci_dev *pdev, 243 struct intel_vsec_platform_info *info) 244 { 245 struct intel_vsec_header **header = info->headers; 246 bool have_devices = false; 247 int ret; 248 249 for ( ; *header; header++) { 250 ret = intel_vsec_add_dev(pdev, *header, info); 251 if (ret) 252 dev_info(&pdev->dev, "Could not add device for VSEC id %d\n", 253 (*header)->id); 254 else 255 have_devices = true; 256 } 257 258 return have_devices; 259 } 260 261 static bool intel_vsec_walk_dvsec(struct pci_dev *pdev, 262 struct intel_vsec_platform_info *info) 263 { 264 bool have_devices = false; 265 int pos = 0; 266 267 do { 268 struct intel_vsec_header header; 269 u32 table, hdr; 270 u16 vid; 271 int ret; 272 273 pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_DVSEC); 274 if (!pos) 275 break; 276 277 pci_read_config_dword(pdev, pos + PCI_DVSEC_HEADER1, &hdr); 278 vid = PCI_DVSEC_HEADER1_VID(hdr); 279 if (vid != PCI_VENDOR_ID_INTEL) 280 continue; 281 282 /* Support only revision 1 */ 283 header.rev = PCI_DVSEC_HEADER1_REV(hdr); 284 if (header.rev != 1) { 285 dev_info(&pdev->dev, "Unsupported DVSEC revision %d\n", header.rev); 286 continue; 287 } 288 289 header.length = PCI_DVSEC_HEADER1_LEN(hdr); 290 291 pci_read_config_byte(pdev, pos + INTEL_DVSEC_ENTRIES, &header.num_entries); 292 pci_read_config_byte(pdev, pos + INTEL_DVSEC_SIZE, &header.entry_size); 293 pci_read_config_dword(pdev, pos + INTEL_DVSEC_TABLE, &table); 294 295 header.tbir = INTEL_DVSEC_TABLE_BAR(table); 296 header.offset = INTEL_DVSEC_TABLE_OFFSET(table); 297 298 pci_read_config_dword(pdev, pos + PCI_DVSEC_HEADER2, &hdr); 299 header.id = PCI_DVSEC_HEADER2_ID(hdr); 300 301 ret = intel_vsec_add_dev(pdev, &header, info); 302 if (ret) 303 continue; 304 305 have_devices = true; 306 } while (true); 307 308 return have_devices; 309 } 310 311 static bool intel_vsec_walk_vsec(struct pci_dev *pdev, 312 struct intel_vsec_platform_info *info) 313 { 314 bool have_devices = false; 315 int pos = 0; 316 317 do { 318 struct intel_vsec_header header; 319 u32 table, hdr; 320 int ret; 321 322 pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_VNDR); 323 if (!pos) 324 break; 325 326 pci_read_config_dword(pdev, pos + PCI_VNDR_HEADER, &hdr); 327 328 /* Support only revision 1 */ 329 header.rev = PCI_VNDR_HEADER_REV(hdr); 330 if (header.rev != 1) { 331 dev_info(&pdev->dev, "Unsupported VSEC revision %d\n", header.rev); 332 continue; 333 } 334 335 header.id = PCI_VNDR_HEADER_ID(hdr); 336 header.length = PCI_VNDR_HEADER_LEN(hdr); 337 338 /* entry, size, and table offset are the same as DVSEC */ 339 pci_read_config_byte(pdev, pos + INTEL_DVSEC_ENTRIES, &header.num_entries); 340 pci_read_config_byte(pdev, pos + INTEL_DVSEC_SIZE, &header.entry_size); 341 pci_read_config_dword(pdev, pos + INTEL_DVSEC_TABLE, &table); 342 343 header.tbir = INTEL_DVSEC_TABLE_BAR(table); 344 header.offset = INTEL_DVSEC_TABLE_OFFSET(table); 345 346 ret = intel_vsec_add_dev(pdev, &header, info); 347 if (ret) 348 continue; 349 350 have_devices = true; 351 } while (true); 352 353 return have_devices; 354 } 355 356 static int intel_vsec_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 357 { 358 struct intel_vsec_platform_info *info; 359 bool have_devices = false; 360 int ret; 361 362 ret = pcim_enable_device(pdev); 363 if (ret) 364 return ret; 365 366 pci_save_state(pdev); 367 info = (struct intel_vsec_platform_info *)id->driver_data; 368 if (!info) 369 return -EINVAL; 370 371 if (intel_vsec_walk_dvsec(pdev, info)) 372 have_devices = true; 373 374 if (intel_vsec_walk_vsec(pdev, info)) 375 have_devices = true; 376 377 if (info && (info->quirks & VSEC_QUIRK_NO_DVSEC) && 378 intel_vsec_walk_header(pdev, info)) 379 have_devices = true; 380 381 if (!have_devices) 382 return -ENODEV; 383 384 return 0; 385 } 386 387 /* DG1 info */ 388 static struct intel_vsec_header dg1_header = { 389 .length = 0x10, 390 .id = 2, 391 .num_entries = 1, 392 .entry_size = 3, 393 .tbir = 0, 394 .offset = 0x466000, 395 }; 396 397 static struct intel_vsec_header *dg1_headers[] = { 398 &dg1_header, 399 NULL 400 }; 401 402 static const struct intel_vsec_platform_info dg1_info = { 403 .caps = VSEC_CAP_TELEMETRY, 404 .headers = dg1_headers, 405 .quirks = VSEC_QUIRK_NO_DVSEC | VSEC_QUIRK_EARLY_HW, 406 }; 407 408 /* MTL info */ 409 static const struct intel_vsec_platform_info mtl_info = { 410 .caps = VSEC_CAP_TELEMETRY, 411 }; 412 413 /* OOBMSM info */ 414 static const struct intel_vsec_platform_info oobmsm_info = { 415 .caps = VSEC_CAP_TELEMETRY | VSEC_CAP_SDSI | VSEC_CAP_TPMI, 416 }; 417 418 /* TGL info */ 419 static const struct intel_vsec_platform_info tgl_info = { 420 .caps = VSEC_CAP_TELEMETRY, 421 .quirks = VSEC_QUIRK_TABLE_SHIFT | VSEC_QUIRK_EARLY_HW, 422 }; 423 424 #define PCI_DEVICE_ID_INTEL_VSEC_ADL 0x467d 425 #define PCI_DEVICE_ID_INTEL_VSEC_DG1 0x490e 426 #define PCI_DEVICE_ID_INTEL_VSEC_MTL_M 0x7d0d 427 #define PCI_DEVICE_ID_INTEL_VSEC_MTL_S 0xad0d 428 #define PCI_DEVICE_ID_INTEL_VSEC_OOBMSM 0x09a7 429 #define PCI_DEVICE_ID_INTEL_VSEC_RPL 0xa77d 430 #define PCI_DEVICE_ID_INTEL_VSEC_TGL 0x9a0d 431 static const struct pci_device_id intel_vsec_pci_ids[] = { 432 { PCI_DEVICE_DATA(INTEL, VSEC_ADL, &tgl_info) }, 433 { PCI_DEVICE_DATA(INTEL, VSEC_DG1, &dg1_info) }, 434 { PCI_DEVICE_DATA(INTEL, VSEC_MTL_M, &mtl_info) }, 435 { PCI_DEVICE_DATA(INTEL, VSEC_MTL_S, &mtl_info) }, 436 { PCI_DEVICE_DATA(INTEL, VSEC_OOBMSM, &oobmsm_info) }, 437 { PCI_DEVICE_DATA(INTEL, VSEC_RPL, &tgl_info) }, 438 { PCI_DEVICE_DATA(INTEL, VSEC_TGL, &tgl_info) }, 439 { } 440 }; 441 MODULE_DEVICE_TABLE(pci, intel_vsec_pci_ids); 442 443 static pci_ers_result_t intel_vsec_pci_error_detected(struct pci_dev *pdev, 444 pci_channel_state_t state) 445 { 446 pci_ers_result_t status = PCI_ERS_RESULT_NEED_RESET; 447 448 dev_info(&pdev->dev, "PCI error detected, state %d", state); 449 450 if (state == pci_channel_io_perm_failure) 451 status = PCI_ERS_RESULT_DISCONNECT; 452 else 453 pci_disable_device(pdev); 454 455 return status; 456 } 457 458 static pci_ers_result_t intel_vsec_pci_slot_reset(struct pci_dev *pdev) 459 { 460 struct intel_vsec_device *intel_vsec_dev; 461 pci_ers_result_t status = PCI_ERS_RESULT_DISCONNECT; 462 const struct pci_device_id *pci_dev_id; 463 unsigned long index; 464 465 dev_info(&pdev->dev, "Resetting PCI slot\n"); 466 467 msleep(2000); 468 if (pci_enable_device(pdev)) { 469 dev_info(&pdev->dev, 470 "Failed to re-enable PCI device after reset.\n"); 471 goto out; 472 } 473 474 status = PCI_ERS_RESULT_RECOVERED; 475 476 xa_for_each(&auxdev_array, index, intel_vsec_dev) { 477 /* check if pdev doesn't match */ 478 if (pdev != intel_vsec_dev->pcidev) 479 continue; 480 devm_release_action(&pdev->dev, intel_vsec_remove_aux, 481 &intel_vsec_dev->auxdev); 482 } 483 pci_disable_device(pdev); 484 pci_restore_state(pdev); 485 pci_dev_id = pci_match_id(intel_vsec_pci_ids, pdev); 486 intel_vsec_pci_probe(pdev, pci_dev_id); 487 488 out: 489 return status; 490 } 491 492 static void intel_vsec_pci_resume(struct pci_dev *pdev) 493 { 494 dev_info(&pdev->dev, "Done resuming PCI device\n"); 495 } 496 497 static const struct pci_error_handlers intel_vsec_pci_err_handlers = { 498 .error_detected = intel_vsec_pci_error_detected, 499 .slot_reset = intel_vsec_pci_slot_reset, 500 .resume = intel_vsec_pci_resume, 501 }; 502 503 static struct pci_driver intel_vsec_pci_driver = { 504 .name = "intel_vsec", 505 .id_table = intel_vsec_pci_ids, 506 .probe = intel_vsec_pci_probe, 507 .err_handler = &intel_vsec_pci_err_handlers, 508 }; 509 module_pci_driver(intel_vsec_pci_driver); 510 511 MODULE_AUTHOR("David E. Box <david.e.box@linux.intel.com>"); 512 MODULE_DESCRIPTION("Intel Extended Capabilities auxiliary bus driver"); 513 MODULE_LICENSE("GPL v2"); 514