1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains platform specific structure definitions 4 * and init function used by Sunrise Point PCH. 5 * 6 * Copyright (c) 2022, Intel Corporation. 7 * All Rights Reserved. 8 * 9 */ 10 11 #include "core.h" 12 13 const struct pmc_bit_map spt_pll_map[] = { 14 {"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0}, 15 {"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1}, 16 {"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2}, 17 {"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3}, 18 {} 19 }; 20 21 const struct pmc_bit_map spt_mphy_map[] = { 22 {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0}, 23 {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1}, 24 {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2}, 25 {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3}, 26 {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4}, 27 {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5}, 28 {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6}, 29 {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7}, 30 {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8}, 31 {"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9}, 32 {"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10}, 33 {"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11}, 34 {"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12}, 35 {"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13}, 36 {"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14}, 37 {"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15}, 38 {} 39 }; 40 41 const struct pmc_bit_map spt_pfear_map[] = { 42 {"PMC", SPT_PMC_BIT_PMC}, 43 {"OPI-DMI", SPT_PMC_BIT_OPI}, 44 {"SPI / eSPI", SPT_PMC_BIT_SPI}, 45 {"XHCI", SPT_PMC_BIT_XHCI}, 46 {"SPA", SPT_PMC_BIT_SPA}, 47 {"SPB", SPT_PMC_BIT_SPB}, 48 {"SPC", SPT_PMC_BIT_SPC}, 49 {"GBE", SPT_PMC_BIT_GBE}, 50 {"SATA", SPT_PMC_BIT_SATA}, 51 {"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0}, 52 {"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1}, 53 {"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2}, 54 {"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3}, 55 {"RSVD", SPT_PMC_BIT_RSVD_0B}, 56 {"LPSS", SPT_PMC_BIT_LPSS}, 57 {"LPC", SPT_PMC_BIT_LPC}, 58 {"SMB", SPT_PMC_BIT_SMB}, 59 {"ISH", SPT_PMC_BIT_ISH}, 60 {"P2SB", SPT_PMC_BIT_P2SB}, 61 {"DFX", SPT_PMC_BIT_DFX}, 62 {"SCC", SPT_PMC_BIT_SCC}, 63 {"RSVD", SPT_PMC_BIT_RSVD_0C}, 64 {"FUSE", SPT_PMC_BIT_FUSE}, 65 {"CAMERA", SPT_PMC_BIT_CAMREA}, 66 {"RSVD", SPT_PMC_BIT_RSVD_0D}, 67 {"USB3-OTG", SPT_PMC_BIT_USB3_OTG}, 68 {"EXI", SPT_PMC_BIT_EXI}, 69 {"CSE", SPT_PMC_BIT_CSE}, 70 {"CSME_KVM", SPT_PMC_BIT_CSME_KVM}, 71 {"CSME_PMT", SPT_PMC_BIT_CSME_PMT}, 72 {"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK}, 73 {"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO}, 74 {"CSME_USBR", SPT_PMC_BIT_CSME_USBR}, 75 {"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM}, 76 {"CSME_SMT", SPT_PMC_BIT_CSME_SMT}, 77 {"RSVD", SPT_PMC_BIT_RSVD_1A}, 78 {"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2}, 79 {"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1}, 80 {"CSME_RTC", SPT_PMC_BIT_CSME_RTC}, 81 {"CSME_PSF", SPT_PMC_BIT_CSME_PSF}, 82 {} 83 }; 84 85 const struct pmc_bit_map *ext_spt_pfear_map[] = { 86 /* 87 * Check intel_pmc_core_ids[] users of spt_reg_map for 88 * a list of core SoCs using this. 89 */ 90 spt_pfear_map, 91 NULL 92 }; 93 94 const struct pmc_bit_map spt_ltr_show_map[] = { 95 {"SOUTHPORT_A", SPT_PMC_LTR_SPA}, 96 {"SOUTHPORT_B", SPT_PMC_LTR_SPB}, 97 {"SATA", SPT_PMC_LTR_SATA}, 98 {"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE}, 99 {"XHCI", SPT_PMC_LTR_XHCI}, 100 {"Reserved", SPT_PMC_LTR_RESERVED}, 101 {"ME", SPT_PMC_LTR_ME}, 102 /* EVA is Enterprise Value Add, doesn't really exist on PCH */ 103 {"EVA", SPT_PMC_LTR_EVA}, 104 {"SOUTHPORT_C", SPT_PMC_LTR_SPC}, 105 {"HD_AUDIO", SPT_PMC_LTR_AZ}, 106 {"LPSS", SPT_PMC_LTR_LPSS}, 107 {"SOUTHPORT_D", SPT_PMC_LTR_SPD}, 108 {"SOUTHPORT_E", SPT_PMC_LTR_SPE}, 109 {"CAMERA", SPT_PMC_LTR_CAM}, 110 {"ESPI", SPT_PMC_LTR_ESPI}, 111 {"SCC", SPT_PMC_LTR_SCC}, 112 {"ISH", SPT_PMC_LTR_ISH}, 113 /* Below two cannot be used for LTR_IGNORE */ 114 {"CURRENT_PLATFORM", SPT_PMC_LTR_CUR_PLT}, 115 {"AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT}, 116 {} 117 }; 118 119 const struct pmc_reg_map spt_reg_map = { 120 .pfear_sts = ext_spt_pfear_map, 121 .mphy_sts = spt_mphy_map, 122 .pll_sts = spt_pll_map, 123 .ltr_show_sts = spt_ltr_show_map, 124 .msr_sts = msr_map, 125 .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET, 126 .slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP, 127 .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET, 128 .regmap_length = SPT_PMC_MMIO_REG_LEN, 129 .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A, 130 .ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES, 131 .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET, 132 .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT, 133 .ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED, 134 .pm_vric1_offset = SPT_PMC_VRIC1_OFFSET, 135 }; 136 137 int spt_core_init(struct pmc_dev *pmcdev) 138 { 139 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 140 141 pmc->map = &spt_reg_map; 142 return get_primary_reg_base(pmc); 143 } 144