1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains platform specific structure definitions 4 * and init function used by Meteor Lake PCH. 5 * 6 * Copyright (c) 2022, Intel Corporation. 7 * All Rights Reserved. 8 * 9 */ 10 11 #include <linux/pci.h> 12 #include "core.h" 13 14 /* 15 * Die Mapping to Product. 16 * Product SOCDie IOEDie PCHDie 17 * MTL-M SOC-M IOE-M None 18 * MTL-P SOC-M IOE-P None 19 * MTL-S SOC-S IOE-P PCH-S 20 */ 21 22 const struct pmc_bit_map mtl_socm_pfear_map[] = { 23 {"PMC", BIT(0)}, 24 {"OPI", BIT(1)}, 25 {"SPI", BIT(2)}, 26 {"XHCI", BIT(3)}, 27 {"SPA", BIT(4)}, 28 {"SPB", BIT(5)}, 29 {"SPC", BIT(6)}, 30 {"GBE", BIT(7)}, 31 32 {"SATA", BIT(0)}, 33 {"DSP0", BIT(1)}, 34 {"DSP1", BIT(2)}, 35 {"DSP2", BIT(3)}, 36 {"DSP3", BIT(4)}, 37 {"SPD", BIT(5)}, 38 {"LPSS", BIT(6)}, 39 {"LPC", BIT(7)}, 40 41 {"SMB", BIT(0)}, 42 {"ISH", BIT(1)}, 43 {"P2SB", BIT(2)}, 44 {"NPK_VNN", BIT(3)}, 45 {"SDX", BIT(4)}, 46 {"SPE", BIT(5)}, 47 {"FUSE", BIT(6)}, 48 {"SBR8", BIT(7)}, 49 50 {"RSVD24", BIT(0)}, 51 {"OTG", BIT(1)}, 52 {"EXI", BIT(2)}, 53 {"CSE", BIT(3)}, 54 {"CSME_KVM", BIT(4)}, 55 {"CSME_PMT", BIT(5)}, 56 {"CSME_CLINK", BIT(6)}, 57 {"CSME_PTIO", BIT(7)}, 58 59 {"CSME_USBR", BIT(0)}, 60 {"CSME_SUSRAM", BIT(1)}, 61 {"CSME_SMT1", BIT(2)}, 62 {"RSVD35", BIT(3)}, 63 {"CSME_SMS2", BIT(4)}, 64 {"CSME_SMS", BIT(5)}, 65 {"CSME_RTC", BIT(6)}, 66 {"CSME_PSF", BIT(7)}, 67 68 {"SBR0", BIT(0)}, 69 {"SBR1", BIT(1)}, 70 {"SBR2", BIT(2)}, 71 {"SBR3", BIT(3)}, 72 {"SBR4", BIT(4)}, 73 {"SBR5", BIT(5)}, 74 {"RSVD46", BIT(6)}, 75 {"PSF1", BIT(7)}, 76 77 {"PSF2", BIT(0)}, 78 {"PSF3", BIT(1)}, 79 {"PSF4", BIT(2)}, 80 {"CNVI", BIT(3)}, 81 {"UFSX2", BIT(4)}, 82 {"EMMC", BIT(5)}, 83 {"SPF", BIT(6)}, 84 {"SBR6", BIT(7)}, 85 86 {"SBR7", BIT(0)}, 87 {"NPK_AON", BIT(1)}, 88 {"HDA4", BIT(2)}, 89 {"HDA5", BIT(3)}, 90 {"HDA6", BIT(4)}, 91 {"PSF6", BIT(5)}, 92 {"RSVD62", BIT(6)}, 93 {"RSVD63", BIT(7)}, 94 {} 95 }; 96 97 const struct pmc_bit_map *ext_mtl_socm_pfear_map[] = { 98 mtl_socm_pfear_map, 99 NULL 100 }; 101 102 const struct pmc_bit_map mtl_socm_ltr_show_map[] = { 103 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 104 {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 105 {"SATA", CNP_PMC_LTR_SATA}, 106 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 107 {"XHCI", CNP_PMC_LTR_XHCI}, 108 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 109 {"ME", CNP_PMC_LTR_ME}, 110 {"SATA1", CNP_PMC_LTR_EVA}, 111 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 112 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 113 {"CNV", CNP_PMC_LTR_CNV}, 114 {"LPSS", CNP_PMC_LTR_LPSS}, 115 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 116 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 117 {"SATA2", CNP_PMC_LTR_CAM}, 118 {"ESPI", CNP_PMC_LTR_ESPI}, 119 {"SCC", CNP_PMC_LTR_SCC}, 120 {"ISH", CNP_PMC_LTR_ISH}, 121 {"UFSX2", CNP_PMC_LTR_UFSX2}, 122 {"EMMC", CNP_PMC_LTR_EMMC}, 123 {"WIGIG", ICL_PMC_LTR_WIGIG}, 124 {"THC0", TGL_PMC_LTR_THC0}, 125 {"THC1", TGL_PMC_LTR_THC1}, 126 {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, 127 {"ESE", MTL_PMC_LTR_ESE}, 128 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC}, 129 130 /* Below two cannot be used for LTR_IGNORE */ 131 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, 132 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, 133 {} 134 }; 135 136 const struct pmc_bit_map mtl_socm_clocksource_status_map[] = { 137 {"AON2_OFF_STS", BIT(0)}, 138 {"AON3_OFF_STS", BIT(1)}, 139 {"AON4_OFF_STS", BIT(2)}, 140 {"AON5_OFF_STS", BIT(3)}, 141 {"AON1_OFF_STS", BIT(4)}, 142 {"XTAL_LVM_OFF_STS", BIT(5)}, 143 {"MPFPW1_0_PLL_OFF_STS", BIT(6)}, 144 {"MPFPW1_1_PLL_OFF_STS", BIT(7)}, 145 {"USB3_PLL_OFF_STS", BIT(8)}, 146 {"AON3_SPL_OFF_STS", BIT(9)}, 147 {"MPFPW2_0_PLL_OFF_STS", BIT(12)}, 148 {"MPFPW3_0_PLL_OFF_STS", BIT(13)}, 149 {"XTAL_AGGR_OFF_STS", BIT(17)}, 150 {"USB2_PLL_OFF_STS", BIT(18)}, 151 {"FILTER_PLL_OFF_STS", BIT(22)}, 152 {"ACE_PLL_OFF_STS", BIT(24)}, 153 {"FABRIC_PLL_OFF_STS", BIT(25)}, 154 {"SOC_PLL_OFF_STS", BIT(26)}, 155 {"PCIFAB_PLL_OFF_STS", BIT(27)}, 156 {"REF_PLL_OFF_STS", BIT(28)}, 157 {"IMG_PLL_OFF_STS", BIT(29)}, 158 {"RTC_PLL_OFF_STS", BIT(31)}, 159 {} 160 }; 161 162 const struct pmc_bit_map mtl_socm_power_gating_status_0_map[] = { 163 {"PMC_PGD0_PG_STS", BIT(0)}, 164 {"DMI_PGD0_PG_STS", BIT(1)}, 165 {"ESPISPI_PGD0_PG_STS", BIT(2)}, 166 {"XHCI_PGD0_PG_STS", BIT(3)}, 167 {"SPA_PGD0_PG_STS", BIT(4)}, 168 {"SPB_PGD0_PG_STS", BIT(5)}, 169 {"SPC_PGD0_PG_STS", BIT(6)}, 170 {"GBE_PGD0_PG_STS", BIT(7)}, 171 {"SATA_PGD0_PG_STS", BIT(8)}, 172 {"PSF13_PGD0_PG_STS", BIT(9)}, 173 {"SOC_D2D_PGD3_PG_STS", BIT(10)}, 174 {"MPFPW3_PGD0_PG_STS", BIT(11)}, 175 {"ESE_PGD0_PG_STS", BIT(12)}, 176 {"SPD_PGD0_PG_STS", BIT(13)}, 177 {"LPSS_PGD0_PG_STS", BIT(14)}, 178 {"LPC_PGD0_PG_STS", BIT(15)}, 179 {"SMB_PGD0_PG_STS", BIT(16)}, 180 {"ISH_PGD0_PG_STS", BIT(17)}, 181 {"P2S_PGD0_PG_STS", BIT(18)}, 182 {"NPK_PGD0_PG_STS", BIT(19)}, 183 {"DBG_SBR_PGD0_PG_STS", BIT(20)}, 184 {"SBRG_PGD0_PG_STS", BIT(21)}, 185 {"FUSE_PGD0_PG_STS", BIT(22)}, 186 {"SBR8_PGD0_PG_STS", BIT(23)}, 187 {"SOC_D2D_PGD2_PG_STS", BIT(24)}, 188 {"XDCI_PGD0_PG_STS", BIT(25)}, 189 {"EXI_PGD0_PG_STS", BIT(26)}, 190 {"CSE_PGD0_PG_STS", BIT(27)}, 191 {"KVMCC_PGD0_PG_STS", BIT(28)}, 192 {"PMT_PGD0_PG_STS", BIT(29)}, 193 {"CLINK_PGD0_PG_STS", BIT(30)}, 194 {"PTIO_PGD0_PG_STS", BIT(31)}, 195 {} 196 }; 197 198 const struct pmc_bit_map mtl_socm_power_gating_status_1_map[] = { 199 {"USBR0_PGD0_PG_STS", BIT(0)}, 200 {"SUSRAM_PGD0_PG_STS", BIT(1)}, 201 {"SMT1_PGD0_PG_STS", BIT(2)}, 202 {"FIACPCB_U_PGD0_PG_STS", BIT(3)}, 203 {"SMS2_PGD0_PG_STS", BIT(4)}, 204 {"SMS1_PGD0_PG_STS", BIT(5)}, 205 {"CSMERTC_PGD0_PG_STS", BIT(6)}, 206 {"CSMEPSF_PGD0_PG_STS", BIT(7)}, 207 {"SBR0_PGD0_PG_STS", BIT(8)}, 208 {"SBR1_PGD0_PG_STS", BIT(9)}, 209 {"SBR2_PGD0_PG_STS", BIT(10)}, 210 {"SBR3_PGD0_PG_STS", BIT(11)}, 211 {"U3FPW1_PGD0_PG_STS", BIT(12)}, 212 {"SBR5_PGD0_PG_STS", BIT(13)}, 213 {"MPFPW1_PGD0_PG_STS", BIT(14)}, 214 {"UFSPW1_PGD0_PG_STS", BIT(15)}, 215 {"FIA_X_PGD0_PG_STS", BIT(16)}, 216 {"SOC_D2D_PGD0_PG_STS", BIT(17)}, 217 {"MPFPW2_PGD0_PG_STS", BIT(18)}, 218 {"CNVI_PGD0_PG_STS", BIT(19)}, 219 {"UFSX2_PGD0_PG_STS", BIT(20)}, 220 {"ENDBG_PGD0_PG_STS", BIT(21)}, 221 {"DBG_PSF_PGD0_PG_STS", BIT(22)}, 222 {"SBR6_PGD0_PG_STS", BIT(23)}, 223 {"SBR7_PGD0_PG_STS", BIT(24)}, 224 {"NPK_PGD1_PG_STS", BIT(25)}, 225 {"FIACPCB_X_PGD0_PG_STS", BIT(26)}, 226 {"DBC_PGD0_PG_STS", BIT(27)}, 227 {"FUSEGPSB_PGD0_PG_STS", BIT(28)}, 228 {"PSF6_PGD0_PG_STS", BIT(29)}, 229 {"PSF7_PGD0_PG_STS", BIT(30)}, 230 {"GBETSN1_PGD0_PG_STS", BIT(31)}, 231 {} 232 }; 233 234 const struct pmc_bit_map mtl_socm_power_gating_status_2_map[] = { 235 {"PSF8_PGD0_PG_STS", BIT(0)}, 236 {"FIA_PGD0_PG_STS", BIT(1)}, 237 {"SOC_D2D_PGD1_PG_STS", BIT(2)}, 238 {"FIA_U_PGD0_PG_STS", BIT(3)}, 239 {"TAM_PGD0_PG_STS", BIT(4)}, 240 {"GBETSN_PGD0_PG_STS", BIT(5)}, 241 {"TBTLSX_PGD0_PG_STS", BIT(6)}, 242 {"THC0_PGD0_PG_STS", BIT(7)}, 243 {"THC1_PGD0_PG_STS", BIT(8)}, 244 {"PMC_PGD1_PG_STS", BIT(9)}, 245 {"GNA_PGD0_PG_STS", BIT(10)}, 246 {"ACE_PGD0_PG_STS", BIT(11)}, 247 {"ACE_PGD1_PG_STS", BIT(12)}, 248 {"ACE_PGD2_PG_STS", BIT(13)}, 249 {"ACE_PGD3_PG_STS", BIT(14)}, 250 {"ACE_PGD4_PG_STS", BIT(15)}, 251 {"ACE_PGD5_PG_STS", BIT(16)}, 252 {"ACE_PGD6_PG_STS", BIT(17)}, 253 {"ACE_PGD7_PG_STS", BIT(18)}, 254 {"ACE_PGD8_PG_STS", BIT(19)}, 255 {"FIA_PGS_PGD0_PG_STS", BIT(20)}, 256 {"FIACPCB_PGS_PGD0_PG_STS", BIT(21)}, 257 {"FUSEPMSB_PGD0_PG_STS", BIT(22)}, 258 {} 259 }; 260 261 const struct pmc_bit_map mtl_socm_d3_status_0_map[] = { 262 {"LPSS_D3_STS", BIT(3)}, 263 {"XDCI_D3_STS", BIT(4)}, 264 {"XHCI_D3_STS", BIT(5)}, 265 {"SPA_D3_STS", BIT(12)}, 266 {"SPB_D3_STS", BIT(13)}, 267 {"SPC_D3_STS", BIT(14)}, 268 {"SPD_D3_STS", BIT(15)}, 269 {"ESPISPI_D3_STS", BIT(18)}, 270 {"SATA_D3_STS", BIT(20)}, 271 {"PSTH_D3_STS", BIT(21)}, 272 {"DMI_D3_STS", BIT(22)}, 273 {} 274 }; 275 276 const struct pmc_bit_map mtl_socm_d3_status_1_map[] = { 277 {"GBETSN1_D3_STS", BIT(14)}, 278 {"GBE_D3_STS", BIT(19)}, 279 {"ITSS_D3_STS", BIT(23)}, 280 {"P2S_D3_STS", BIT(24)}, 281 {"CNVI_D3_STS", BIT(27)}, 282 {"UFSX2_D3_STS", BIT(28)}, 283 {} 284 }; 285 286 const struct pmc_bit_map mtl_socm_d3_status_2_map[] = { 287 {"GNA_D3_STS", BIT(0)}, 288 {"CSMERTC_D3_STS", BIT(1)}, 289 {"SUSRAM_D3_STS", BIT(2)}, 290 {"CSE_D3_STS", BIT(4)}, 291 {"KVMCC_D3_STS", BIT(5)}, 292 {"USBR0_D3_STS", BIT(6)}, 293 {"ISH_D3_STS", BIT(7)}, 294 {"SMT1_D3_STS", BIT(8)}, 295 {"SMT2_D3_STS", BIT(9)}, 296 {"SMT3_D3_STS", BIT(10)}, 297 {"CLINK_D3_STS", BIT(14)}, 298 {"PTIO_D3_STS", BIT(16)}, 299 {"PMT_D3_STS", BIT(17)}, 300 {"SMS1_D3_STS", BIT(18)}, 301 {"SMS2_D3_STS", BIT(19)}, 302 {} 303 }; 304 305 const struct pmc_bit_map mtl_socm_d3_status_3_map[] = { 306 {"ESE_D3_STS", BIT(2)}, 307 {"GBETSN_D3_STS", BIT(13)}, 308 {"THC0_D3_STS", BIT(14)}, 309 {"THC1_D3_STS", BIT(15)}, 310 {"ACE_D3_STS", BIT(23)}, 311 {} 312 }; 313 314 const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[] = { 315 {"LPSS_VNN_REQ_STS", BIT(3)}, 316 {"FIA_VNN_REQ_STS", BIT(17)}, 317 {"ESPISPI_VNN_REQ_STS", BIT(18)}, 318 {} 319 }; 320 321 const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[] = { 322 {"NPK_VNN_REQ_STS", BIT(4)}, 323 {"DFXAGG_VNN_REQ_STS", BIT(8)}, 324 {"EXI_VNN_REQ_STS", BIT(9)}, 325 {"P2D_VNN_REQ_STS", BIT(18)}, 326 {"GBE_VNN_REQ_STS", BIT(19)}, 327 {"SMB_VNN_REQ_STS", BIT(25)}, 328 {"LPC_VNN_REQ_STS", BIT(26)}, 329 {} 330 }; 331 332 const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[] = { 333 {"CSMERTC_VNN_REQ_STS", BIT(1)}, 334 {"CSE_VNN_REQ_STS", BIT(4)}, 335 {"ISH_VNN_REQ_STS", BIT(7)}, 336 {"SMT1_VNN_REQ_STS", BIT(8)}, 337 {"CLINK_VNN_REQ_STS", BIT(14)}, 338 {"SMS1_VNN_REQ_STS", BIT(18)}, 339 {"SMS2_VNN_REQ_STS", BIT(19)}, 340 {"GPIOCOM4_VNN_REQ_STS", BIT(20)}, 341 {"GPIOCOM3_VNN_REQ_STS", BIT(21)}, 342 {"GPIOCOM2_VNN_REQ_STS", BIT(22)}, 343 {"GPIOCOM1_VNN_REQ_STS", BIT(23)}, 344 {"GPIOCOM0_VNN_REQ_STS", BIT(24)}, 345 {} 346 }; 347 348 const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[] = { 349 {"ESE_VNN_REQ_STS", BIT(2)}, 350 {"DTS0_VNN_REQ_STS", BIT(7)}, 351 {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, 352 {} 353 }; 354 355 const struct pmc_bit_map mtl_socm_vnn_misc_status_map[] = { 356 {"CPU_C10_REQ_STS", BIT(0)}, 357 {"TS_OFF_REQ_STS", BIT(1)}, 358 {"PNDE_MET_REQ_STS", BIT(2)}, 359 {"PCIE_DEEP_PM_REQ_STS", BIT(3)}, 360 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)}, 361 {"NPK_VNNAON_REQ_STS", BIT(5)}, 362 {"VNN_SOC_REQ_STS", BIT(6)}, 363 {"ISH_VNNAON_REQ_STS", BIT(7)}, 364 {"IOE_COND_MET_S02I2_0_REQ_STS", BIT(8)}, 365 {"IOE_COND_MET_S02I2_1_REQ_STS", BIT(9)}, 366 {"IOE_COND_MET_S02I2_2_REQ_STS", BIT(10)}, 367 {"PLT_GREATER_REQ_STS", BIT(11)}, 368 {"PCIE_CLKREQ_REQ_STS", BIT(12)}, 369 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)}, 370 {"PM_SYNC_STATES_REQ_STS", BIT(14)}, 371 {"EA_REQ_STS", BIT(15)}, 372 {"MPHY_CORE_OFF_REQ_STS", BIT(16)}, 373 {"BRK_EV_EN_REQ_STS", BIT(17)}, 374 {"AUTO_DEMO_EN_REQ_STS", BIT(18)}, 375 {"ITSS_CLK_SRC_REQ_STS", BIT(19)}, 376 {"LPC_CLK_SRC_REQ_STS", BIT(20)}, 377 {"ARC_IDLE_REQ_STS", BIT(21)}, 378 {"MPHY_SUS_REQ_STS", BIT(22)}, 379 {"FIA_DEEP_PM_REQ_STS", BIT(23)}, 380 {"UXD_CONNECTED_REQ_STS", BIT(24)}, 381 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)}, 382 {"USB2_VNNAON_ACT_REQ_STS", BIT(26)}, 383 {"PRE_WAKE0_REQ_STS", BIT(27)}, 384 {"PRE_WAKE1_REQ_STS", BIT(28)}, 385 {"PRE_WAKE2_EN_REQ_STS", BIT(29)}, 386 {"WOV_REQ_STS", BIT(30)}, 387 {"CNVI_V1P05_REQ_STS", BIT(31)}, 388 {} 389 }; 390 391 const struct pmc_bit_map mtl_socm_signal_status_map[] = { 392 {"LSX_Wake0_En_STS", BIT(0)}, 393 {"LSX_Wake0_Pol_STS", BIT(1)}, 394 {"LSX_Wake1_En_STS", BIT(2)}, 395 {"LSX_Wake1_Pol_STS", BIT(3)}, 396 {"LSX_Wake2_En_STS", BIT(4)}, 397 {"LSX_Wake2_Pol_STS", BIT(5)}, 398 {"LSX_Wake3_En_STS", BIT(6)}, 399 {"LSX_Wake3_Pol_STS", BIT(7)}, 400 {"LSX_Wake4_En_STS", BIT(8)}, 401 {"LSX_Wake4_Pol_STS", BIT(9)}, 402 {"LSX_Wake5_En_STS", BIT(10)}, 403 {"LSX_Wake5_Pol_STS", BIT(11)}, 404 {"LSX_Wake6_En_STS", BIT(12)}, 405 {"LSX_Wake6_Pol_STS", BIT(13)}, 406 {"LSX_Wake7_En_STS", BIT(14)}, 407 {"LSX_Wake7_Pol_STS", BIT(15)}, 408 {"LPSS_Wake0_En_STS", BIT(16)}, 409 {"LPSS_Wake0_Pol_STS", BIT(17)}, 410 {"LPSS_Wake1_En_STS", BIT(18)}, 411 {"LPSS_Wake1_Pol_STS", BIT(19)}, 412 {"Int_Timer_SS_Wake0_En_STS", BIT(20)}, 413 {"Int_Timer_SS_Wake0_Pol_STS", BIT(21)}, 414 {"Int_Timer_SS_Wake1_En_STS", BIT(22)}, 415 {"Int_Timer_SS_Wake1_Pol_STS", BIT(23)}, 416 {"Int_Timer_SS_Wake2_En_STS", BIT(24)}, 417 {"Int_Timer_SS_Wake2_Pol_STS", BIT(25)}, 418 {"Int_Timer_SS_Wake3_En_STS", BIT(26)}, 419 {"Int_Timer_SS_Wake3_Pol_STS", BIT(27)}, 420 {"Int_Timer_SS_Wake4_En_STS", BIT(28)}, 421 {"Int_Timer_SS_Wake4_Pol_STS", BIT(29)}, 422 {"Int_Timer_SS_Wake5_En_STS", BIT(30)}, 423 {"Int_Timer_SS_Wake5_Pol_STS", BIT(31)}, 424 {} 425 }; 426 427 const struct pmc_bit_map *mtl_socm_lpm_maps[] = { 428 mtl_socm_clocksource_status_map, 429 mtl_socm_power_gating_status_0_map, 430 mtl_socm_power_gating_status_1_map, 431 mtl_socm_power_gating_status_2_map, 432 mtl_socm_d3_status_0_map, 433 mtl_socm_d3_status_1_map, 434 mtl_socm_d3_status_2_map, 435 mtl_socm_d3_status_3_map, 436 mtl_socm_vnn_req_status_0_map, 437 mtl_socm_vnn_req_status_1_map, 438 mtl_socm_vnn_req_status_2_map, 439 mtl_socm_vnn_req_status_3_map, 440 mtl_socm_vnn_misc_status_map, 441 mtl_socm_signal_status_map, 442 NULL 443 }; 444 445 const struct pmc_reg_map mtl_socm_reg_map = { 446 .pfear_sts = ext_mtl_socm_pfear_map, 447 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 448 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 449 .ltr_show_sts = mtl_socm_ltr_show_map, 450 .msr_sts = msr_map, 451 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 452 .regmap_length = MTL_SOC_PMC_MMIO_REG_LEN, 453 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 454 .ppfear_buckets = MTL_SOCM_PPFEAR_NUM_ENTRIES, 455 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 456 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 457 .lpm_num_maps = ADL_LPM_NUM_MAPS, 458 .ltr_ignore_max = MTL_SOCM_NUM_IP_IGN_ALLOWED, 459 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 460 .etr3_offset = ETR3_OFFSET, 461 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 462 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 463 .lpm_en_offset = MTL_LPM_EN_OFFSET, 464 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 465 .lpm_sts = mtl_socm_lpm_maps, 466 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 467 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 468 }; 469 470 const struct pmc_bit_map mtl_ioep_pfear_map[] = { 471 {"PMC_0", BIT(0)}, 472 {"OPI", BIT(1)}, 473 {"TCSS", BIT(2)}, 474 {"RSVD3", BIT(3)}, 475 {"SPA", BIT(4)}, 476 {"SPB", BIT(5)}, 477 {"SPC", BIT(6)}, 478 {"IOE_D2D_3", BIT(7)}, 479 480 {"RSVD8", BIT(0)}, 481 {"RSVD9", BIT(1)}, 482 {"SPE", BIT(2)}, 483 {"RSVD11", BIT(3)}, 484 {"RSVD12", BIT(4)}, 485 {"SPD", BIT(5)}, 486 {"ACE_7", BIT(6)}, 487 {"RSVD15", BIT(7)}, 488 489 {"ACE_0", BIT(0)}, 490 {"FIACPCB_P", BIT(1)}, 491 {"P2S", BIT(2)}, 492 {"RSVD19", BIT(3)}, 493 {"ACE_8", BIT(4)}, 494 {"IOE_D2D_0", BIT(5)}, 495 {"FUSE", BIT(6)}, 496 {"RSVD23", BIT(7)}, 497 498 {"FIACPCB_P5", BIT(0)}, 499 {"ACE_3", BIT(1)}, 500 {"RSF5", BIT(2)}, 501 {"ACE_2", BIT(3)}, 502 {"ACE_4", BIT(4)}, 503 {"RSVD29", BIT(5)}, 504 {"RSF10", BIT(6)}, 505 {"MPFPW5", BIT(7)}, 506 507 {"PSF9", BIT(0)}, 508 {"MPFPW4", BIT(1)}, 509 {"RSVD34", BIT(2)}, 510 {"RSVD35", BIT(3)}, 511 {"RSVD36", BIT(4)}, 512 {"RSVD37", BIT(5)}, 513 {"RSVD38", BIT(6)}, 514 {"RSVD39", BIT(7)}, 515 516 {"SBR0", BIT(0)}, 517 {"SBR1", BIT(1)}, 518 {"SBR2", BIT(2)}, 519 {"SBR3", BIT(3)}, 520 {"SBR4", BIT(4)}, 521 {"SBR5", BIT(5)}, 522 {"RSVD46", BIT(6)}, 523 {"RSVD47", BIT(7)}, 524 525 {"RSVD48", BIT(0)}, 526 {"FIA_P5", BIT(1)}, 527 {"RSVD50", BIT(2)}, 528 {"RSVD51", BIT(3)}, 529 {"RSVD52", BIT(4)}, 530 {"RSVD53", BIT(5)}, 531 {"RSVD54", BIT(6)}, 532 {"ACE_1", BIT(7)}, 533 534 {"RSVD56", BIT(0)}, 535 {"ACE_5", BIT(1)}, 536 {"RSVD58", BIT(2)}, 537 {"G5FPW1", BIT(3)}, 538 {"RSVD60", BIT(4)}, 539 {"ACE_6", BIT(5)}, 540 {"RSVD62", BIT(6)}, 541 {"GBETSN1", BIT(7)}, 542 543 {"RSVD64", BIT(0)}, 544 {"FIA", BIT(1)}, 545 {"RSVD66", BIT(2)}, 546 {"FIA_P", BIT(3)}, 547 {"TAM", BIT(4)}, 548 {"GBETSN", BIT(5)}, 549 {"IOE_D2D_2", BIT(6)}, 550 {"IOE_D2D_1", BIT(7)}, 551 552 {"SPF", BIT(0)}, 553 {"PMC_1", BIT(1)}, 554 {} 555 }; 556 557 const struct pmc_bit_map *ext_mtl_ioep_pfear_map[] = { 558 mtl_ioep_pfear_map, 559 NULL 560 }; 561 562 const struct pmc_bit_map mtl_ioep_ltr_show_map[] = { 563 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 564 {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 565 {"SATA", CNP_PMC_LTR_SATA}, 566 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 567 {"XHCI", CNP_PMC_LTR_XHCI}, 568 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 569 {"ME", CNP_PMC_LTR_ME}, 570 {"SATA1", CNP_PMC_LTR_EVA}, 571 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 572 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 573 {"CNV", CNP_PMC_LTR_CNV}, 574 {"LPSS", CNP_PMC_LTR_LPSS}, 575 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 576 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 577 {"SATA2", CNP_PMC_LTR_CAM}, 578 {"ESPI", CNP_PMC_LTR_ESPI}, 579 {"SCC", CNP_PMC_LTR_SCC}, 580 {"Reserved", MTL_PMC_LTR_RESERVED}, 581 {"UFSX2", CNP_PMC_LTR_UFSX2}, 582 {"EMMC", CNP_PMC_LTR_EMMC}, 583 {"WIGIG", ICL_PMC_LTR_WIGIG}, 584 {"THC0", TGL_PMC_LTR_THC0}, 585 {"THC1", TGL_PMC_LTR_THC1}, 586 {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, 587 588 /* Below two cannot be used for LTR_IGNORE */ 589 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, 590 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, 591 {} 592 }; 593 594 const struct pmc_bit_map mtl_ioep_clocksource_status_map[] = { 595 {"AON2_OFF_STS", BIT(0)}, 596 {"AON3_OFF_STS", BIT(1)}, 597 {"AON4_OFF_STS", BIT(2)}, 598 {"AON5_OFF_STS", BIT(3)}, 599 {"AON1_OFF_STS", BIT(4)}, 600 {"TBT_PLL_OFF_STS", BIT(5)}, 601 {"TMU_PLL_OFF_STS", BIT(6)}, 602 {"BCLK_PLL_OFF_STS", BIT(7)}, 603 {"D2D_PLL_OFF_STS", BIT(8)}, 604 {"AON3_SPL_OFF_STS", BIT(9)}, 605 {"MPFPW4_0_PLL_OFF_STS", BIT(12)}, 606 {"MPFPW5_0_PLL_OFF_STS", BIT(13)}, 607 {"G5FPW_0_PLL_OFF_STS", BIT(14)}, 608 {"G5FPW_1_PLL_OFF_STS", BIT(15)}, 609 {"XTAL_AGGR_OFF_STS", BIT(17)}, 610 {"FABRIC_PLL_OFF_STS", BIT(25)}, 611 {"SOC_PLL_OFF_STS", BIT(26)}, 612 {"REF_PLL_OFF_STS", BIT(28)}, 613 {"RTC_PLL_OFF_STS", BIT(31)}, 614 {} 615 }; 616 617 const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[] = { 618 {"PMC_PGD0_PG_STS", BIT(0)}, 619 {"DMI_PGD0_PG_STS", BIT(1)}, 620 {"TCSS_PGD0_PG_STS", BIT(2)}, 621 {"SPA_PGD0_PG_STS", BIT(4)}, 622 {"SPB_PGD0_PG_STS", BIT(5)}, 623 {"SPC_PGD0_PG_STS", BIT(6)}, 624 {"IOE_D2D_PGD3_PG_STS", BIT(7)}, 625 {"SPE_PGD0_PG_STS", BIT(10)}, 626 {"SPD_PGD0_PG_STS", BIT(13)}, 627 {"ACE_PGD7_PG_STS", BIT(14)}, 628 {"ACE_PGD0_PG_STS", BIT(16)}, 629 {"FIACPCB_P_PGD0_PG_STS", BIT(17)}, 630 {"P2S_PGD0_PG_STS", BIT(18)}, 631 {"ACE_PGD8_PG_STS", BIT(20)}, 632 {"IOE_D2D_PGD0_PG_STS", BIT(21)}, 633 {"FUSE_PGD0_PG_STS", BIT(22)}, 634 {"FIACPCB_P5_PGD0_PG_STS", BIT(24)}, 635 {"ACE_PGD3_PG_STS", BIT(25)}, 636 {"PSF5_PGD0_PG_STS", BIT(26)}, 637 {"ACE_PGD2_PG_STS", BIT(27)}, 638 {"ACE_PGD4_PG_STS", BIT(28)}, 639 {"PSF10_PGD0_PG_STS", BIT(30)}, 640 {"MPFPW5_PGD0_PG_STS", BIT(31)}, 641 {} 642 }; 643 644 const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[] = { 645 {"PSF9_PGD0_PG_STS", BIT(0)}, 646 {"MPFPW4_PGD0_PG_STS", BIT(1)}, 647 {"SBR0_PGD0_PG_STS", BIT(8)}, 648 {"SBR1_PGD0_PG_STS", BIT(9)}, 649 {"SBR2_PGD0_PG_STS", BIT(10)}, 650 {"SBR3_PGD0_PG_STS", BIT(11)}, 651 {"SBR4_PGD0_PG_STS", BIT(12)}, 652 {"SBR5_PGD0_PG_STS", BIT(13)}, 653 {"FIA_P5_PGD0_PG_STS", BIT(17)}, 654 {"ACE_PGD1_PGD0_PG_STS", BIT(23)}, 655 {"ACE_PGD5_PGD1_PG_STS", BIT(25)}, 656 {"G5FPW1_PGD0_PG_STS", BIT(27)}, 657 {"ACE_PGD6_PG_STS", BIT(29)}, 658 {"GBETSN1_PGD0_PG_STS", BIT(31)}, 659 {} 660 }; 661 662 const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[] = { 663 {"FIA_PGD0_PG_STS", BIT(1)}, 664 {"FIA_P_PGD0_PG_STS", BIT(3)}, 665 {"TAM_PGD0_PG_STS", BIT(4)}, 666 {"GBETSN_PGD0_PG_STS", BIT(5)}, 667 {"IOE_D2D_PGD2_PG_STS", BIT(6)}, 668 {"IOE_D2D_PGD1_PG_STS", BIT(7)}, 669 {"SPF_PGD0_PG_STS", BIT(8)}, 670 {"PMC_PGD1_PG_STS", BIT(9)}, 671 {} 672 }; 673 674 const struct pmc_bit_map mtl_ioep_d3_status_0_map[] = { 675 {"SPF_D3_STS", BIT(0)}, 676 {"SPA_D3_STS", BIT(12)}, 677 {"SPB_D3_STS", BIT(13)}, 678 {"SPC_D3_STS", BIT(14)}, 679 {"SPD_D3_STS", BIT(15)}, 680 {"SPE_D3_STS", BIT(16)}, 681 {"DMI_D3_STS", BIT(22)}, 682 {} 683 }; 684 685 const struct pmc_bit_map mtl_ioep_d3_status_1_map[] = { 686 {"GBETSN1_D3_STS", BIT(14)}, 687 {"P2S_D3_STS", BIT(24)}, 688 {} 689 }; 690 691 const struct pmc_bit_map mtl_ioep_d3_status_2_map[] = { 692 {} 693 }; 694 695 const struct pmc_bit_map mtl_ioep_d3_status_3_map[] = { 696 {"GBETSN_D3_STS", BIT(13)}, 697 {"ACE_D3_STS", BIT(23)}, 698 {} 699 }; 700 701 const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[] = { 702 {"FIA_VNN_REQ_STS", BIT(17)}, 703 {} 704 }; 705 706 const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[] = { 707 {"DFXAGG_VNN_REQ_STS", BIT(8)}, 708 {} 709 }; 710 711 const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[] = { 712 {} 713 }; 714 715 const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[] = { 716 {"DTS0_VNN_REQ_STS", BIT(7)}, 717 {"DISP_VNN_REQ_STS", BIT(19)}, 718 {} 719 }; 720 721 const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[] = { 722 {"CPU_C10_REQ_STS", BIT(0)}, 723 {"TS_OFF_REQ_STS", BIT(1)}, 724 {"PNDE_MET_REQ_STS", BIT(2)}, 725 {"PCIE_DEEP_PM_REQ_STS", BIT(3)}, 726 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)}, 727 {"NPK_VNNAON_REQ_STS", BIT(5)}, 728 {"VNN_SOC_REQ_STS", BIT(6)}, 729 {"USB_DEVICE_ATTACHED_REQ_STS", BIT(8)}, 730 {"FIA_EXIT_REQ_STS", BIT(9)}, 731 {"USB2_SUS_PG_REQ_STS", BIT(10)}, 732 {"PLT_GREATER_REQ_STS", BIT(11)}, 733 {"PCIE_CLKREQ_REQ_STS", BIT(12)}, 734 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)}, 735 {"PM_SYNC_STATES_REQ_STS", BIT(14)}, 736 {"EA_REQ_STS", BIT(15)}, 737 {"MPHY_CORE_OFF_REQ_STS", BIT(16)}, 738 {"BRK_EV_EN_REQ_STS", BIT(17)}, 739 {"AUTO_DEMO_EN_REQ_STS", BIT(18)}, 740 {"ITSS_CLK_SRC_REQ_STS", BIT(19)}, 741 {"LPC_CLK_SRC_REQ_STS", BIT(20)}, 742 {"ARC_IDLE_REQ_STS", BIT(21)}, 743 {"MPHY_SUS_REQ_STS", BIT(22)}, 744 {"FIA_DEEP_PM_REQ_STS", BIT(23)}, 745 {"UXD_CONNECTED_REQ_STS", BIT(24)}, 746 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)}, 747 {"USB2_VNNAON_ACT_REQ_STS", BIT(26)}, 748 {"PRE_WAKE0_REQ_STS", BIT(27)}, 749 {"PRE_WAKE1_REQ_STS", BIT(28)}, 750 {"PRE_WAKE2_EN_REQ_STS", BIT(29)}, 751 {"WOV_REQ_STS", BIT(30)}, 752 {"CNVI_V1P05_REQ_STS", BIT(31)}, 753 {} 754 }; 755 756 const struct pmc_bit_map *mtl_ioep_lpm_maps[] = { 757 mtl_ioep_clocksource_status_map, 758 mtl_ioep_power_gating_status_0_map, 759 mtl_ioep_power_gating_status_1_map, 760 mtl_ioep_power_gating_status_2_map, 761 mtl_ioep_d3_status_0_map, 762 mtl_ioep_d3_status_1_map, 763 mtl_ioep_d3_status_2_map, 764 mtl_ioep_d3_status_3_map, 765 mtl_ioep_vnn_req_status_0_map, 766 mtl_ioep_vnn_req_status_1_map, 767 mtl_ioep_vnn_req_status_2_map, 768 mtl_ioep_vnn_req_status_3_map, 769 mtl_ioep_vnn_misc_status_map, 770 mtl_socm_signal_status_map, 771 NULL 772 }; 773 774 const struct pmc_reg_map mtl_ioep_reg_map = { 775 .regmap_length = MTL_IOE_PMC_MMIO_REG_LEN, 776 .pfear_sts = ext_mtl_ioep_pfear_map, 777 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 778 .ppfear_buckets = MTL_IOE_PPFEAR_NUM_ENTRIES, 779 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 780 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 781 .lpm_sts = mtl_ioep_lpm_maps, 782 .ltr_show_sts = mtl_ioep_ltr_show_map, 783 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 784 .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, 785 }; 786 787 const struct pmc_bit_map mtl_ioem_pfear_map[] = { 788 {"PMC_0", BIT(0)}, 789 {"OPI", BIT(1)}, 790 {"TCSS", BIT(2)}, 791 {"RSVD3", BIT(3)}, 792 {"SPA", BIT(4)}, 793 {"SPB", BIT(5)}, 794 {"SPC", BIT(6)}, 795 {"IOE_D2D_3", BIT(7)}, 796 797 {"RSVD8", BIT(0)}, 798 {"RSVD9", BIT(1)}, 799 {"SPE", BIT(2)}, 800 {"RSVD11", BIT(3)}, 801 {"RSVD12", BIT(4)}, 802 {"SPD", BIT(5)}, 803 {"ACE_7", BIT(6)}, 804 {"RSVD15", BIT(7)}, 805 806 {"ACE_0", BIT(0)}, 807 {"FIACPCB_P", BIT(1)}, 808 {"P2S", BIT(2)}, 809 {"RSVD19", BIT(3)}, 810 {"ACE_8", BIT(4)}, 811 {"IOE_D2D_0", BIT(5)}, 812 {"FUSE", BIT(6)}, 813 {"RSVD23", BIT(7)}, 814 815 {"FIACPCB_P5", BIT(0)}, 816 {"ACE_3", BIT(1)}, 817 {"RSF5", BIT(2)}, 818 {"ACE_2", BIT(3)}, 819 {"ACE_4", BIT(4)}, 820 {"RSVD29", BIT(5)}, 821 {"RSF10", BIT(6)}, 822 {"MPFPW5", BIT(7)}, 823 824 {"PSF9", BIT(0)}, 825 {"MPFPW4", BIT(1)}, 826 {"RSVD34", BIT(2)}, 827 {"RSVD35", BIT(3)}, 828 {"RSVD36", BIT(4)}, 829 {"RSVD37", BIT(5)}, 830 {"RSVD38", BIT(6)}, 831 {"RSVD39", BIT(7)}, 832 833 {"SBR0", BIT(0)}, 834 {"SBR1", BIT(1)}, 835 {"SBR2", BIT(2)}, 836 {"SBR3", BIT(3)}, 837 {"SBR4", BIT(4)}, 838 {"RSVD45", BIT(5)}, 839 {"RSVD46", BIT(6)}, 840 {"RSVD47", BIT(7)}, 841 842 {"RSVD48", BIT(0)}, 843 {"FIA_P5", BIT(1)}, 844 {"RSVD50", BIT(2)}, 845 {"RSVD51", BIT(3)}, 846 {"RSVD52", BIT(4)}, 847 {"RSVD53", BIT(5)}, 848 {"RSVD54", BIT(6)}, 849 {"ACE_1", BIT(7)}, 850 851 {"RSVD56", BIT(0)}, 852 {"ACE_5", BIT(1)}, 853 {"RSVD58", BIT(2)}, 854 {"G5FPW1", BIT(3)}, 855 {"RSVD60", BIT(4)}, 856 {"ACE_6", BIT(5)}, 857 {"RSVD62", BIT(6)}, 858 {"GBETSN1", BIT(7)}, 859 860 {"RSVD64", BIT(0)}, 861 {"FIA", BIT(1)}, 862 {"RSVD66", BIT(2)}, 863 {"FIA_P", BIT(3)}, 864 {"TAM", BIT(4)}, 865 {"GBETSN", BIT(5)}, 866 {"IOE_D2D_2", BIT(6)}, 867 {"IOE_D2D_1", BIT(7)}, 868 869 {"SPF", BIT(0)}, 870 {"PMC_1", BIT(1)}, 871 {} 872 }; 873 874 const struct pmc_bit_map *ext_mtl_ioem_pfear_map[] = { 875 mtl_ioem_pfear_map, 876 NULL 877 }; 878 879 const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[] = { 880 {"PSF9_PGD0_PG_STS", BIT(0)}, 881 {"MPFPW4_PGD0_PG_STS", BIT(1)}, 882 {"SBR0_PGD0_PG_STS", BIT(8)}, 883 {"SBR1_PGD0_PG_STS", BIT(9)}, 884 {"SBR2_PGD0_PG_STS", BIT(10)}, 885 {"SBR3_PGD0_PG_STS", BIT(11)}, 886 {"SBR4_PGD0_PG_STS", BIT(12)}, 887 {"FIA_P5_PGD0_PG_STS", BIT(17)}, 888 {"ACE_PGD1_PGD0_PG_STS", BIT(23)}, 889 {"ACE_PGD5_PGD1_PG_STS", BIT(25)}, 890 {"G5FPW1_PGD0_PG_STS", BIT(27)}, 891 {"ACE_PGD6_PG_STS", BIT(29)}, 892 {"GBETSN1_PGD0_PG_STS", BIT(31)}, 893 {} 894 }; 895 896 const struct pmc_bit_map *mtl_ioem_lpm_maps[] = { 897 mtl_ioep_clocksource_status_map, 898 mtl_ioep_power_gating_status_0_map, 899 mtl_ioem_power_gating_status_1_map, 900 mtl_ioep_power_gating_status_2_map, 901 mtl_ioep_d3_status_0_map, 902 mtl_ioep_d3_status_1_map, 903 mtl_ioep_d3_status_2_map, 904 mtl_ioep_d3_status_3_map, 905 mtl_ioep_vnn_req_status_0_map, 906 mtl_ioep_vnn_req_status_1_map, 907 mtl_ioep_vnn_req_status_2_map, 908 mtl_ioep_vnn_req_status_3_map, 909 mtl_ioep_vnn_misc_status_map, 910 mtl_socm_signal_status_map, 911 NULL 912 }; 913 914 const struct pmc_reg_map mtl_ioem_reg_map = { 915 .regmap_length = MTL_IOE_PMC_MMIO_REG_LEN, 916 .pfear_sts = ext_mtl_ioem_pfear_map, 917 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 918 .ppfear_buckets = MTL_IOE_PPFEAR_NUM_ENTRIES, 919 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 920 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 921 .lpm_sts = mtl_ioem_lpm_maps, 922 .ltr_show_sts = mtl_ioep_ltr_show_map, 923 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 924 .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, 925 }; 926 927 #define PMC_DEVID_SOCM 0x7e7f 928 #define PMC_DEVID_IOEP 0x7ecf 929 #define PMC_DEVID_IOEM 0x7ebf 930 static struct pmc_info mtl_pmc_info_list[] = { 931 { 932 .devid = PMC_DEVID_SOCM, 933 .map = &mtl_socm_reg_map, 934 }, 935 { 936 .devid = PMC_DEVID_IOEP, 937 .map = &mtl_ioep_reg_map, 938 }, 939 { 940 .devid = PMC_DEVID_IOEM, 941 .map = &mtl_ioem_reg_map 942 }, 943 {} 944 }; 945 946 #define MTL_GNA_PCI_DEV 0x7e4c 947 #define MTL_IPU_PCI_DEV 0x7d19 948 #define MTL_VPU_PCI_DEV 0x7d1d 949 static void mtl_set_device_d3(unsigned int device) 950 { 951 struct pci_dev *pcidev; 952 953 pcidev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 954 if (pcidev) { 955 if (!device_trylock(&pcidev->dev)) { 956 pci_dev_put(pcidev); 957 return; 958 } 959 if (!pcidev->dev.driver) { 960 dev_info(&pcidev->dev, "Setting to D3hot\n"); 961 pci_set_power_state(pcidev, PCI_D3hot); 962 } 963 device_unlock(&pcidev->dev); 964 pci_dev_put(pcidev); 965 } 966 } 967 968 /* 969 * Set power state of select devices that do not have drivers to D3 970 * so that they do not block Package C entry. 971 */ 972 static void mtl_d3_fixup(void) 973 { 974 mtl_set_device_d3(MTL_GNA_PCI_DEV); 975 mtl_set_device_d3(MTL_IPU_PCI_DEV); 976 mtl_set_device_d3(MTL_VPU_PCI_DEV); 977 } 978 979 static int mtl_resume(struct pmc_dev *pmcdev) 980 { 981 mtl_d3_fixup(); 982 return pmc_core_resume_common(pmcdev); 983 } 984 985 int mtl_core_init(struct pmc_dev *pmcdev) 986 { 987 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC]; 988 int ret = 0; 989 990 mtl_d3_fixup(); 991 992 pmcdev->resume = mtl_resume; 993 994 pmcdev->regmap_list = mtl_pmc_info_list; 995 pmc_core_ssram_init(pmcdev); 996 997 /* If regbase not assigned, set map and discover using legacy method */ 998 if (!pmc->regbase) { 999 pmc->map = &mtl_socm_reg_map; 1000 ret = get_primary_reg_base(pmc); 1001 if (ret) 1002 return ret; 1003 } 1004 1005 /* Due to a hardware limitation, the GBE LTR blocks PC10 1006 * when a cable is attached. Tell the PMC to ignore it. 1007 */ 1008 dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n"); 1009 pmc_core_send_ltr_ignore(pmcdev, 3); 1010 1011 return 0; 1012 } 1013