1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Intel Core SoC Power Management Controller Header File 4 * 5 * Copyright (c) 2016, Intel Corporation. 6 * All Rights Reserved. 7 * 8 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> 9 * Vishwanath Somayaji <vishwanath.somayaji@intel.com> 10 */ 11 12 #ifndef PMC_CORE_H 13 #define PMC_CORE_H 14 15 #include <linux/acpi.h> 16 #include <linux/bits.h> 17 #include <linux/platform_device.h> 18 19 #define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0) 20 21 #define PMC_BASE_ADDR_DEFAULT 0xFE000000 22 23 /* Sunrise Point Power Management Controller PCI Device ID */ 24 #define SPT_PMC_PCI_DEVICE_ID 0x9d21 25 #define SPT_PMC_BASE_ADDR_OFFSET 0x48 26 #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c 27 #define SPT_PMC_PM_CFG_OFFSET 0x18 28 #define SPT_PMC_PM_STS_OFFSET 0x1c 29 #define SPT_PMC_MTPMC_OFFSET 0x20 30 #define SPT_PMC_MFPMC_OFFSET 0x38 31 #define SPT_PMC_LTR_IGNORE_OFFSET 0x30C 32 #define SPT_PMC_VRIC1_OFFSET 0x31c 33 #define SPT_PMC_MPHY_CORE_STS_0 0x1143 34 #define SPT_PMC_MPHY_CORE_STS_1 0x1142 35 #define SPT_PMC_MPHY_COM_STS_0 0x1155 36 #define SPT_PMC_MMIO_REG_LEN 0x1000 37 #define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x68 38 #define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1) 39 #define MTPMC_MASK 0xffff0000 40 #define PPFEAR_MAX_NUM_ENTRIES 12 41 #define SPT_PPFEAR_NUM_ENTRIES 5 42 #define SPT_PMC_READ_DISABLE_BIT 0x16 43 #define SPT_PMC_MSG_FULL_STS_BIT 0x18 44 #define NUM_RETRIES 100 45 #define SPT_NUM_IP_IGN_ALLOWED 17 46 47 #define SPT_PMC_LTR_CUR_PLT 0x350 48 #define SPT_PMC_LTR_CUR_ASLT 0x354 49 #define SPT_PMC_LTR_SPA 0x360 50 #define SPT_PMC_LTR_SPB 0x364 51 #define SPT_PMC_LTR_SATA 0x368 52 #define SPT_PMC_LTR_GBE 0x36C 53 #define SPT_PMC_LTR_XHCI 0x370 54 #define SPT_PMC_LTR_RESERVED 0x374 55 #define SPT_PMC_LTR_ME 0x378 56 #define SPT_PMC_LTR_EVA 0x37C 57 #define SPT_PMC_LTR_SPC 0x380 58 #define SPT_PMC_LTR_AZ 0x384 59 #define SPT_PMC_LTR_LPSS 0x38C 60 #define SPT_PMC_LTR_CAM 0x390 61 #define SPT_PMC_LTR_SPD 0x394 62 #define SPT_PMC_LTR_SPE 0x398 63 #define SPT_PMC_LTR_ESPI 0x39C 64 #define SPT_PMC_LTR_SCC 0x3A0 65 #define SPT_PMC_LTR_ISH 0x3A4 66 67 /* Sunrise Point: PGD PFET Enable Ack Status Registers */ 68 enum ppfear_regs { 69 SPT_PMC_XRAM_PPFEAR0A = 0x590, 70 SPT_PMC_XRAM_PPFEAR0B, 71 SPT_PMC_XRAM_PPFEAR0C, 72 SPT_PMC_XRAM_PPFEAR0D, 73 SPT_PMC_XRAM_PPFEAR1A, 74 }; 75 76 #define SPT_PMC_BIT_PMC BIT(0) 77 #define SPT_PMC_BIT_OPI BIT(1) 78 #define SPT_PMC_BIT_SPI BIT(2) 79 #define SPT_PMC_BIT_XHCI BIT(3) 80 #define SPT_PMC_BIT_SPA BIT(4) 81 #define SPT_PMC_BIT_SPB BIT(5) 82 #define SPT_PMC_BIT_SPC BIT(6) 83 #define SPT_PMC_BIT_GBE BIT(7) 84 85 #define SPT_PMC_BIT_SATA BIT(0) 86 #define SPT_PMC_BIT_HDA_PGD0 BIT(1) 87 #define SPT_PMC_BIT_HDA_PGD1 BIT(2) 88 #define SPT_PMC_BIT_HDA_PGD2 BIT(3) 89 #define SPT_PMC_BIT_HDA_PGD3 BIT(4) 90 #define SPT_PMC_BIT_RSVD_0B BIT(5) 91 #define SPT_PMC_BIT_LPSS BIT(6) 92 #define SPT_PMC_BIT_LPC BIT(7) 93 94 #define SPT_PMC_BIT_SMB BIT(0) 95 #define SPT_PMC_BIT_ISH BIT(1) 96 #define SPT_PMC_BIT_P2SB BIT(2) 97 #define SPT_PMC_BIT_DFX BIT(3) 98 #define SPT_PMC_BIT_SCC BIT(4) 99 #define SPT_PMC_BIT_RSVD_0C BIT(5) 100 #define SPT_PMC_BIT_FUSE BIT(6) 101 #define SPT_PMC_BIT_CAMREA BIT(7) 102 103 #define SPT_PMC_BIT_RSVD_0D BIT(0) 104 #define SPT_PMC_BIT_USB3_OTG BIT(1) 105 #define SPT_PMC_BIT_EXI BIT(2) 106 #define SPT_PMC_BIT_CSE BIT(3) 107 #define SPT_PMC_BIT_CSME_KVM BIT(4) 108 #define SPT_PMC_BIT_CSME_PMT BIT(5) 109 #define SPT_PMC_BIT_CSME_CLINK BIT(6) 110 #define SPT_PMC_BIT_CSME_PTIO BIT(7) 111 112 #define SPT_PMC_BIT_CSME_USBR BIT(0) 113 #define SPT_PMC_BIT_CSME_SUSRAM BIT(1) 114 #define SPT_PMC_BIT_CSME_SMT BIT(2) 115 #define SPT_PMC_BIT_RSVD_1A BIT(3) 116 #define SPT_PMC_BIT_CSME_SMS2 BIT(4) 117 #define SPT_PMC_BIT_CSME_SMS1 BIT(5) 118 #define SPT_PMC_BIT_CSME_RTC BIT(6) 119 #define SPT_PMC_BIT_CSME_PSF BIT(7) 120 121 #define SPT_PMC_BIT_MPHY_LANE0 BIT(0) 122 #define SPT_PMC_BIT_MPHY_LANE1 BIT(1) 123 #define SPT_PMC_BIT_MPHY_LANE2 BIT(2) 124 #define SPT_PMC_BIT_MPHY_LANE3 BIT(3) 125 #define SPT_PMC_BIT_MPHY_LANE4 BIT(4) 126 #define SPT_PMC_BIT_MPHY_LANE5 BIT(5) 127 #define SPT_PMC_BIT_MPHY_LANE6 BIT(6) 128 #define SPT_PMC_BIT_MPHY_LANE7 BIT(7) 129 130 #define SPT_PMC_BIT_MPHY_LANE8 BIT(0) 131 #define SPT_PMC_BIT_MPHY_LANE9 BIT(1) 132 #define SPT_PMC_BIT_MPHY_LANE10 BIT(2) 133 #define SPT_PMC_BIT_MPHY_LANE11 BIT(3) 134 #define SPT_PMC_BIT_MPHY_LANE12 BIT(4) 135 #define SPT_PMC_BIT_MPHY_LANE13 BIT(5) 136 #define SPT_PMC_BIT_MPHY_LANE14 BIT(6) 137 #define SPT_PMC_BIT_MPHY_LANE15 BIT(7) 138 139 #define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0) 140 #define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1) 141 #define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2) 142 #define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3) 143 144 #define SPT_PMC_VRIC1_SLPS0LVEN BIT(13) 145 #define SPT_PMC_VRIC1_XTALSDQDIS BIT(22) 146 147 /* Cannonlake Power Management Controller register offsets */ 148 #define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4 149 #define CNP_PMC_PM_CFG_OFFSET 0x1818 150 #define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C 151 #define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C 152 /* Cannonlake: PGD PFET Enable Ack Status Register(s) start */ 153 #define CNP_PMC_HOST_PPFEAR0A 0x1D90 154 155 #define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31) 156 157 #define CNP_PMC_MMIO_REG_LEN 0x2000 158 #define CNP_PPFEAR_NUM_ENTRIES 8 159 #define CNP_PMC_READ_DISABLE_BIT 22 160 #define CNP_NUM_IP_IGN_ALLOWED 19 161 #define CNP_PMC_LTR_CUR_PLT 0x1B50 162 #define CNP_PMC_LTR_CUR_ASLT 0x1B54 163 #define CNP_PMC_LTR_SPA 0x1B60 164 #define CNP_PMC_LTR_SPB 0x1B64 165 #define CNP_PMC_LTR_SATA 0x1B68 166 #define CNP_PMC_LTR_GBE 0x1B6C 167 #define CNP_PMC_LTR_XHCI 0x1B70 168 #define CNP_PMC_LTR_RESERVED 0x1B74 169 #define CNP_PMC_LTR_ME 0x1B78 170 #define CNP_PMC_LTR_EVA 0x1B7C 171 #define CNP_PMC_LTR_SPC 0x1B80 172 #define CNP_PMC_LTR_AZ 0x1B84 173 #define CNP_PMC_LTR_LPSS 0x1B8C 174 #define CNP_PMC_LTR_CAM 0x1B90 175 #define CNP_PMC_LTR_SPD 0x1B94 176 #define CNP_PMC_LTR_SPE 0x1B98 177 #define CNP_PMC_LTR_ESPI 0x1B9C 178 #define CNP_PMC_LTR_SCC 0x1BA0 179 #define CNP_PMC_LTR_ISH 0x1BA4 180 #define CNP_PMC_LTR_CNV 0x1BF0 181 #define CNP_PMC_LTR_EMMC 0x1BF4 182 #define CNP_PMC_LTR_UFSX2 0x1BF8 183 184 #define LTR_DECODED_VAL GENMASK(9, 0) 185 #define LTR_DECODED_SCALE GENMASK(12, 10) 186 #define LTR_REQ_SNOOP BIT(15) 187 #define LTR_REQ_NONSNOOP BIT(31) 188 189 #define ICL_PPFEAR_NUM_ENTRIES 9 190 #define ICL_NUM_IP_IGN_ALLOWED 20 191 #define ICL_PMC_LTR_WIGIG 0x1BFC 192 #define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64 193 194 #define LPM_MAX_NUM_MODES 8 195 #define LPM_DEFAULT_PRI { 7, 6, 2, 5, 4, 1, 3, 0 } 196 197 #define GET_X2_COUNTER(v) ((v) >> 1) 198 #define LPM_STS_LATCH_MODE BIT(31) 199 200 #define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A 201 #define TGL_PMC_LTR_THC0 0x1C04 202 #define TGL_PMC_LTR_THC1 0x1C08 203 #define TGL_NUM_IP_IGN_ALLOWED 23 204 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ 205 206 #define ADL_PMC_LTR_SPF 0x1C00 207 #define ADL_NUM_IP_IGN_ALLOWED 23 208 #define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET 0x1098 209 210 /* 211 * Tigerlake Power Management Controller register offsets 212 */ 213 #define TGL_LPM_STS_LATCH_EN_OFFSET 0x1C34 214 #define TGL_LPM_EN_OFFSET 0x1C78 215 #define TGL_LPM_RESIDENCY_OFFSET 0x1C80 216 217 /* Tigerlake Low Power Mode debug registers */ 218 #define TGL_LPM_STATUS_OFFSET 0x1C3C 219 #define TGL_LPM_LIVE_STATUS_OFFSET 0x1C5C 220 #define TGL_LPM_PRI_OFFSET 0x1C7C 221 #define TGL_LPM_NUM_MAPS 6 222 223 /* Extended Test Mode Register 3 (CNL and later) */ 224 #define ETR3_OFFSET 0x1048 225 #define ETR3_CF9GR BIT(20) 226 #define ETR3_CF9LOCK BIT(31) 227 228 /* Extended Test Mode Register LPM bits (TGL and later */ 229 #define ETR3_CLEAR_LPM_EVENTS BIT(28) 230 231 /* Alder Lake Power Management Controller register offsets */ 232 #define ADL_LPM_EN_OFFSET 0x179C 233 #define ADL_LPM_RESIDENCY_OFFSET 0x17A4 234 #define ADL_LPM_NUM_MODES 2 235 #define ADL_LPM_NUM_MAPS 14 236 237 /* Alder Lake Low Power Mode debug registers */ 238 #define ADL_LPM_STATUS_OFFSET 0x170C 239 #define ADL_LPM_PRI_OFFSET 0x17A0 240 #define ADL_LPM_STATUS_LATCH_EN_OFFSET 0x1704 241 #define ADL_LPM_LIVE_STATUS_OFFSET 0x1764 242 243 /* Meteor Lake Power Management Controller register offsets */ 244 #define MTL_LPM_EN_OFFSET 0x1798 245 #define MTL_LPM_RESIDENCY_OFFSET 0x17A0 246 247 /* Meteor Lake Low Power Mode debug registers */ 248 #define MTL_LPM_PRI_OFFSET 0x179C 249 #define MTL_LPM_STATUS_LATCH_EN_OFFSET 0x16F8 250 #define MTL_LPM_STATUS_OFFSET 0x1700 251 #define MTL_LPM_LIVE_STATUS_OFFSET 0x175C 252 253 extern const char *pmc_lpm_modes[]; 254 255 struct pmc_bit_map { 256 const char *name; 257 u32 bit_mask; 258 }; 259 260 /** 261 * struct pmc_reg_map - Structure used to define parameter unique to a 262 PCH family 263 * @pfear_sts: Maps name of IP block to PPFEAR* bit 264 * @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit 265 * @pll_sts: Maps name of PLL to corresponding bit status 266 * @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info 267 * @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets 268 * @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency 269 * @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit 270 * @regmap_length: Length of memory to map from PWRMBASE address to access 271 * @ppfear0_offset: PWRMBASE offset to read PPFEAR* 272 * @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from 273 * PPFEAR 274 * @pm_cfg_offset: PWRMBASE offset to PM_CFG register 275 * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE 276 * @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG* 277 * 278 * Each PCH has unique set of register offsets and bit indexes. This structure 279 * captures them to have a common implementation. 280 */ 281 struct pmc_reg_map { 282 const struct pmc_bit_map **pfear_sts; 283 const struct pmc_bit_map *mphy_sts; 284 const struct pmc_bit_map *pll_sts; 285 const struct pmc_bit_map **slps0_dbg_maps; 286 const struct pmc_bit_map *ltr_show_sts; 287 const struct pmc_bit_map *msr_sts; 288 const struct pmc_bit_map **lpm_sts; 289 const u32 slp_s0_offset; 290 const int slp_s0_res_counter_step; 291 const u32 ltr_ignore_offset; 292 const int regmap_length; 293 const u32 ppfear0_offset; 294 const int ppfear_buckets; 295 const u32 pm_cfg_offset; 296 const int pm_read_disable_bit; 297 const u32 slps0_dbg_offset; 298 const u32 ltr_ignore_max; 299 const u32 pm_vric1_offset; 300 /* Low Power Mode registers */ 301 const int lpm_num_maps; 302 const int lpm_num_modes; 303 const int lpm_res_counter_step_x2; 304 const u32 lpm_sts_latch_en_offset; 305 const u32 lpm_en_offset; 306 const u32 lpm_priority_offset; 307 const u32 lpm_residency_offset; 308 const u32 lpm_status_offset; 309 const u32 lpm_live_status_offset; 310 const u32 etr3_offset; 311 }; 312 313 /** 314 * struct pmc_dev - pmc device structure 315 * @base_addr: contains pmc base address 316 * @regbase: pointer to io-remapped memory location 317 * @map: pointer to pmc_reg_map struct that contains platform 318 * specific attributes 319 * @pdev: pointer to platform_device struct 320 * @dbgfs_dir: path to debugfs interface 321 * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers 322 * used to read MPHY PG and PLL status are available 323 * @mutex_lock: mutex to complete one transcation 324 * @pc10_counter: PC10 residency counter 325 * @s0ix_counter: S0ix residency (step adjusted) 326 * @num_lpm_modes: Count of enabled modes 327 * @lpm_en_modes: Array of enabled modes from lowest to highest priority 328 * @lpm_req_regs: List of substate requirements 329 * @core_configure: Function pointer to configure the platform 330 * 331 * pmc_dev contains info about power management controller device. 332 */ 333 struct pmc_dev { 334 u32 base_addr; 335 void __iomem *regbase; 336 const struct pmc_reg_map *map; 337 struct dentry *dbgfs_dir; 338 struct platform_device *pdev; 339 int pmc_xram_read_bit; 340 struct mutex lock; /* generic mutex lock for PMC Core */ 341 342 u64 pc10_counter; 343 u64 s0ix_counter; 344 int num_lpm_modes; 345 int lpm_en_modes[LPM_MAX_NUM_MODES]; 346 u32 *lpm_req_regs; 347 void (*core_configure)(struct pmc_dev *pmcdev); 348 }; 349 350 extern const struct pmc_bit_map msr_map[]; 351 extern const struct pmc_bit_map spt_pll_map[]; 352 extern const struct pmc_bit_map spt_mphy_map[]; 353 extern const struct pmc_bit_map spt_pfear_map[]; 354 extern const struct pmc_bit_map *ext_spt_pfear_map[]; 355 extern const struct pmc_bit_map spt_ltr_show_map[]; 356 extern const struct pmc_reg_map spt_reg_map; 357 extern const struct pmc_bit_map cnp_pfear_map[]; 358 extern const struct pmc_bit_map *ext_cnp_pfear_map[]; 359 extern const struct pmc_bit_map cnp_slps0_dbg0_map[]; 360 extern const struct pmc_bit_map cnp_slps0_dbg1_map[]; 361 extern const struct pmc_bit_map cnp_slps0_dbg2_map[]; 362 extern const struct pmc_bit_map *cnp_slps0_dbg_maps[]; 363 extern const struct pmc_bit_map cnp_ltr_show_map[]; 364 extern const struct pmc_reg_map cnp_reg_map; 365 extern const struct pmc_bit_map icl_pfear_map[]; 366 extern const struct pmc_bit_map *ext_icl_pfear_map[]; 367 extern const struct pmc_reg_map icl_reg_map; 368 extern const struct pmc_bit_map tgl_pfear_map[]; 369 extern const struct pmc_bit_map *ext_tgl_pfear_map[]; 370 extern const struct pmc_bit_map tgl_clocksource_status_map[]; 371 extern const struct pmc_bit_map tgl_power_gating_status_map[]; 372 extern const struct pmc_bit_map tgl_d3_status_map[]; 373 extern const struct pmc_bit_map tgl_vnn_req_status_map[]; 374 extern const struct pmc_bit_map tgl_vnn_misc_status_map[]; 375 extern const struct pmc_bit_map tgl_signal_status_map[]; 376 extern const struct pmc_bit_map *tgl_lpm_maps[]; 377 extern const struct pmc_reg_map tgl_reg_map; 378 extern const struct pmc_bit_map adl_pfear_map[]; 379 extern const struct pmc_bit_map *ext_adl_pfear_map[]; 380 extern const struct pmc_bit_map adl_ltr_show_map[]; 381 extern const struct pmc_bit_map adl_clocksource_status_map[]; 382 extern const struct pmc_bit_map adl_power_gating_status_0_map[]; 383 extern const struct pmc_bit_map adl_power_gating_status_1_map[]; 384 extern const struct pmc_bit_map adl_power_gating_status_2_map[]; 385 extern const struct pmc_bit_map adl_d3_status_0_map[]; 386 extern const struct pmc_bit_map adl_d3_status_1_map[]; 387 extern const struct pmc_bit_map adl_d3_status_2_map[]; 388 extern const struct pmc_bit_map adl_d3_status_3_map[]; 389 extern const struct pmc_bit_map adl_vnn_req_status_0_map[]; 390 extern const struct pmc_bit_map adl_vnn_req_status_1_map[]; 391 extern const struct pmc_bit_map adl_vnn_req_status_2_map[]; 392 extern const struct pmc_bit_map adl_vnn_req_status_3_map[]; 393 extern const struct pmc_bit_map adl_vnn_misc_status_map[]; 394 extern const struct pmc_bit_map *adl_lpm_maps[]; 395 extern const struct pmc_reg_map adl_reg_map; 396 extern const struct pmc_reg_map mtl_reg_map; 397 398 extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev); 399 extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value); 400 401 void spt_core_init(struct pmc_dev *pmcdev); 402 void cnp_core_init(struct pmc_dev *pmcdev); 403 void icl_core_init(struct pmc_dev *pmcdev); 404 void tgl_core_init(struct pmc_dev *pmcdev); 405 void adl_core_init(struct pmc_dev *pmcdev); 406 void mtl_core_init(struct pmc_dev *pmcdev); 407 void tgl_core_configure(struct pmc_dev *pmcdev); 408 void adl_core_configure(struct pmc_dev *pmcdev); 409 void mtl_core_configure(struct pmc_dev *pmcdev); 410 411 #define pmc_for_each_mode(i, mode, pmcdev) \ 412 for (i = 0, mode = pmcdev->lpm_en_modes[i]; \ 413 i < pmcdev->num_lpm_modes; \ 414 i++, mode = pmcdev->lpm_en_modes[i]) 415 416 #define DEFINE_PMC_CORE_ATTR_WRITE(__name) \ 417 static int __name ## _open(struct inode *inode, struct file *file) \ 418 { \ 419 return single_open(file, __name ## _show, inode->i_private); \ 420 } \ 421 \ 422 static const struct file_operations __name ## _fops = { \ 423 .owner = THIS_MODULE, \ 424 .open = __name ## _open, \ 425 .read = seq_read, \ 426 .write = __name ## _write, \ 427 .release = single_release, \ 428 } 429 430 #endif /* PMC_CORE_H */ 431