1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Intel Core SoC Power Management Controller Header File 4 * 5 * Copyright (c) 2016, Intel Corporation. 6 * All Rights Reserved. 7 * 8 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> 9 * Vishwanath Somayaji <vishwanath.somayaji@intel.com> 10 */ 11 12 #ifndef PMC_CORE_H 13 #define PMC_CORE_H 14 15 #include <linux/acpi.h> 16 #include <linux/bits.h> 17 #include <linux/platform_device.h> 18 19 #define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0) 20 21 #define PMC_BASE_ADDR_DEFAULT 0xFE000000 22 #define MAX_NUM_PMC 3 23 24 /* Sunrise Point Power Management Controller PCI Device ID */ 25 #define SPT_PMC_PCI_DEVICE_ID 0x9d21 26 #define SPT_PMC_BASE_ADDR_OFFSET 0x48 27 #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c 28 #define SPT_PMC_PM_CFG_OFFSET 0x18 29 #define SPT_PMC_PM_STS_OFFSET 0x1c 30 #define SPT_PMC_MTPMC_OFFSET 0x20 31 #define SPT_PMC_MFPMC_OFFSET 0x38 32 #define SPT_PMC_LTR_IGNORE_OFFSET 0x30C 33 #define SPT_PMC_VRIC1_OFFSET 0x31c 34 #define SPT_PMC_MPHY_CORE_STS_0 0x1143 35 #define SPT_PMC_MPHY_CORE_STS_1 0x1142 36 #define SPT_PMC_MPHY_COM_STS_0 0x1155 37 #define SPT_PMC_MMIO_REG_LEN 0x1000 38 #define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x68 39 #define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1) 40 #define MTPMC_MASK 0xffff0000 41 #define PPFEAR_MAX_NUM_ENTRIES 12 42 #define SPT_PPFEAR_NUM_ENTRIES 5 43 #define SPT_PMC_READ_DISABLE_BIT 0x16 44 #define SPT_PMC_MSG_FULL_STS_BIT 0x18 45 #define NUM_RETRIES 100 46 #define SPT_NUM_IP_IGN_ALLOWED 17 47 48 #define SPT_PMC_LTR_CUR_PLT 0x350 49 #define SPT_PMC_LTR_CUR_ASLT 0x354 50 #define SPT_PMC_LTR_SPA 0x360 51 #define SPT_PMC_LTR_SPB 0x364 52 #define SPT_PMC_LTR_SATA 0x368 53 #define SPT_PMC_LTR_GBE 0x36C 54 #define SPT_PMC_LTR_XHCI 0x370 55 #define SPT_PMC_LTR_RESERVED 0x374 56 #define SPT_PMC_LTR_ME 0x378 57 #define SPT_PMC_LTR_EVA 0x37C 58 #define SPT_PMC_LTR_SPC 0x380 59 #define SPT_PMC_LTR_AZ 0x384 60 #define SPT_PMC_LTR_LPSS 0x38C 61 #define SPT_PMC_LTR_CAM 0x390 62 #define SPT_PMC_LTR_SPD 0x394 63 #define SPT_PMC_LTR_SPE 0x398 64 #define SPT_PMC_LTR_ESPI 0x39C 65 #define SPT_PMC_LTR_SCC 0x3A0 66 #define SPT_PMC_LTR_ISH 0x3A4 67 68 /* Sunrise Point: PGD PFET Enable Ack Status Registers */ 69 enum ppfear_regs { 70 SPT_PMC_XRAM_PPFEAR0A = 0x590, 71 SPT_PMC_XRAM_PPFEAR0B, 72 SPT_PMC_XRAM_PPFEAR0C, 73 SPT_PMC_XRAM_PPFEAR0D, 74 SPT_PMC_XRAM_PPFEAR1A, 75 }; 76 77 #define SPT_PMC_BIT_PMC BIT(0) 78 #define SPT_PMC_BIT_OPI BIT(1) 79 #define SPT_PMC_BIT_SPI BIT(2) 80 #define SPT_PMC_BIT_XHCI BIT(3) 81 #define SPT_PMC_BIT_SPA BIT(4) 82 #define SPT_PMC_BIT_SPB BIT(5) 83 #define SPT_PMC_BIT_SPC BIT(6) 84 #define SPT_PMC_BIT_GBE BIT(7) 85 86 #define SPT_PMC_BIT_SATA BIT(0) 87 #define SPT_PMC_BIT_HDA_PGD0 BIT(1) 88 #define SPT_PMC_BIT_HDA_PGD1 BIT(2) 89 #define SPT_PMC_BIT_HDA_PGD2 BIT(3) 90 #define SPT_PMC_BIT_HDA_PGD3 BIT(4) 91 #define SPT_PMC_BIT_RSVD_0B BIT(5) 92 #define SPT_PMC_BIT_LPSS BIT(6) 93 #define SPT_PMC_BIT_LPC BIT(7) 94 95 #define SPT_PMC_BIT_SMB BIT(0) 96 #define SPT_PMC_BIT_ISH BIT(1) 97 #define SPT_PMC_BIT_P2SB BIT(2) 98 #define SPT_PMC_BIT_DFX BIT(3) 99 #define SPT_PMC_BIT_SCC BIT(4) 100 #define SPT_PMC_BIT_RSVD_0C BIT(5) 101 #define SPT_PMC_BIT_FUSE BIT(6) 102 #define SPT_PMC_BIT_CAMREA BIT(7) 103 104 #define SPT_PMC_BIT_RSVD_0D BIT(0) 105 #define SPT_PMC_BIT_USB3_OTG BIT(1) 106 #define SPT_PMC_BIT_EXI BIT(2) 107 #define SPT_PMC_BIT_CSE BIT(3) 108 #define SPT_PMC_BIT_CSME_KVM BIT(4) 109 #define SPT_PMC_BIT_CSME_PMT BIT(5) 110 #define SPT_PMC_BIT_CSME_CLINK BIT(6) 111 #define SPT_PMC_BIT_CSME_PTIO BIT(7) 112 113 #define SPT_PMC_BIT_CSME_USBR BIT(0) 114 #define SPT_PMC_BIT_CSME_SUSRAM BIT(1) 115 #define SPT_PMC_BIT_CSME_SMT BIT(2) 116 #define SPT_PMC_BIT_RSVD_1A BIT(3) 117 #define SPT_PMC_BIT_CSME_SMS2 BIT(4) 118 #define SPT_PMC_BIT_CSME_SMS1 BIT(5) 119 #define SPT_PMC_BIT_CSME_RTC BIT(6) 120 #define SPT_PMC_BIT_CSME_PSF BIT(7) 121 122 #define SPT_PMC_BIT_MPHY_LANE0 BIT(0) 123 #define SPT_PMC_BIT_MPHY_LANE1 BIT(1) 124 #define SPT_PMC_BIT_MPHY_LANE2 BIT(2) 125 #define SPT_PMC_BIT_MPHY_LANE3 BIT(3) 126 #define SPT_PMC_BIT_MPHY_LANE4 BIT(4) 127 #define SPT_PMC_BIT_MPHY_LANE5 BIT(5) 128 #define SPT_PMC_BIT_MPHY_LANE6 BIT(6) 129 #define SPT_PMC_BIT_MPHY_LANE7 BIT(7) 130 131 #define SPT_PMC_BIT_MPHY_LANE8 BIT(0) 132 #define SPT_PMC_BIT_MPHY_LANE9 BIT(1) 133 #define SPT_PMC_BIT_MPHY_LANE10 BIT(2) 134 #define SPT_PMC_BIT_MPHY_LANE11 BIT(3) 135 #define SPT_PMC_BIT_MPHY_LANE12 BIT(4) 136 #define SPT_PMC_BIT_MPHY_LANE13 BIT(5) 137 #define SPT_PMC_BIT_MPHY_LANE14 BIT(6) 138 #define SPT_PMC_BIT_MPHY_LANE15 BIT(7) 139 140 #define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0) 141 #define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1) 142 #define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2) 143 #define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3) 144 145 #define SPT_PMC_VRIC1_SLPS0LVEN BIT(13) 146 #define SPT_PMC_VRIC1_XTALSDQDIS BIT(22) 147 148 /* Cannonlake Power Management Controller register offsets */ 149 #define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4 150 #define CNP_PMC_PM_CFG_OFFSET 0x1818 151 #define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C 152 #define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C 153 /* Cannonlake: PGD PFET Enable Ack Status Register(s) start */ 154 #define CNP_PMC_HOST_PPFEAR0A 0x1D90 155 156 #define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31) 157 158 #define CNP_PMC_MMIO_REG_LEN 0x2000 159 #define CNP_PPFEAR_NUM_ENTRIES 8 160 #define CNP_PMC_READ_DISABLE_BIT 22 161 #define CNP_NUM_IP_IGN_ALLOWED 19 162 #define CNP_PMC_LTR_CUR_PLT 0x1B50 163 #define CNP_PMC_LTR_CUR_ASLT 0x1B54 164 #define CNP_PMC_LTR_SPA 0x1B60 165 #define CNP_PMC_LTR_SPB 0x1B64 166 #define CNP_PMC_LTR_SATA 0x1B68 167 #define CNP_PMC_LTR_GBE 0x1B6C 168 #define CNP_PMC_LTR_XHCI 0x1B70 169 #define CNP_PMC_LTR_RESERVED 0x1B74 170 #define CNP_PMC_LTR_ME 0x1B78 171 #define CNP_PMC_LTR_EVA 0x1B7C 172 #define CNP_PMC_LTR_SPC 0x1B80 173 #define CNP_PMC_LTR_AZ 0x1B84 174 #define CNP_PMC_LTR_LPSS 0x1B8C 175 #define CNP_PMC_LTR_CAM 0x1B90 176 #define CNP_PMC_LTR_SPD 0x1B94 177 #define CNP_PMC_LTR_SPE 0x1B98 178 #define CNP_PMC_LTR_ESPI 0x1B9C 179 #define CNP_PMC_LTR_SCC 0x1BA0 180 #define CNP_PMC_LTR_ISH 0x1BA4 181 #define CNP_PMC_LTR_CNV 0x1BF0 182 #define CNP_PMC_LTR_EMMC 0x1BF4 183 #define CNP_PMC_LTR_UFSX2 0x1BF8 184 185 #define LTR_DECODED_VAL GENMASK(9, 0) 186 #define LTR_DECODED_SCALE GENMASK(12, 10) 187 #define LTR_REQ_SNOOP BIT(15) 188 #define LTR_REQ_NONSNOOP BIT(31) 189 190 #define ICL_PPFEAR_NUM_ENTRIES 9 191 #define ICL_NUM_IP_IGN_ALLOWED 20 192 #define ICL_PMC_LTR_WIGIG 0x1BFC 193 #define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64 194 195 #define LPM_MAX_NUM_MODES 8 196 #define LPM_DEFAULT_PRI { 7, 6, 2, 5, 4, 1, 3, 0 } 197 198 #define GET_X2_COUNTER(v) ((v) >> 1) 199 #define LPM_STS_LATCH_MODE BIT(31) 200 201 #define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A 202 #define TGL_PMC_LTR_THC0 0x1C04 203 #define TGL_PMC_LTR_THC1 0x1C08 204 #define TGL_NUM_IP_IGN_ALLOWED 23 205 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ 206 207 #define ADL_PMC_LTR_SPF 0x1C00 208 #define ADL_NUM_IP_IGN_ALLOWED 23 209 #define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET 0x1098 210 211 /* 212 * Tigerlake Power Management Controller register offsets 213 */ 214 #define TGL_LPM_STS_LATCH_EN_OFFSET 0x1C34 215 #define TGL_LPM_EN_OFFSET 0x1C78 216 #define TGL_LPM_RESIDENCY_OFFSET 0x1C80 217 218 /* Tigerlake Low Power Mode debug registers */ 219 #define TGL_LPM_STATUS_OFFSET 0x1C3C 220 #define TGL_LPM_LIVE_STATUS_OFFSET 0x1C5C 221 #define TGL_LPM_PRI_OFFSET 0x1C7C 222 #define TGL_LPM_NUM_MAPS 6 223 224 /* Extended Test Mode Register 3 (CNL and later) */ 225 #define ETR3_OFFSET 0x1048 226 #define ETR3_CF9GR BIT(20) 227 #define ETR3_CF9LOCK BIT(31) 228 229 /* Extended Test Mode Register LPM bits (TGL and later */ 230 #define ETR3_CLEAR_LPM_EVENTS BIT(28) 231 232 /* Alder Lake Power Management Controller register offsets */ 233 #define ADL_LPM_EN_OFFSET 0x179C 234 #define ADL_LPM_RESIDENCY_OFFSET 0x17A4 235 #define ADL_LPM_NUM_MODES 2 236 #define ADL_LPM_NUM_MAPS 14 237 238 /* Alder Lake Low Power Mode debug registers */ 239 #define ADL_LPM_STATUS_OFFSET 0x170C 240 #define ADL_LPM_PRI_OFFSET 0x17A0 241 #define ADL_LPM_STATUS_LATCH_EN_OFFSET 0x1704 242 #define ADL_LPM_LIVE_STATUS_OFFSET 0x1764 243 244 /* Meteor Lake Power Management Controller register offsets */ 245 #define MTL_LPM_EN_OFFSET 0x1798 246 #define MTL_LPM_RESIDENCY_OFFSET 0x17A0 247 248 /* Meteor Lake Low Power Mode debug registers */ 249 #define MTL_LPM_PRI_OFFSET 0x179C 250 #define MTL_LPM_STATUS_LATCH_EN_OFFSET 0x16F8 251 #define MTL_LPM_STATUS_OFFSET 0x1700 252 #define MTL_LPM_LIVE_STATUS_OFFSET 0x175C 253 #define MTL_PMC_LTR_IOE_PMC 0x1C0C 254 #define MTL_PMC_LTR_ESE 0x1BAC 255 #define MTL_PMC_LTR_RESERVED 0x1BA4 256 #define MTL_IOE_PMC_MMIO_REG_LEN 0x23A4 257 #define MTL_SOCM_NUM_IP_IGN_ALLOWED 25 258 #define MTL_SOC_PMC_MMIO_REG_LEN 0x2708 259 #define MTL_PMC_LTR_SPG 0x1B74 260 261 /* Meteor Lake PGD PFET Enable Ack Status */ 262 #define MTL_SOCM_PPFEAR_NUM_ENTRIES 8 263 #define MTL_IOE_PPFEAR_NUM_ENTRIES 10 264 265 extern const char *pmc_lpm_modes[]; 266 267 struct pmc_bit_map { 268 const char *name; 269 u32 bit_mask; 270 }; 271 272 /** 273 * struct pmc_reg_map - Structure used to define parameter unique to a 274 PCH family 275 * @pfear_sts: Maps name of IP block to PPFEAR* bit 276 * @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit 277 * @pll_sts: Maps name of PLL to corresponding bit status 278 * @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info 279 * @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets 280 * @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency 281 * @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit 282 * @regmap_length: Length of memory to map from PWRMBASE address to access 283 * @ppfear0_offset: PWRMBASE offset to read PPFEAR* 284 * @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from 285 * PPFEAR 286 * @pm_cfg_offset: PWRMBASE offset to PM_CFG register 287 * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE 288 * @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG* 289 * 290 * Each PCH has unique set of register offsets and bit indexes. This structure 291 * captures them to have a common implementation. 292 */ 293 struct pmc_reg_map { 294 const struct pmc_bit_map **pfear_sts; 295 const struct pmc_bit_map *mphy_sts; 296 const struct pmc_bit_map *pll_sts; 297 const struct pmc_bit_map **slps0_dbg_maps; 298 const struct pmc_bit_map *ltr_show_sts; 299 const struct pmc_bit_map *msr_sts; 300 const struct pmc_bit_map **lpm_sts; 301 const u32 slp_s0_offset; 302 const int slp_s0_res_counter_step; 303 const u32 ltr_ignore_offset; 304 const int regmap_length; 305 const u32 ppfear0_offset; 306 const int ppfear_buckets; 307 const u32 pm_cfg_offset; 308 const int pm_read_disable_bit; 309 const u32 slps0_dbg_offset; 310 const u32 ltr_ignore_max; 311 const u32 pm_vric1_offset; 312 /* Low Power Mode registers */ 313 const int lpm_num_maps; 314 const int lpm_num_modes; 315 const int lpm_res_counter_step_x2; 316 const u32 lpm_sts_latch_en_offset; 317 const u32 lpm_en_offset; 318 const u32 lpm_priority_offset; 319 const u32 lpm_residency_offset; 320 const u32 lpm_status_offset; 321 const u32 lpm_live_status_offset; 322 const u32 etr3_offset; 323 }; 324 325 /** 326 * struct pmc_info - Structure to keep pmc info 327 * @devid: device id of the pmc device 328 * @map: pointer to a pmc_reg_map struct that contains platform 329 * specific attributes 330 */ 331 struct pmc_info { 332 u16 devid; 333 const struct pmc_reg_map *map; 334 }; 335 336 /** 337 * struct pmc - pmc private info structure 338 * @base_addr: contains pmc base address 339 * @regbase: pointer to io-remapped memory location 340 * @map: pointer to pmc_reg_map struct that contains platform 341 * specific attributes 342 * @lpm_req_regs: List of substate requirements 343 * 344 * pmc contains info about one power management controller device. 345 */ 346 struct pmc { 347 u64 base_addr; 348 void __iomem *regbase; 349 const struct pmc_reg_map *map; 350 u32 *lpm_req_regs; 351 }; 352 353 /** 354 * struct pmc_dev - pmc device structure 355 * @devs: pointer to an array of pmc pointers 356 * @pdev: pointer to platform_device struct 357 * @ssram_pcidev: pointer to pci device struct for the PMC SSRAM 358 * @dbgfs_dir: path to debugfs interface 359 * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers 360 * used to read MPHY PG and PLL status are available 361 * @mutex_lock: mutex to complete one transcation 362 * @pc10_counter: PC10 residency counter 363 * @s0ix_counter: S0ix residency (step adjusted) 364 * @num_lpm_modes: Count of enabled modes 365 * @lpm_en_modes: Array of enabled modes from lowest to highest priority 366 * @resume: Function to perform platform specific resume 367 * 368 * pmc_dev contains info about power management controller device. 369 */ 370 struct pmc_dev { 371 struct pmc *pmcs[MAX_NUM_PMC]; 372 struct dentry *dbgfs_dir; 373 struct platform_device *pdev; 374 struct pci_dev *ssram_pcidev; 375 int pmc_xram_read_bit; 376 struct mutex lock; /* generic mutex lock for PMC Core */ 377 378 u64 pc10_counter; 379 u64 s0ix_counter; 380 int num_lpm_modes; 381 int lpm_en_modes[LPM_MAX_NUM_MODES]; 382 int (*resume)(struct pmc_dev *pmcdev); 383 384 bool has_die_c6; 385 u32 die_c6_offset; 386 struct telem_endpoint *punit_ep; 387 struct pmc_info *regmap_list; 388 }; 389 390 enum pmc_index { 391 PMC_IDX_MAIN, 392 PMC_IDX_SOC = PMC_IDX_MAIN, 393 PMC_IDX_IOE, 394 PMC_IDX_PCH, 395 PMC_IDX_MAX 396 }; 397 398 extern const struct pmc_bit_map msr_map[]; 399 extern const struct pmc_bit_map spt_pll_map[]; 400 extern const struct pmc_bit_map spt_mphy_map[]; 401 extern const struct pmc_bit_map spt_pfear_map[]; 402 extern const struct pmc_bit_map *ext_spt_pfear_map[]; 403 extern const struct pmc_bit_map spt_ltr_show_map[]; 404 extern const struct pmc_reg_map spt_reg_map; 405 extern const struct pmc_bit_map cnp_pfear_map[]; 406 extern const struct pmc_bit_map *ext_cnp_pfear_map[]; 407 extern const struct pmc_bit_map cnp_slps0_dbg0_map[]; 408 extern const struct pmc_bit_map cnp_slps0_dbg1_map[]; 409 extern const struct pmc_bit_map cnp_slps0_dbg2_map[]; 410 extern const struct pmc_bit_map *cnp_slps0_dbg_maps[]; 411 extern const struct pmc_bit_map cnp_ltr_show_map[]; 412 extern const struct pmc_reg_map cnp_reg_map; 413 extern const struct pmc_bit_map icl_pfear_map[]; 414 extern const struct pmc_bit_map *ext_icl_pfear_map[]; 415 extern const struct pmc_reg_map icl_reg_map; 416 extern const struct pmc_bit_map tgl_pfear_map[]; 417 extern const struct pmc_bit_map *ext_tgl_pfear_map[]; 418 extern const struct pmc_bit_map tgl_clocksource_status_map[]; 419 extern const struct pmc_bit_map tgl_power_gating_status_map[]; 420 extern const struct pmc_bit_map tgl_d3_status_map[]; 421 extern const struct pmc_bit_map tgl_vnn_req_status_map[]; 422 extern const struct pmc_bit_map tgl_vnn_misc_status_map[]; 423 extern const struct pmc_bit_map tgl_signal_status_map[]; 424 extern const struct pmc_bit_map *tgl_lpm_maps[]; 425 extern const struct pmc_reg_map tgl_reg_map; 426 extern const struct pmc_bit_map adl_pfear_map[]; 427 extern const struct pmc_bit_map *ext_adl_pfear_map[]; 428 extern const struct pmc_bit_map adl_ltr_show_map[]; 429 extern const struct pmc_bit_map adl_clocksource_status_map[]; 430 extern const struct pmc_bit_map adl_power_gating_status_0_map[]; 431 extern const struct pmc_bit_map adl_power_gating_status_1_map[]; 432 extern const struct pmc_bit_map adl_power_gating_status_2_map[]; 433 extern const struct pmc_bit_map adl_d3_status_0_map[]; 434 extern const struct pmc_bit_map adl_d3_status_1_map[]; 435 extern const struct pmc_bit_map adl_d3_status_2_map[]; 436 extern const struct pmc_bit_map adl_d3_status_3_map[]; 437 extern const struct pmc_bit_map adl_vnn_req_status_0_map[]; 438 extern const struct pmc_bit_map adl_vnn_req_status_1_map[]; 439 extern const struct pmc_bit_map adl_vnn_req_status_2_map[]; 440 extern const struct pmc_bit_map adl_vnn_req_status_3_map[]; 441 extern const struct pmc_bit_map adl_vnn_misc_status_map[]; 442 extern const struct pmc_bit_map *adl_lpm_maps[]; 443 extern const struct pmc_reg_map adl_reg_map; 444 extern const struct pmc_bit_map mtl_socm_pfear_map[]; 445 extern const struct pmc_bit_map *ext_mtl_socm_pfear_map[]; 446 extern const struct pmc_bit_map mtl_socm_ltr_show_map[]; 447 extern const struct pmc_bit_map mtl_socm_clocksource_status_map[]; 448 extern const struct pmc_bit_map mtl_socm_power_gating_status_0_map[]; 449 extern const struct pmc_bit_map mtl_socm_power_gating_status_1_map[]; 450 extern const struct pmc_bit_map mtl_socm_power_gating_status_2_map[]; 451 extern const struct pmc_bit_map mtl_socm_d3_status_0_map[]; 452 extern const struct pmc_bit_map mtl_socm_d3_status_1_map[]; 453 extern const struct pmc_bit_map mtl_socm_d3_status_2_map[]; 454 extern const struct pmc_bit_map mtl_socm_d3_status_3_map[]; 455 extern const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[]; 456 extern const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[]; 457 extern const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[]; 458 extern const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[]; 459 extern const struct pmc_bit_map mtl_socm_vnn_misc_status_map[]; 460 extern const struct pmc_bit_map mtl_socm_signal_status_map[]; 461 extern const struct pmc_bit_map *mtl_socm_lpm_maps[]; 462 extern const struct pmc_reg_map mtl_socm_reg_map; 463 extern const struct pmc_bit_map mtl_ioep_pfear_map[]; 464 extern const struct pmc_bit_map *ext_mtl_ioep_pfear_map[]; 465 extern const struct pmc_bit_map mtl_ioep_ltr_show_map[]; 466 extern const struct pmc_bit_map mtl_ioep_clocksource_status_map[]; 467 extern const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[]; 468 extern const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[]; 469 extern const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[]; 470 extern const struct pmc_bit_map mtl_ioep_d3_status_0_map[]; 471 extern const struct pmc_bit_map mtl_ioep_d3_status_1_map[]; 472 extern const struct pmc_bit_map mtl_ioep_d3_status_2_map[]; 473 extern const struct pmc_bit_map mtl_ioep_d3_status_3_map[]; 474 extern const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[]; 475 extern const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[]; 476 extern const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[]; 477 extern const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[]; 478 extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[]; 479 extern const struct pmc_bit_map *mtl_ioep_lpm_maps[]; 480 extern const struct pmc_reg_map mtl_ioep_reg_map; 481 extern const struct pmc_bit_map mtl_ioem_pfear_map[]; 482 extern const struct pmc_bit_map *ext_mtl_ioem_pfear_map[]; 483 extern const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[]; 484 extern const struct pmc_bit_map mtl_ioem_vnn_req_status_1_map[]; 485 extern const struct pmc_bit_map *mtl_ioem_lpm_maps[]; 486 extern const struct pmc_reg_map mtl_ioem_reg_map; 487 488 extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev); 489 extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value); 490 491 int pmc_core_resume_common(struct pmc_dev *pmcdev); 492 int get_primary_reg_base(struct pmc *pmc); 493 494 extern void pmc_core_ssram_init(struct pmc_dev *pmcdev); 495 496 int spt_core_init(struct pmc_dev *pmcdev); 497 int cnp_core_init(struct pmc_dev *pmcdev); 498 int icl_core_init(struct pmc_dev *pmcdev); 499 int tgl_core_init(struct pmc_dev *pmcdev); 500 int adl_core_init(struct pmc_dev *pmcdev); 501 int mtl_core_init(struct pmc_dev *pmcdev); 502 503 #define pmc_for_each_mode(i, mode, pmcdev) \ 504 for (i = 0, mode = pmcdev->lpm_en_modes[i]; \ 505 i < pmcdev->num_lpm_modes; \ 506 i++, mode = pmcdev->lpm_en_modes[i]) 507 508 #define DEFINE_PMC_CORE_ATTR_WRITE(__name) \ 509 static int __name ## _open(struct inode *inode, struct file *file) \ 510 { \ 511 return single_open(file, __name ## _show, inode->i_private); \ 512 } \ 513 \ 514 static const struct file_operations __name ## _fops = { \ 515 .owner = THIS_MODULE, \ 516 .open = __name ## _open, \ 517 .read = seq_read, \ 518 .write = __name ## _write, \ 519 .release = single_release, \ 520 } 521 522 #endif /* PMC_CORE_H */ 523