1*08876884SGayatri Kammela // SPDX-License-Identifier: GPL-2.0 2*08876884SGayatri Kammela /* 3*08876884SGayatri Kammela * This file contains platform specific structure definitions 4*08876884SGayatri Kammela * and init function used by Alder Lake PCH. 5*08876884SGayatri Kammela * 6*08876884SGayatri Kammela * Copyright (c) 2022, Intel Corporation. 7*08876884SGayatri Kammela * All Rights Reserved. 8*08876884SGayatri Kammela * 9*08876884SGayatri Kammela */ 10*08876884SGayatri Kammela 11*08876884SGayatri Kammela #include "core.h" 12*08876884SGayatri Kammela 13*08876884SGayatri Kammela /* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */ 14*08876884SGayatri Kammela const struct pmc_bit_map adl_pfear_map[] = { 15*08876884SGayatri Kammela {"SPI/eSPI", BIT(2)}, 16*08876884SGayatri Kammela {"XHCI", BIT(3)}, 17*08876884SGayatri Kammela {"SPA", BIT(4)}, 18*08876884SGayatri Kammela {"SPB", BIT(5)}, 19*08876884SGayatri Kammela {"SPC", BIT(6)}, 20*08876884SGayatri Kammela {"GBE", BIT(7)}, 21*08876884SGayatri Kammela 22*08876884SGayatri Kammela {"SATA", BIT(0)}, 23*08876884SGayatri Kammela {"HDA_PGD0", BIT(1)}, 24*08876884SGayatri Kammela {"HDA_PGD1", BIT(2)}, 25*08876884SGayatri Kammela {"HDA_PGD2", BIT(3)}, 26*08876884SGayatri Kammela {"HDA_PGD3", BIT(4)}, 27*08876884SGayatri Kammela {"SPD", BIT(5)}, 28*08876884SGayatri Kammela {"LPSS", BIT(6)}, 29*08876884SGayatri Kammela 30*08876884SGayatri Kammela {"SMB", BIT(0)}, 31*08876884SGayatri Kammela {"ISH", BIT(1)}, 32*08876884SGayatri Kammela {"ITH", BIT(3)}, 33*08876884SGayatri Kammela 34*08876884SGayatri Kammela {"XDCI", BIT(1)}, 35*08876884SGayatri Kammela {"DCI", BIT(2)}, 36*08876884SGayatri Kammela {"CSE", BIT(3)}, 37*08876884SGayatri Kammela {"CSME_KVM", BIT(4)}, 38*08876884SGayatri Kammela {"CSME_PMT", BIT(5)}, 39*08876884SGayatri Kammela {"CSME_CLINK", BIT(6)}, 40*08876884SGayatri Kammela {"CSME_PTIO", BIT(7)}, 41*08876884SGayatri Kammela 42*08876884SGayatri Kammela {"CSME_USBR", BIT(0)}, 43*08876884SGayatri Kammela {"CSME_SUSRAM", BIT(1)}, 44*08876884SGayatri Kammela {"CSME_SMT1", BIT(2)}, 45*08876884SGayatri Kammela {"CSME_SMS2", BIT(4)}, 46*08876884SGayatri Kammela {"CSME_SMS1", BIT(5)}, 47*08876884SGayatri Kammela {"CSME_RTC", BIT(6)}, 48*08876884SGayatri Kammela {"CSME_PSF", BIT(7)}, 49*08876884SGayatri Kammela 50*08876884SGayatri Kammela {"CNVI", BIT(3)}, 51*08876884SGayatri Kammela {"HDA_PGD4", BIT(2)}, 52*08876884SGayatri Kammela {"HDA_PGD5", BIT(3)}, 53*08876884SGayatri Kammela {"HDA_PGD6", BIT(4)}, 54*08876884SGayatri Kammela {} 55*08876884SGayatri Kammela }; 56*08876884SGayatri Kammela 57*08876884SGayatri Kammela const struct pmc_bit_map *ext_adl_pfear_map[] = { 58*08876884SGayatri Kammela /* 59*08876884SGayatri Kammela * Check intel_pmc_core_ids[] users of cnp_reg_map for 60*08876884SGayatri Kammela * a list of core SoCs using this. 61*08876884SGayatri Kammela */ 62*08876884SGayatri Kammela adl_pfear_map, 63*08876884SGayatri Kammela NULL 64*08876884SGayatri Kammela }; 65*08876884SGayatri Kammela 66*08876884SGayatri Kammela const struct pmc_bit_map adl_ltr_show_map[] = { 67*08876884SGayatri Kammela {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 68*08876884SGayatri Kammela {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 69*08876884SGayatri Kammela {"SATA", CNP_PMC_LTR_SATA}, 70*08876884SGayatri Kammela {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 71*08876884SGayatri Kammela {"XHCI", CNP_PMC_LTR_XHCI}, 72*08876884SGayatri Kammela {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 73*08876884SGayatri Kammela {"ME", CNP_PMC_LTR_ME}, 74*08876884SGayatri Kammela /* EVA is Enterprise Value Add, doesn't really exist on PCH */ 75*08876884SGayatri Kammela {"SATA1", CNP_PMC_LTR_EVA}, 76*08876884SGayatri Kammela {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 77*08876884SGayatri Kammela {"HD_AUDIO", CNP_PMC_LTR_AZ}, 78*08876884SGayatri Kammela {"CNV", CNP_PMC_LTR_CNV}, 79*08876884SGayatri Kammela {"LPSS", CNP_PMC_LTR_LPSS}, 80*08876884SGayatri Kammela {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 81*08876884SGayatri Kammela {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 82*08876884SGayatri Kammela {"SATA2", CNP_PMC_LTR_CAM}, 83*08876884SGayatri Kammela {"ESPI", CNP_PMC_LTR_ESPI}, 84*08876884SGayatri Kammela {"SCC", CNP_PMC_LTR_SCC}, 85*08876884SGayatri Kammela {"ISH", CNP_PMC_LTR_ISH}, 86*08876884SGayatri Kammela {"UFSX2", CNP_PMC_LTR_UFSX2}, 87*08876884SGayatri Kammela {"EMMC", CNP_PMC_LTR_EMMC}, 88*08876884SGayatri Kammela /* 89*08876884SGayatri Kammela * Check intel_pmc_core_ids[] users of cnp_reg_map for 90*08876884SGayatri Kammela * a list of core SoCs using this. 91*08876884SGayatri Kammela */ 92*08876884SGayatri Kammela {"WIGIG", ICL_PMC_LTR_WIGIG}, 93*08876884SGayatri Kammela {"THC0", TGL_PMC_LTR_THC0}, 94*08876884SGayatri Kammela {"THC1", TGL_PMC_LTR_THC1}, 95*08876884SGayatri Kammela {"SOUTHPORT_G", CNP_PMC_LTR_RESERVED}, 96*08876884SGayatri Kammela 97*08876884SGayatri Kammela /* Below two cannot be used for LTR_IGNORE */ 98*08876884SGayatri Kammela {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, 99*08876884SGayatri Kammela {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, 100*08876884SGayatri Kammela {} 101*08876884SGayatri Kammela }; 102*08876884SGayatri Kammela 103*08876884SGayatri Kammela const struct pmc_bit_map adl_clocksource_status_map[] = { 104*08876884SGayatri Kammela {"CLKPART1_OFF_STS", BIT(0)}, 105*08876884SGayatri Kammela {"CLKPART2_OFF_STS", BIT(1)}, 106*08876884SGayatri Kammela {"CLKPART3_OFF_STS", BIT(2)}, 107*08876884SGayatri Kammela {"CLKPART4_OFF_STS", BIT(3)}, 108*08876884SGayatri Kammela {"CLKPART5_OFF_STS", BIT(4)}, 109*08876884SGayatri Kammela {"CLKPART6_OFF_STS", BIT(5)}, 110*08876884SGayatri Kammela {"CLKPART7_OFF_STS", BIT(6)}, 111*08876884SGayatri Kammela {"CLKPART8_OFF_STS", BIT(7)}, 112*08876884SGayatri Kammela {"PCIE0PLL_OFF_STS", BIT(10)}, 113*08876884SGayatri Kammela {"PCIE1PLL_OFF_STS", BIT(11)}, 114*08876884SGayatri Kammela {"PCIE2PLL_OFF_STS", BIT(12)}, 115*08876884SGayatri Kammela {"PCIE3PLL_OFF_STS", BIT(13)}, 116*08876884SGayatri Kammela {"PCIE4PLL_OFF_STS", BIT(14)}, 117*08876884SGayatri Kammela {"PCIE5PLL_OFF_STS", BIT(15)}, 118*08876884SGayatri Kammela {"PCIE6PLL_OFF_STS", BIT(16)}, 119*08876884SGayatri Kammela {"USB2PLL_OFF_STS", BIT(18)}, 120*08876884SGayatri Kammela {"OCPLL_OFF_STS", BIT(22)}, 121*08876884SGayatri Kammela {"AUDIOPLL_OFF_STS", BIT(23)}, 122*08876884SGayatri Kammela {"GBEPLL_OFF_STS", BIT(24)}, 123*08876884SGayatri Kammela {"Fast_XTAL_Osc_OFF_STS", BIT(25)}, 124*08876884SGayatri Kammela {"AC_Ring_Osc_OFF_STS", BIT(26)}, 125*08876884SGayatri Kammela {"MC_Ring_Osc_OFF_STS", BIT(27)}, 126*08876884SGayatri Kammela {"SATAPLL_OFF_STS", BIT(29)}, 127*08876884SGayatri Kammela {"USB3PLL_OFF_STS", BIT(31)}, 128*08876884SGayatri Kammela {} 129*08876884SGayatri Kammela }; 130*08876884SGayatri Kammela 131*08876884SGayatri Kammela const struct pmc_bit_map adl_power_gating_status_0_map[] = { 132*08876884SGayatri Kammela {"PMC_PGD0_PG_STS", BIT(0)}, 133*08876884SGayatri Kammela {"DMI_PGD0_PG_STS", BIT(1)}, 134*08876884SGayatri Kammela {"ESPISPI_PGD0_PG_STS", BIT(2)}, 135*08876884SGayatri Kammela {"XHCI_PGD0_PG_STS", BIT(3)}, 136*08876884SGayatri Kammela {"SPA_PGD0_PG_STS", BIT(4)}, 137*08876884SGayatri Kammela {"SPB_PGD0_PG_STS", BIT(5)}, 138*08876884SGayatri Kammela {"SPC_PGD0_PG_STS", BIT(6)}, 139*08876884SGayatri Kammela {"GBE_PGD0_PG_STS", BIT(7)}, 140*08876884SGayatri Kammela {"SATA_PGD0_PG_STS", BIT(8)}, 141*08876884SGayatri Kammela {"DSP_PGD0_PG_STS", BIT(9)}, 142*08876884SGayatri Kammela {"DSP_PGD1_PG_STS", BIT(10)}, 143*08876884SGayatri Kammela {"DSP_PGD2_PG_STS", BIT(11)}, 144*08876884SGayatri Kammela {"DSP_PGD3_PG_STS", BIT(12)}, 145*08876884SGayatri Kammela {"SPD_PGD0_PG_STS", BIT(13)}, 146*08876884SGayatri Kammela {"LPSS_PGD0_PG_STS", BIT(14)}, 147*08876884SGayatri Kammela {"SMB_PGD0_PG_STS", BIT(16)}, 148*08876884SGayatri Kammela {"ISH_PGD0_PG_STS", BIT(17)}, 149*08876884SGayatri Kammela {"NPK_PGD0_PG_STS", BIT(19)}, 150*08876884SGayatri Kammela {"PECI_PGD0_PG_STS", BIT(21)}, 151*08876884SGayatri Kammela {"XDCI_PGD0_PG_STS", BIT(25)}, 152*08876884SGayatri Kammela {"EXI_PGD0_PG_STS", BIT(26)}, 153*08876884SGayatri Kammela {"CSE_PGD0_PG_STS", BIT(27)}, 154*08876884SGayatri Kammela {"KVMCC_PGD0_PG_STS", BIT(28)}, 155*08876884SGayatri Kammela {"PMT_PGD0_PG_STS", BIT(29)}, 156*08876884SGayatri Kammela {"CLINK_PGD0_PG_STS", BIT(30)}, 157*08876884SGayatri Kammela {"PTIO_PGD0_PG_STS", BIT(31)}, 158*08876884SGayatri Kammela {} 159*08876884SGayatri Kammela }; 160*08876884SGayatri Kammela 161*08876884SGayatri Kammela const struct pmc_bit_map adl_power_gating_status_1_map[] = { 162*08876884SGayatri Kammela {"USBR0_PGD0_PG_STS", BIT(0)}, 163*08876884SGayatri Kammela {"SMT1_PGD0_PG_STS", BIT(2)}, 164*08876884SGayatri Kammela {"CSMERTC_PGD0_PG_STS", BIT(6)}, 165*08876884SGayatri Kammela {"CSMEPSF_PGD0_PG_STS", BIT(7)}, 166*08876884SGayatri Kammela {"CNVI_PGD0_PG_STS", BIT(19)}, 167*08876884SGayatri Kammela {"DSP_PGD4_PG_STS", BIT(26)}, 168*08876884SGayatri Kammela {"SPG_PGD0_PG_STS", BIT(27)}, 169*08876884SGayatri Kammela {"SPE_PGD0_PG_STS", BIT(28)}, 170*08876884SGayatri Kammela {} 171*08876884SGayatri Kammela }; 172*08876884SGayatri Kammela 173*08876884SGayatri Kammela const struct pmc_bit_map adl_power_gating_status_2_map[] = { 174*08876884SGayatri Kammela {"THC0_PGD0_PG_STS", BIT(7)}, 175*08876884SGayatri Kammela {"THC1_PGD0_PG_STS", BIT(8)}, 176*08876884SGayatri Kammela {"SPF_PGD0_PG_STS", BIT(14)}, 177*08876884SGayatri Kammela {} 178*08876884SGayatri Kammela }; 179*08876884SGayatri Kammela 180*08876884SGayatri Kammela const struct pmc_bit_map adl_d3_status_0_map[] = { 181*08876884SGayatri Kammela {"ISH_D3_STS", BIT(2)}, 182*08876884SGayatri Kammela {"LPSS_D3_STS", BIT(3)}, 183*08876884SGayatri Kammela {"XDCI_D3_STS", BIT(4)}, 184*08876884SGayatri Kammela {"XHCI_D3_STS", BIT(5)}, 185*08876884SGayatri Kammela {"SPA_D3_STS", BIT(12)}, 186*08876884SGayatri Kammela {"SPB_D3_STS", BIT(13)}, 187*08876884SGayatri Kammela {"SPC_D3_STS", BIT(14)}, 188*08876884SGayatri Kammela {"SPD_D3_STS", BIT(15)}, 189*08876884SGayatri Kammela {"SPE_D3_STS", BIT(16)}, 190*08876884SGayatri Kammela {"DSP_D3_STS", BIT(19)}, 191*08876884SGayatri Kammela {"SATA_D3_STS", BIT(20)}, 192*08876884SGayatri Kammela {"DMI_D3_STS", BIT(22)}, 193*08876884SGayatri Kammela {} 194*08876884SGayatri Kammela }; 195*08876884SGayatri Kammela 196*08876884SGayatri Kammela const struct pmc_bit_map adl_d3_status_1_map[] = { 197*08876884SGayatri Kammela {"GBE_D3_STS", BIT(19)}, 198*08876884SGayatri Kammela {"CNVI_D3_STS", BIT(27)}, 199*08876884SGayatri Kammela {} 200*08876884SGayatri Kammela }; 201*08876884SGayatri Kammela 202*08876884SGayatri Kammela const struct pmc_bit_map adl_d3_status_2_map[] = { 203*08876884SGayatri Kammela {"CSMERTC_D3_STS", BIT(1)}, 204*08876884SGayatri Kammela {"CSE_D3_STS", BIT(4)}, 205*08876884SGayatri Kammela {"KVMCC_D3_STS", BIT(5)}, 206*08876884SGayatri Kammela {"USBR0_D3_STS", BIT(6)}, 207*08876884SGayatri Kammela {"SMT1_D3_STS", BIT(8)}, 208*08876884SGayatri Kammela {"PTIO_D3_STS", BIT(16)}, 209*08876884SGayatri Kammela {"PMT_D3_STS", BIT(17)}, 210*08876884SGayatri Kammela {} 211*08876884SGayatri Kammela }; 212*08876884SGayatri Kammela 213*08876884SGayatri Kammela const struct pmc_bit_map adl_d3_status_3_map[] = { 214*08876884SGayatri Kammela {"THC0_D3_STS", BIT(14)}, 215*08876884SGayatri Kammela {"THC1_D3_STS", BIT(15)}, 216*08876884SGayatri Kammela {} 217*08876884SGayatri Kammela }; 218*08876884SGayatri Kammela 219*08876884SGayatri Kammela const struct pmc_bit_map adl_vnn_req_status_0_map[] = { 220*08876884SGayatri Kammela {"ISH_VNN_REQ_STS", BIT(2)}, 221*08876884SGayatri Kammela {"ESPISPI_VNN_REQ_STS", BIT(18)}, 222*08876884SGayatri Kammela {"DSP_VNN_REQ_STS", BIT(19)}, 223*08876884SGayatri Kammela {} 224*08876884SGayatri Kammela }; 225*08876884SGayatri Kammela 226*08876884SGayatri Kammela const struct pmc_bit_map adl_vnn_req_status_1_map[] = { 227*08876884SGayatri Kammela {"NPK_VNN_REQ_STS", BIT(4)}, 228*08876884SGayatri Kammela {"EXI_VNN_REQ_STS", BIT(9)}, 229*08876884SGayatri Kammela {"GBE_VNN_REQ_STS", BIT(19)}, 230*08876884SGayatri Kammela {"SMB_VNN_REQ_STS", BIT(25)}, 231*08876884SGayatri Kammela {"CNVI_VNN_REQ_STS", BIT(27)}, 232*08876884SGayatri Kammela {} 233*08876884SGayatri Kammela }; 234*08876884SGayatri Kammela 235*08876884SGayatri Kammela const struct pmc_bit_map adl_vnn_req_status_2_map[] = { 236*08876884SGayatri Kammela {"CSMERTC_VNN_REQ_STS", BIT(1)}, 237*08876884SGayatri Kammela {"CSE_VNN_REQ_STS", BIT(4)}, 238*08876884SGayatri Kammela {"SMT1_VNN_REQ_STS", BIT(8)}, 239*08876884SGayatri Kammela {"CLINK_VNN_REQ_STS", BIT(14)}, 240*08876884SGayatri Kammela {"GPIOCOM4_VNN_REQ_STS", BIT(20)}, 241*08876884SGayatri Kammela {"GPIOCOM3_VNN_REQ_STS", BIT(21)}, 242*08876884SGayatri Kammela {"GPIOCOM2_VNN_REQ_STS", BIT(22)}, 243*08876884SGayatri Kammela {"GPIOCOM1_VNN_REQ_STS", BIT(23)}, 244*08876884SGayatri Kammela {"GPIOCOM0_VNN_REQ_STS", BIT(24)}, 245*08876884SGayatri Kammela {} 246*08876884SGayatri Kammela }; 247*08876884SGayatri Kammela 248*08876884SGayatri Kammela const struct pmc_bit_map adl_vnn_req_status_3_map[] = { 249*08876884SGayatri Kammela {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, 250*08876884SGayatri Kammela {} 251*08876884SGayatri Kammela }; 252*08876884SGayatri Kammela 253*08876884SGayatri Kammela const struct pmc_bit_map adl_vnn_misc_status_map[] = { 254*08876884SGayatri Kammela {"CPU_C10_REQ_STS", BIT(0)}, 255*08876884SGayatri Kammela {"PCIe_LPM_En_REQ_STS", BIT(3)}, 256*08876884SGayatri Kammela {"ITH_REQ_STS", BIT(5)}, 257*08876884SGayatri Kammela {"CNVI_REQ_STS", BIT(6)}, 258*08876884SGayatri Kammela {"ISH_REQ_STS", BIT(7)}, 259*08876884SGayatri Kammela {"USB2_SUS_PG_Sys_REQ_STS", BIT(10)}, 260*08876884SGayatri Kammela {"PCIe_Clk_REQ_STS", BIT(12)}, 261*08876884SGayatri Kammela {"MPHY_Core_DL_REQ_STS", BIT(16)}, 262*08876884SGayatri Kammela {"Break-even_En_REQ_STS", BIT(17)}, 263*08876884SGayatri Kammela {"MPHY_SUS_REQ_STS", BIT(22)}, 264*08876884SGayatri Kammela {"xDCI_attached_REQ_STS", BIT(24)}, 265*08876884SGayatri Kammela {} 266*08876884SGayatri Kammela }; 267*08876884SGayatri Kammela 268*08876884SGayatri Kammela const struct pmc_bit_map *adl_lpm_maps[] = { 269*08876884SGayatri Kammela adl_clocksource_status_map, 270*08876884SGayatri Kammela adl_power_gating_status_0_map, 271*08876884SGayatri Kammela adl_power_gating_status_1_map, 272*08876884SGayatri Kammela adl_power_gating_status_2_map, 273*08876884SGayatri Kammela adl_d3_status_0_map, 274*08876884SGayatri Kammela adl_d3_status_1_map, 275*08876884SGayatri Kammela adl_d3_status_2_map, 276*08876884SGayatri Kammela adl_d3_status_3_map, 277*08876884SGayatri Kammela adl_vnn_req_status_0_map, 278*08876884SGayatri Kammela adl_vnn_req_status_1_map, 279*08876884SGayatri Kammela adl_vnn_req_status_2_map, 280*08876884SGayatri Kammela adl_vnn_req_status_3_map, 281*08876884SGayatri Kammela adl_vnn_misc_status_map, 282*08876884SGayatri Kammela tgl_signal_status_map, 283*08876884SGayatri Kammela NULL 284*08876884SGayatri Kammela }; 285*08876884SGayatri Kammela 286*08876884SGayatri Kammela const struct pmc_reg_map adl_reg_map = { 287*08876884SGayatri Kammela .pfear_sts = ext_adl_pfear_map, 288*08876884SGayatri Kammela .slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET, 289*08876884SGayatri Kammela .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 290*08876884SGayatri Kammela .ltr_show_sts = adl_ltr_show_map, 291*08876884SGayatri Kammela .msr_sts = msr_map, 292*08876884SGayatri Kammela .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 293*08876884SGayatri Kammela .regmap_length = CNP_PMC_MMIO_REG_LEN, 294*08876884SGayatri Kammela .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 295*08876884SGayatri Kammela .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES, 296*08876884SGayatri Kammela .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 297*08876884SGayatri Kammela .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 298*08876884SGayatri Kammela .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, 299*08876884SGayatri Kammela .lpm_num_modes = ADL_LPM_NUM_MODES, 300*08876884SGayatri Kammela .lpm_num_maps = ADL_LPM_NUM_MAPS, 301*08876884SGayatri Kammela .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 302*08876884SGayatri Kammela .etr3_offset = ETR3_OFFSET, 303*08876884SGayatri Kammela .lpm_sts_latch_en_offset = ADL_LPM_STATUS_LATCH_EN_OFFSET, 304*08876884SGayatri Kammela .lpm_priority_offset = ADL_LPM_PRI_OFFSET, 305*08876884SGayatri Kammela .lpm_en_offset = ADL_LPM_EN_OFFSET, 306*08876884SGayatri Kammela .lpm_residency_offset = ADL_LPM_RESIDENCY_OFFSET, 307*08876884SGayatri Kammela .lpm_sts = adl_lpm_maps, 308*08876884SGayatri Kammela .lpm_status_offset = ADL_LPM_STATUS_OFFSET, 309*08876884SGayatri Kammela .lpm_live_status_offset = ADL_LPM_LIVE_STATUS_OFFSET, 310*08876884SGayatri Kammela }; 311*08876884SGayatri Kammela 312*08876884SGayatri Kammela void adl_core_configure(struct pmc_dev *pmcdev) 313*08876884SGayatri Kammela { 314*08876884SGayatri Kammela /* Due to a hardware limitation, the GBE LTR blocks PC10 315*08876884SGayatri Kammela * when a cable is attached. Tell the PMC to ignore it. 316*08876884SGayatri Kammela */ 317*08876884SGayatri Kammela dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n"); 318*08876884SGayatri Kammela pmc_core_send_ltr_ignore(pmcdev, 3); 319*08876884SGayatri Kammela } 320*08876884SGayatri Kammela 321*08876884SGayatri Kammela void adl_core_init(struct pmc_dev *pmcdev) 322*08876884SGayatri Kammela { 323*08876884SGayatri Kammela pmcdev->map = &adl_reg_map; 324*08876884SGayatri Kammela pmcdev->core_configure = adl_core_configure; 325*08876884SGayatri Kammela } 326