1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * AMD Platform Management Framework Driver 4 * 5 * Copyright (c) 2022, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #ifndef PMF_H 12 #define PMF_H 13 14 #include <linux/acpi.h> 15 #include <linux/platform_profile.h> 16 17 /* APMF Functions */ 18 #define APMF_FUNC_VERIFY_INTERFACE 0 19 #define APMF_FUNC_GET_SYS_PARAMS 1 20 #define APMF_FUNC_SBIOS_REQUESTS 2 21 #define APMF_FUNC_SBIOS_HEARTBEAT 4 22 #define APMF_FUNC_AUTO_MODE 5 23 #define APMF_FUNC_SET_FAN_IDX 7 24 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 25 #define APMF_FUNC_DYN_SLIDER_AC 11 26 #define APMF_FUNC_DYN_SLIDER_DC 12 27 28 /* Message Definitions */ 29 #define SET_SPL 0x03 /* SPL: Sustained Power Limit */ 30 #define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */ 31 #define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */ 32 #define GET_SPL 0x0B 33 #define GET_SPPT 0x0D 34 #define GET_FPPT 0x0F 35 #define SET_DRAM_ADDR_HIGH 0x14 36 #define SET_DRAM_ADDR_LOW 0x15 37 #define SET_TRANSFER_TABLE 0x16 38 #define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */ 39 #define SET_STT_LIMIT_APU 0x19 40 #define SET_STT_LIMIT_HS2 0x1A 41 #define SET_SPPT_APU_ONLY 0x1D 42 #define GET_SPPT_APU_ONLY 0x1E 43 #define GET_STT_MIN_LIMIT 0x1F 44 #define GET_STT_LIMIT_APU 0x20 45 #define GET_STT_LIMIT_HS2 0x21 46 47 /* Fan Index for Auto Mode */ 48 #define FAN_INDEX_AUTO 0xFFFFFFFF 49 50 #define ARG_NONE 0 51 #define AVG_SAMPLE_SIZE 3 52 53 /* AMD PMF BIOS interfaces */ 54 struct apmf_verify_interface { 55 u16 size; 56 u16 version; 57 u32 notification_mask; 58 u32 supported_functions; 59 } __packed; 60 61 struct apmf_system_params { 62 u16 size; 63 u32 valid_mask; 64 u32 flags; 65 u8 command_code; 66 u32 heartbeat_int; 67 } __packed; 68 69 struct apmf_sbios_req { 70 u16 size; 71 u32 pending_req; 72 u8 rsd; 73 u8 cql_event; 74 u8 amt_event; 75 u32 fppt; 76 u32 sppt; 77 u32 fppt_apu_only; 78 u32 spl; 79 u32 stt_min_limit; 80 u8 skin_temp_apu; 81 u8 skin_temp_hs2; 82 } __packed; 83 84 struct apmf_fan_idx { 85 u16 size; 86 u8 fan_ctl_mode; 87 u32 fan_ctl_idx; 88 } __packed; 89 90 struct smu_pmf_metrics { 91 u16 gfxclk_freq; /* in MHz */ 92 u16 socclk_freq; /* in MHz */ 93 u16 vclk_freq; /* in MHz */ 94 u16 dclk_freq; /* in MHz */ 95 u16 memclk_freq; /* in MHz */ 96 u16 spare; 97 u16 gfx_activity; /* in Centi */ 98 u16 uvd_activity; /* in Centi */ 99 u16 voltage[2]; /* in mV */ 100 u16 currents[2]; /* in mA */ 101 u16 power[2];/* in mW */ 102 u16 core_freq[8]; /* in MHz */ 103 u16 core_power[8]; /* in mW */ 104 u16 core_temp[8]; /* in centi-Celsius */ 105 u16 l3_freq; /* in MHz */ 106 u16 l3_temp; /* in centi-Celsius */ 107 u16 gfx_temp; /* in centi-Celsius */ 108 u16 soc_temp; /* in centi-Celsius */ 109 u16 throttler_status; 110 u16 current_socketpower; /* in mW */ 111 u16 stapm_orig_limit; /* in W */ 112 u16 stapm_cur_limit; /* in W */ 113 u32 apu_power; /* in mW */ 114 u32 dgpu_power; /* in mW */ 115 u16 vdd_tdc_val; /* in mA */ 116 u16 soc_tdc_val; /* in mA */ 117 u16 vdd_edc_val; /* in mA */ 118 u16 soc_edcv_al; /* in mA */ 119 u16 infra_cpu_maxfreq; /* in MHz */ 120 u16 infra_gfx_maxfreq; /* in MHz */ 121 u16 skin_temp; /* in centi-Celsius */ 122 u16 device_state; 123 } __packed; 124 125 enum amd_stt_skin_temp { 126 STT_TEMP_APU, 127 STT_TEMP_HS2, 128 STT_TEMP_COUNT, 129 }; 130 131 enum amd_slider_op { 132 SLIDER_OP_GET, 133 SLIDER_OP_SET, 134 }; 135 136 enum power_source { 137 POWER_SOURCE_AC, 138 POWER_SOURCE_DC, 139 POWER_SOURCE_MAX, 140 }; 141 142 enum power_modes { 143 POWER_MODE_PERFORMANCE, 144 POWER_MODE_BALANCED_POWER, 145 POWER_MODE_POWER_SAVER, 146 POWER_MODE_MAX, 147 }; 148 149 struct amd_pmf_dev { 150 void __iomem *regbase; 151 void __iomem *smu_virt_addr; 152 void *buf; 153 u32 base_addr; 154 u32 cpu_id; 155 struct device *dev; 156 struct mutex lock; /* protects the PMF interface */ 157 u32 supported_func; 158 enum platform_profile_option current_profile; 159 struct platform_profile_handler pprof; 160 struct dentry *dbgfs_dir; 161 int hb_interval; /* SBIOS heartbeat interval */ 162 struct delayed_work heart_beat; 163 struct smu_pmf_metrics m_table; 164 struct delayed_work work_buffer; 165 ktime_t start_time; 166 int socket_power_history[AVG_SAMPLE_SIZE]; 167 int socket_power_history_idx; 168 bool amt_enabled; 169 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */ 170 bool cnqf_enabled; 171 bool cnqf_supported; 172 }; 173 174 struct apmf_sps_prop_granular { 175 u32 fppt; 176 u32 sppt; 177 u32 sppt_apu_only; 178 u32 spl; 179 u32 stt_min; 180 u8 stt_skin_temp[STT_TEMP_COUNT]; 181 u32 fan_id; 182 } __packed; 183 184 /* Static Slider */ 185 struct apmf_static_slider_granular_output { 186 u16 size; 187 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX]; 188 } __packed; 189 190 struct amd_pmf_static_slider_granular { 191 u16 size; 192 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; 193 }; 194 195 struct fan_table_control { 196 bool manual; 197 unsigned long fan_id; 198 }; 199 200 struct power_table_control { 201 u32 spl; 202 u32 sppt; 203 u32 fppt; 204 u32 sppt_apu_only; 205 u32 stt_min; 206 u32 stt_skin_temp[STT_TEMP_COUNT]; 207 u32 reserved[16]; 208 }; 209 210 /* Auto Mode Layer */ 211 enum auto_mode_transition_priority { 212 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */ 213 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 214 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 215 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */ 216 AUTO_TRANSITION_MAX, 217 }; 218 219 enum auto_mode_mode { 220 AUTO_QUIET, 221 AUTO_BALANCE, 222 AUTO_PERFORMANCE_ON_LAP, 223 AUTO_PERFORMANCE, 224 AUTO_MODE_MAX, 225 }; 226 227 struct auto_mode_trans_params { 228 u32 time_constant; /* minimum time required to switch to next mode */ 229 u32 power_delta; /* delta power to shift mode */ 230 u32 power_threshold; 231 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */ 232 u32 applied; 233 enum auto_mode_mode target_mode; 234 u32 shifting_up; 235 }; 236 237 struct auto_mode_mode_settings { 238 struct power_table_control power_control; 239 struct fan_table_control fan_control; 240 u32 power_floor; 241 }; 242 243 struct auto_mode_mode_config { 244 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX]; 245 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX]; 246 enum auto_mode_mode current_mode; 247 }; 248 249 struct apmf_auto_mode { 250 u16 size; 251 /* time constant */ 252 u32 balanced_to_perf; 253 u32 perf_to_balanced; 254 u32 quiet_to_balanced; 255 u32 balanced_to_quiet; 256 /* power floor */ 257 u32 pfloor_perf; 258 u32 pfloor_balanced; 259 u32 pfloor_quiet; 260 /* Power delta for mode change */ 261 u32 pd_balanced_to_perf; 262 u32 pd_perf_to_balanced; 263 u32 pd_quiet_to_balanced; 264 u32 pd_balanced_to_quiet; 265 /* skin temperature limits */ 266 u8 stt_apu_perf_on_lap; /* CQL ON */ 267 u8 stt_hs2_perf_on_lap; /* CQL ON */ 268 u8 stt_apu_perf; 269 u8 stt_hs2_perf; 270 u8 stt_apu_balanced; 271 u8 stt_hs2_balanced; 272 u8 stt_apu_quiet; 273 u8 stt_hs2_quiet; 274 u32 stt_min_limit_perf_on_lap; /* CQL ON */ 275 u32 stt_min_limit_perf; 276 u32 stt_min_limit_balanced; 277 u32 stt_min_limit_quiet; 278 /* SPL based */ 279 u32 fppt_perf_on_lap; /* CQL ON */ 280 u32 sppt_perf_on_lap; /* CQL ON */ 281 u32 spl_perf_on_lap; /* CQL ON */ 282 u32 sppt_apu_only_perf_on_lap; /* CQL ON */ 283 u32 fppt_perf; 284 u32 sppt_perf; 285 u32 spl_perf; 286 u32 sppt_apu_only_perf; 287 u32 fppt_balanced; 288 u32 sppt_balanced; 289 u32 spl_balanced; 290 u32 sppt_apu_only_balanced; 291 u32 fppt_quiet; 292 u32 sppt_quiet; 293 u32 spl_quiet; 294 u32 sppt_apu_only_quiet; 295 /* Fan ID */ 296 u32 fan_id_perf; 297 u32 fan_id_balanced; 298 u32 fan_id_quiet; 299 } __packed; 300 301 /* CnQF Layer */ 302 enum cnqf_trans_priority { 303 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */ 304 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */ 305 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 306 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 307 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */ 308 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */ 309 CNQF_TRANSITION_MAX, 310 }; 311 312 enum cnqf_mode { 313 CNQF_MODE_QUIET, 314 CNQF_MODE_BALANCE, 315 CNQF_MODE_PERFORMANCE, 316 CNQF_MODE_TURBO, 317 CNQF_MODE_MAX, 318 }; 319 320 enum apmf_cnqf_pos { 321 APMF_CNQF_TURBO, 322 APMF_CNQF_PERFORMANCE, 323 APMF_CNQF_BALANCE, 324 APMF_CNQF_QUIET, 325 APMF_CNQF_MAX, 326 }; 327 328 struct cnqf_mode_settings { 329 struct power_table_control power_control; 330 struct fan_table_control fan_control; 331 u32 power_floor; 332 }; 333 334 struct cnqf_tran_params { 335 u32 time_constant; /* minimum time required to switch to next mode */ 336 u32 power_threshold; 337 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */ 338 u32 total_power; 339 u32 count; 340 bool priority; 341 bool shifting_up; 342 enum cnqf_mode target_mode; 343 }; 344 345 struct cnqf_config { 346 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX]; 347 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX]; 348 struct power_table_control defaults; 349 enum cnqf_mode current_mode; 350 u32 power_src; 351 u32 avg_power; 352 }; 353 354 struct apmf_cnqf_power_set { 355 u32 pfloor; 356 u32 fppt; 357 u32 sppt; 358 u32 sppt_apu_only; 359 u32 spl; 360 u32 stt_min_limit; 361 u8 stt_skintemp[STT_TEMP_COUNT]; 362 u32 fan_id; 363 } __packed; 364 365 struct apmf_dyn_slider_output { 366 u16 size; 367 u16 flags; 368 u32 t_perf_to_turbo; 369 u32 t_balanced_to_perf; 370 u32 t_quiet_to_balanced; 371 u32 t_balanced_to_quiet; 372 u32 t_perf_to_balanced; 373 u32 t_turbo_to_perf; 374 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX]; 375 } __packed; 376 377 /* Core Layer */ 378 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); 379 void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); 380 int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index); 381 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); 382 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev); 383 int amd_pmf_get_power_source(void); 384 int apmf_install_handler(struct amd_pmf_dev *pmf_dev); 385 386 /* SPS Layer */ 387 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf); 388 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx, 389 struct amd_pmf_static_slider_granular *table); 390 int amd_pmf_init_sps(struct amd_pmf_dev *dev); 391 void amd_pmf_deinit_sps(struct amd_pmf_dev *dev); 392 int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev, 393 struct apmf_static_slider_granular_output *output); 394 395 396 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx); 397 398 /* Auto Mode Layer */ 399 int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data); 400 void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev); 401 void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev); 402 void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms); 403 int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req); 404 405 void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event); 406 int amd_pmf_reset_amt(struct amd_pmf_dev *dev); 407 void amd_pmf_handle_amt(struct amd_pmf_dev *dev); 408 409 /* CnQF Layer */ 410 int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 411 int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 412 int amd_pmf_init_cnqf(struct amd_pmf_dev *dev); 413 void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev); 414 int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); 415 extern const struct attribute_group cnqf_feature_attribute_group; 416 417 #endif /* PMF_H */ 418