1 // SPDX-License-Identifier: GPL-2.0 2 // LPC interface for ChromeOS Embedded Controller 3 // 4 // Copyright (C) 2012-2015 Google, Inc 5 // 6 // This driver uses the ChromeOS EC byte-level message-based protocol for 7 // communicating the keyboard state (which keys are pressed) from a keyboard EC 8 // to the AP over some bus (such as i2c, lpc, spi). The EC does debouncing, 9 // but everything else (including deghosting) is done here. The main 10 // motivation for this is to keep the EC firmware as simple as possible, since 11 // it cannot be easily upgraded and EC flash/IRAM space is relatively 12 // expensive. 13 14 #include <linux/acpi.h> 15 #include <linux/dmi.h> 16 #include <linux/delay.h> 17 #include <linux/io.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/platform_data/cros_ec_commands.h> 21 #include <linux/platform_data/cros_ec_proto.h> 22 #include <linux/platform_device.h> 23 #include <linux/printk.h> 24 #include <linux/suspend.h> 25 26 #include "cros_ec_lpc_mec.h" 27 28 #define DRV_NAME "cros_ec_lpcs" 29 #define ACPI_DRV_NAME "GOOG0004" 30 31 /* True if ACPI device is present */ 32 static bool cros_ec_lpc_acpi_device_found; 33 34 /** 35 * struct lpc_driver_ops - LPC driver operations 36 * @read: Copy length bytes from EC address offset into buffer dest. Returns 37 * the 8-bit checksum of all bytes read. 38 * @write: Copy length bytes from buffer msg into EC address offset. Returns 39 * the 8-bit checksum of all bytes written. 40 */ 41 struct lpc_driver_ops { 42 u8 (*read)(unsigned int offset, unsigned int length, u8 *dest); 43 u8 (*write)(unsigned int offset, unsigned int length, const u8 *msg); 44 }; 45 46 static struct lpc_driver_ops cros_ec_lpc_ops = { }; 47 48 /* 49 * A generic instance of the read function of struct lpc_driver_ops, used for 50 * the LPC EC. 51 */ 52 static u8 cros_ec_lpc_read_bytes(unsigned int offset, unsigned int length, 53 u8 *dest) 54 { 55 int sum = 0; 56 int i; 57 58 for (i = 0; i < length; ++i) { 59 dest[i] = inb(offset + i); 60 sum += dest[i]; 61 } 62 63 /* Return checksum of all bytes read */ 64 return sum; 65 } 66 67 /* 68 * A generic instance of the write function of struct lpc_driver_ops, used for 69 * the LPC EC. 70 */ 71 static u8 cros_ec_lpc_write_bytes(unsigned int offset, unsigned int length, 72 const u8 *msg) 73 { 74 int sum = 0; 75 int i; 76 77 for (i = 0; i < length; ++i) { 78 outb(msg[i], offset + i); 79 sum += msg[i]; 80 } 81 82 /* Return checksum of all bytes written */ 83 return sum; 84 } 85 86 /* 87 * An instance of the read function of struct lpc_driver_ops, used for the 88 * MEC variant of LPC EC. 89 */ 90 static u8 cros_ec_lpc_mec_read_bytes(unsigned int offset, unsigned int length, 91 u8 *dest) 92 { 93 int in_range = cros_ec_lpc_mec_in_range(offset, length); 94 95 if (in_range < 0) 96 return 0; 97 98 return in_range ? 99 cros_ec_lpc_io_bytes_mec(MEC_IO_READ, 100 offset - EC_HOST_CMD_REGION0, 101 length, dest) : 102 cros_ec_lpc_read_bytes(offset, length, dest); 103 } 104 105 /* 106 * An instance of the write function of struct lpc_driver_ops, used for the 107 * MEC variant of LPC EC. 108 */ 109 static u8 cros_ec_lpc_mec_write_bytes(unsigned int offset, unsigned int length, 110 const u8 *msg) 111 { 112 int in_range = cros_ec_lpc_mec_in_range(offset, length); 113 114 if (in_range < 0) 115 return 0; 116 117 return in_range ? 118 cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE, 119 offset - EC_HOST_CMD_REGION0, 120 length, (u8 *)msg) : 121 cros_ec_lpc_write_bytes(offset, length, msg); 122 } 123 124 static int ec_response_timed_out(void) 125 { 126 unsigned long one_second = jiffies + HZ; 127 u8 data; 128 129 usleep_range(200, 300); 130 do { 131 if (!(cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_CMD, 1, &data) & 132 EC_LPC_STATUS_BUSY_MASK)) 133 return 0; 134 usleep_range(100, 200); 135 } while (time_before(jiffies, one_second)); 136 137 return 1; 138 } 139 140 static int cros_ec_pkt_xfer_lpc(struct cros_ec_device *ec, 141 struct cros_ec_command *msg) 142 { 143 struct ec_host_response response; 144 u8 sum; 145 int ret = 0; 146 u8 *dout; 147 148 ret = cros_ec_prepare_tx(ec, msg); 149 150 /* Write buffer */ 151 cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PACKET, ret, ec->dout); 152 153 /* Here we go */ 154 sum = EC_COMMAND_PROTOCOL_3; 155 cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum); 156 157 if (ec_response_timed_out()) { 158 dev_warn(ec->dev, "EC responsed timed out\n"); 159 ret = -EIO; 160 goto done; 161 } 162 163 /* Check result */ 164 msg->result = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum); 165 ret = cros_ec_check_result(ec, msg); 166 if (ret) 167 goto done; 168 169 /* Read back response */ 170 dout = (u8 *)&response; 171 sum = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET, sizeof(response), 172 dout); 173 174 msg->result = response.result; 175 176 if (response.data_len > msg->insize) { 177 dev_err(ec->dev, 178 "packet too long (%d bytes, expected %d)", 179 response.data_len, msg->insize); 180 ret = -EMSGSIZE; 181 goto done; 182 } 183 184 /* Read response and process checksum */ 185 sum += cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET + 186 sizeof(response), response.data_len, 187 msg->data); 188 189 if (sum) { 190 dev_err(ec->dev, 191 "bad packet checksum %02x\n", 192 response.checksum); 193 ret = -EBADMSG; 194 goto done; 195 } 196 197 /* Return actual amount of data received */ 198 ret = response.data_len; 199 done: 200 return ret; 201 } 202 203 static int cros_ec_cmd_xfer_lpc(struct cros_ec_device *ec, 204 struct cros_ec_command *msg) 205 { 206 struct ec_lpc_host_args args; 207 u8 sum; 208 int ret = 0; 209 210 if (msg->outsize > EC_PROTO2_MAX_PARAM_SIZE || 211 msg->insize > EC_PROTO2_MAX_PARAM_SIZE) { 212 dev_err(ec->dev, 213 "invalid buffer sizes (out %d, in %d)\n", 214 msg->outsize, msg->insize); 215 return -EINVAL; 216 } 217 218 /* Now actually send the command to the EC and get the result */ 219 args.flags = EC_HOST_ARGS_FLAG_FROM_HOST; 220 args.command_version = msg->version; 221 args.data_size = msg->outsize; 222 223 /* Initialize checksum */ 224 sum = msg->command + args.flags + args.command_version + args.data_size; 225 226 /* Copy data and update checksum */ 227 sum += cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PARAM, msg->outsize, 228 msg->data); 229 230 /* Finalize checksum and write args */ 231 args.checksum = sum; 232 cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_ARGS, sizeof(args), 233 (u8 *)&args); 234 235 /* Here we go */ 236 sum = msg->command; 237 cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum); 238 239 if (ec_response_timed_out()) { 240 dev_warn(ec->dev, "EC responsed timed out\n"); 241 ret = -EIO; 242 goto done; 243 } 244 245 /* Check result */ 246 msg->result = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum); 247 ret = cros_ec_check_result(ec, msg); 248 if (ret) 249 goto done; 250 251 /* Read back args */ 252 cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8 *)&args); 253 254 if (args.data_size > msg->insize) { 255 dev_err(ec->dev, 256 "packet too long (%d bytes, expected %d)", 257 args.data_size, msg->insize); 258 ret = -ENOSPC; 259 goto done; 260 } 261 262 /* Start calculating response checksum */ 263 sum = msg->command + args.flags + args.command_version + args.data_size; 264 265 /* Read response and update checksum */ 266 sum += cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PARAM, args.data_size, 267 msg->data); 268 269 /* Verify checksum */ 270 if (args.checksum != sum) { 271 dev_err(ec->dev, 272 "bad packet checksum, expected %02x, got %02x\n", 273 args.checksum, sum); 274 ret = -EBADMSG; 275 goto done; 276 } 277 278 /* Return actual amount of data received */ 279 ret = args.data_size; 280 done: 281 return ret; 282 } 283 284 /* Returns num bytes read, or negative on error. Doesn't need locking. */ 285 static int cros_ec_lpc_readmem(struct cros_ec_device *ec, unsigned int offset, 286 unsigned int bytes, void *dest) 287 { 288 int i = offset; 289 char *s = dest; 290 int cnt = 0; 291 292 if (offset >= EC_MEMMAP_SIZE - bytes) 293 return -EINVAL; 294 295 /* fixed length */ 296 if (bytes) { 297 cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + offset, bytes, s); 298 return bytes; 299 } 300 301 /* string */ 302 for (; i < EC_MEMMAP_SIZE; i++, s++) { 303 cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + i, 1, s); 304 cnt++; 305 if (!*s) 306 break; 307 } 308 309 return cnt; 310 } 311 312 static void cros_ec_lpc_acpi_notify(acpi_handle device, u32 value, void *data) 313 { 314 struct cros_ec_device *ec_dev = data; 315 316 if (ec_dev->mkbp_event_supported && 317 cros_ec_get_next_event(ec_dev, NULL) > 0) 318 blocking_notifier_call_chain(&ec_dev->event_notifier, 0, 319 ec_dev); 320 321 if (value == ACPI_NOTIFY_DEVICE_WAKE) 322 pm_system_wakeup(); 323 } 324 325 static int cros_ec_lpc_probe(struct platform_device *pdev) 326 { 327 struct device *dev = &pdev->dev; 328 struct acpi_device *adev; 329 acpi_status status; 330 struct cros_ec_device *ec_dev; 331 u8 buf[2]; 332 int irq, ret; 333 334 if (!devm_request_region(dev, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE, 335 dev_name(dev))) { 336 dev_err(dev, "couldn't reserve memmap region\n"); 337 return -EBUSY; 338 } 339 340 /* 341 * Read the mapped ID twice, the first one is assuming the 342 * EC is a Microchip Embedded Controller (MEC) variant, if the 343 * protocol fails, fallback to the non MEC variant and try to 344 * read again the ID. 345 */ 346 cros_ec_lpc_ops.read = cros_ec_lpc_mec_read_bytes; 347 cros_ec_lpc_ops.write = cros_ec_lpc_mec_write_bytes; 348 cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2, buf); 349 if (buf[0] != 'E' || buf[1] != 'C') { 350 /* Re-assign read/write operations for the non MEC variant */ 351 cros_ec_lpc_ops.read = cros_ec_lpc_read_bytes; 352 cros_ec_lpc_ops.write = cros_ec_lpc_write_bytes; 353 cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2, 354 buf); 355 if (buf[0] != 'E' || buf[1] != 'C') { 356 dev_err(dev, "EC ID not detected\n"); 357 return -ENODEV; 358 } 359 } 360 361 if (!devm_request_region(dev, EC_HOST_CMD_REGION0, 362 EC_HOST_CMD_REGION_SIZE, dev_name(dev))) { 363 dev_err(dev, "couldn't reserve region0\n"); 364 return -EBUSY; 365 } 366 if (!devm_request_region(dev, EC_HOST_CMD_REGION1, 367 EC_HOST_CMD_REGION_SIZE, dev_name(dev))) { 368 dev_err(dev, "couldn't reserve region1\n"); 369 return -EBUSY; 370 } 371 372 ec_dev = devm_kzalloc(dev, sizeof(*ec_dev), GFP_KERNEL); 373 if (!ec_dev) 374 return -ENOMEM; 375 376 platform_set_drvdata(pdev, ec_dev); 377 ec_dev->dev = dev; 378 ec_dev->phys_name = dev_name(dev); 379 ec_dev->cmd_xfer = cros_ec_cmd_xfer_lpc; 380 ec_dev->pkt_xfer = cros_ec_pkt_xfer_lpc; 381 ec_dev->cmd_readmem = cros_ec_lpc_readmem; 382 ec_dev->din_size = sizeof(struct ec_host_response) + 383 sizeof(struct ec_response_get_protocol_info); 384 ec_dev->dout_size = sizeof(struct ec_host_request); 385 386 /* 387 * Some boards do not have an IRQ allotted for cros_ec_lpc, 388 * which makes ENXIO an expected (and safe) scenario. 389 */ 390 irq = platform_get_irq(pdev, 0); 391 if (irq > 0) 392 ec_dev->irq = irq; 393 else if (irq != -ENXIO) { 394 dev_err(dev, "couldn't retrieve IRQ number (%d)\n", irq); 395 return irq; 396 } 397 398 ret = cros_ec_register(ec_dev); 399 if (ret) { 400 dev_err(dev, "couldn't register ec_dev (%d)\n", ret); 401 return ret; 402 } 403 404 /* 405 * Connect a notify handler to process MKBP messages if we have a 406 * companion ACPI device. 407 */ 408 adev = ACPI_COMPANION(dev); 409 if (adev) { 410 status = acpi_install_notify_handler(adev->handle, 411 ACPI_ALL_NOTIFY, 412 cros_ec_lpc_acpi_notify, 413 ec_dev); 414 if (ACPI_FAILURE(status)) 415 dev_warn(dev, "Failed to register notifier %08x\n", 416 status); 417 } 418 419 return 0; 420 } 421 422 static int cros_ec_lpc_remove(struct platform_device *pdev) 423 { 424 struct cros_ec_device *ec_dev = platform_get_drvdata(pdev); 425 struct acpi_device *adev; 426 427 adev = ACPI_COMPANION(&pdev->dev); 428 if (adev) 429 acpi_remove_notify_handler(adev->handle, ACPI_ALL_NOTIFY, 430 cros_ec_lpc_acpi_notify); 431 432 return cros_ec_unregister(ec_dev); 433 } 434 435 static const struct acpi_device_id cros_ec_lpc_acpi_device_ids[] = { 436 { ACPI_DRV_NAME, 0 }, 437 { } 438 }; 439 MODULE_DEVICE_TABLE(acpi, cros_ec_lpc_acpi_device_ids); 440 441 static const struct dmi_system_id cros_ec_lpc_dmi_table[] __initconst = { 442 { 443 /* 444 * Today all Chromebooks/boxes ship with Google_* as version and 445 * coreboot as bios vendor. No other systems with this 446 * combination are known to date. 447 */ 448 .matches = { 449 DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), 450 DMI_MATCH(DMI_BIOS_VERSION, "Google_"), 451 }, 452 }, 453 { 454 /* 455 * If the box is running custom coreboot firmware then the 456 * DMI BIOS version string will not be matched by "Google_", 457 * but the system vendor string will still be matched by 458 * "GOOGLE". 459 */ 460 .matches = { 461 DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), 462 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 463 }, 464 }, 465 { 466 /* x86-link, the Chromebook Pixel. */ 467 .matches = { 468 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 469 DMI_MATCH(DMI_PRODUCT_NAME, "Link"), 470 }, 471 }, 472 { 473 /* x86-samus, the Chromebook Pixel 2. */ 474 .matches = { 475 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 476 DMI_MATCH(DMI_PRODUCT_NAME, "Samus"), 477 }, 478 }, 479 { 480 /* x86-peppy, the Acer C720 Chromebook. */ 481 .matches = { 482 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 483 DMI_MATCH(DMI_PRODUCT_NAME, "Peppy"), 484 }, 485 }, 486 { 487 /* x86-glimmer, the Lenovo Thinkpad Yoga 11e. */ 488 .matches = { 489 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 490 DMI_MATCH(DMI_PRODUCT_NAME, "Glimmer"), 491 }, 492 }, 493 { /* sentinel */ } 494 }; 495 MODULE_DEVICE_TABLE(dmi, cros_ec_lpc_dmi_table); 496 497 #ifdef CONFIG_PM_SLEEP 498 static int cros_ec_lpc_suspend(struct device *dev) 499 { 500 struct cros_ec_device *ec_dev = dev_get_drvdata(dev); 501 502 return cros_ec_suspend(ec_dev); 503 } 504 505 static int cros_ec_lpc_resume(struct device *dev) 506 { 507 struct cros_ec_device *ec_dev = dev_get_drvdata(dev); 508 509 return cros_ec_resume(ec_dev); 510 } 511 #endif 512 513 static const struct dev_pm_ops cros_ec_lpc_pm_ops = { 514 SET_LATE_SYSTEM_SLEEP_PM_OPS(cros_ec_lpc_suspend, cros_ec_lpc_resume) 515 }; 516 517 static struct platform_driver cros_ec_lpc_driver = { 518 .driver = { 519 .name = DRV_NAME, 520 .acpi_match_table = cros_ec_lpc_acpi_device_ids, 521 .pm = &cros_ec_lpc_pm_ops, 522 }, 523 .probe = cros_ec_lpc_probe, 524 .remove = cros_ec_lpc_remove, 525 }; 526 527 static struct platform_device cros_ec_lpc_device = { 528 .name = DRV_NAME 529 }; 530 531 static acpi_status cros_ec_lpc_parse_device(acpi_handle handle, u32 level, 532 void *context, void **retval) 533 { 534 *(bool *)context = true; 535 return AE_CTRL_TERMINATE; 536 } 537 538 static int __init cros_ec_lpc_init(void) 539 { 540 int ret; 541 acpi_status status; 542 543 status = acpi_get_devices(ACPI_DRV_NAME, cros_ec_lpc_parse_device, 544 &cros_ec_lpc_acpi_device_found, NULL); 545 if (ACPI_FAILURE(status)) 546 pr_warn(DRV_NAME ": Looking for %s failed\n", ACPI_DRV_NAME); 547 548 if (!cros_ec_lpc_acpi_device_found && 549 !dmi_check_system(cros_ec_lpc_dmi_table)) { 550 pr_err(DRV_NAME ": unsupported system.\n"); 551 return -ENODEV; 552 } 553 554 cros_ec_lpc_mec_init(EC_HOST_CMD_REGION0, 555 EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE); 556 557 /* Register the driver */ 558 ret = platform_driver_register(&cros_ec_lpc_driver); 559 if (ret) { 560 pr_err(DRV_NAME ": can't register driver: %d\n", ret); 561 cros_ec_lpc_mec_destroy(); 562 return ret; 563 } 564 565 if (!cros_ec_lpc_acpi_device_found) { 566 /* Register the device, and it'll get hooked up automatically */ 567 ret = platform_device_register(&cros_ec_lpc_device); 568 if (ret) { 569 pr_err(DRV_NAME ": can't register device: %d\n", ret); 570 platform_driver_unregister(&cros_ec_lpc_driver); 571 cros_ec_lpc_mec_destroy(); 572 } 573 } 574 575 return ret; 576 } 577 578 static void __exit cros_ec_lpc_exit(void) 579 { 580 if (!cros_ec_lpc_acpi_device_found) 581 platform_device_unregister(&cros_ec_lpc_device); 582 platform_driver_unregister(&cros_ec_lpc_driver); 583 cros_ec_lpc_mec_destroy(); 584 } 585 586 module_init(cros_ec_lpc_init); 587 module_exit(cros_ec_lpc_exit); 588 589 MODULE_LICENSE("GPL"); 590 MODULE_DESCRIPTION("ChromeOS EC LPC driver"); 591