1 /* 2 * Copyright (C) 2015-2017 Socionext Inc. 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/list.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/of.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 26 #include "../core.h" 27 #include "../pinctrl-utils.h" 28 #include "pinctrl-uniphier.h" 29 30 #define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000 31 #define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700 32 #define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x1800 33 #define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x1900 34 #define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x1980 35 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00 36 #define UNIPHIER_PINCTRL_IECTRL_BASE 0x1d00 37 38 struct uniphier_pinctrl_reg_region { 39 struct list_head node; 40 unsigned int base; 41 unsigned int nregs; 42 u32 vals[0]; 43 }; 44 45 struct uniphier_pinctrl_priv { 46 struct pinctrl_desc pctldesc; 47 struct pinctrl_dev *pctldev; 48 struct regmap *regmap; 49 struct uniphier_pinctrl_socdata *socdata; 50 struct list_head reg_regions; 51 }; 52 53 static int uniphier_pctl_get_groups_count(struct pinctrl_dev *pctldev) 54 { 55 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 56 57 return priv->socdata->groups_count; 58 } 59 60 static const char *uniphier_pctl_get_group_name(struct pinctrl_dev *pctldev, 61 unsigned selector) 62 { 63 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 64 65 return priv->socdata->groups[selector].name; 66 } 67 68 static int uniphier_pctl_get_group_pins(struct pinctrl_dev *pctldev, 69 unsigned selector, 70 const unsigned **pins, 71 unsigned *num_pins) 72 { 73 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 74 75 *pins = priv->socdata->groups[selector].pins; 76 *num_pins = priv->socdata->groups[selector].num_pins; 77 78 return 0; 79 } 80 81 #ifdef CONFIG_DEBUG_FS 82 static void uniphier_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, 83 struct seq_file *s, unsigned offset) 84 { 85 const struct pin_desc *desc = pin_desc_get(pctldev, offset); 86 const char *pull_dir, *drv_type; 87 88 switch (uniphier_pin_get_pull_dir(desc->drv_data)) { 89 case UNIPHIER_PIN_PULL_UP: 90 pull_dir = "UP"; 91 break; 92 case UNIPHIER_PIN_PULL_DOWN: 93 pull_dir = "DOWN"; 94 break; 95 case UNIPHIER_PIN_PULL_UP_FIXED: 96 pull_dir = "UP(FIXED)"; 97 break; 98 case UNIPHIER_PIN_PULL_DOWN_FIXED: 99 pull_dir = "DOWN(FIXED)"; 100 break; 101 case UNIPHIER_PIN_PULL_NONE: 102 pull_dir = "NONE"; 103 break; 104 default: 105 BUG(); 106 } 107 108 switch (uniphier_pin_get_drv_type(desc->drv_data)) { 109 case UNIPHIER_PIN_DRV_1BIT: 110 drv_type = "4/8(mA)"; 111 break; 112 case UNIPHIER_PIN_DRV_2BIT: 113 drv_type = "8/12/16/20(mA)"; 114 break; 115 case UNIPHIER_PIN_DRV_3BIT: 116 drv_type = "4/5/7/9/11/12/14/16(mA)"; 117 break; 118 case UNIPHIER_PIN_DRV_FIXED4: 119 drv_type = "4(mA)"; 120 break; 121 case UNIPHIER_PIN_DRV_FIXED5: 122 drv_type = "5(mA)"; 123 break; 124 case UNIPHIER_PIN_DRV_FIXED8: 125 drv_type = "8(mA)"; 126 break; 127 case UNIPHIER_PIN_DRV_NONE: 128 drv_type = "NONE"; 129 break; 130 default: 131 BUG(); 132 } 133 134 seq_printf(s, " PULL_DIR=%s DRV_TYPE=%s", pull_dir, drv_type); 135 } 136 #endif 137 138 static const struct pinctrl_ops uniphier_pctlops = { 139 .get_groups_count = uniphier_pctl_get_groups_count, 140 .get_group_name = uniphier_pctl_get_group_name, 141 .get_group_pins = uniphier_pctl_get_group_pins, 142 #ifdef CONFIG_DEBUG_FS 143 .pin_dbg_show = uniphier_pctl_pin_dbg_show, 144 #endif 145 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 146 .dt_free_map = pinctrl_utils_free_map, 147 }; 148 149 static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev, 150 unsigned int pin, 151 enum pin_config_param param) 152 { 153 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 154 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 155 enum uniphier_pin_pull_dir pull_dir = 156 uniphier_pin_get_pull_dir(desc->drv_data); 157 unsigned int pupdctrl, reg, shift, val; 158 unsigned int expected = 1; 159 int ret; 160 161 switch (param) { 162 case PIN_CONFIG_BIAS_DISABLE: 163 if (pull_dir == UNIPHIER_PIN_PULL_NONE) 164 return 0; 165 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED || 166 pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED) 167 return -EINVAL; 168 expected = 0; 169 break; 170 case PIN_CONFIG_BIAS_PULL_UP: 171 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED) 172 return 0; 173 if (pull_dir != UNIPHIER_PIN_PULL_UP) 174 return -EINVAL; 175 break; 176 case PIN_CONFIG_BIAS_PULL_DOWN: 177 if (pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED) 178 return 0; 179 if (pull_dir != UNIPHIER_PIN_PULL_DOWN) 180 return -EINVAL; 181 break; 182 default: 183 BUG(); 184 } 185 186 pupdctrl = uniphier_pin_get_pupdctrl(desc->drv_data); 187 188 reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4; 189 shift = pupdctrl % 32; 190 191 ret = regmap_read(priv->regmap, reg, &val); 192 if (ret) 193 return ret; 194 195 val = (val >> shift) & 1; 196 197 return (val == expected) ? 0 : -EINVAL; 198 } 199 200 static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev, 201 unsigned int pin, u32 *strength) 202 { 203 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 204 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 205 enum uniphier_pin_drv_type type = 206 uniphier_pin_get_drv_type(desc->drv_data); 207 static const unsigned int strength_1bit[] = {4, 8}; 208 static const unsigned int strength_2bit[] = {8, 12, 16, 20}; 209 static const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 210 14, 16}; 211 const unsigned int *supported_strength; 212 unsigned int drvctrl, reg, shift, mask, width, val; 213 int ret; 214 215 switch (type) { 216 case UNIPHIER_PIN_DRV_1BIT: 217 supported_strength = strength_1bit; 218 reg = UNIPHIER_PINCTRL_DRVCTRL_BASE; 219 width = 1; 220 break; 221 case UNIPHIER_PIN_DRV_2BIT: 222 supported_strength = strength_2bit; 223 reg = UNIPHIER_PINCTRL_DRV2CTRL_BASE; 224 width = 2; 225 break; 226 case UNIPHIER_PIN_DRV_3BIT: 227 supported_strength = strength_3bit; 228 reg = UNIPHIER_PINCTRL_DRV3CTRL_BASE; 229 width = 4; 230 break; 231 case UNIPHIER_PIN_DRV_FIXED4: 232 *strength = 4; 233 return 0; 234 case UNIPHIER_PIN_DRV_FIXED5: 235 *strength = 5; 236 return 0; 237 case UNIPHIER_PIN_DRV_FIXED8: 238 *strength = 8; 239 return 0; 240 default: 241 /* drive strength control is not supported for this pin */ 242 return -EINVAL; 243 } 244 245 drvctrl = uniphier_pin_get_drvctrl(desc->drv_data); 246 drvctrl *= width; 247 248 reg += drvctrl / 32 * 4; 249 shift = drvctrl % 32; 250 mask = (1U << width) - 1; 251 252 ret = regmap_read(priv->regmap, reg, &val); 253 if (ret) 254 return ret; 255 256 *strength = supported_strength[(val >> shift) & mask]; 257 258 return 0; 259 } 260 261 static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev, 262 unsigned int pin) 263 { 264 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 265 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 266 unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data); 267 unsigned int reg, mask, val; 268 int ret; 269 270 if (iectrl == UNIPHIER_PIN_IECTRL_NONE) 271 /* This pin is always input-enabled. */ 272 return 0; 273 274 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) 275 iectrl = pin; 276 277 reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4; 278 mask = BIT(iectrl % 32); 279 280 ret = regmap_read(priv->regmap, reg, &val); 281 if (ret) 282 return ret; 283 284 return val & mask ? 0 : -EINVAL; 285 } 286 287 static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev, 288 unsigned pin, 289 unsigned long *configs) 290 { 291 enum pin_config_param param = pinconf_to_config_param(*configs); 292 bool has_arg = false; 293 u32 arg; 294 int ret; 295 296 switch (param) { 297 case PIN_CONFIG_BIAS_DISABLE: 298 case PIN_CONFIG_BIAS_PULL_UP: 299 case PIN_CONFIG_BIAS_PULL_DOWN: 300 ret = uniphier_conf_pin_bias_get(pctldev, pin, param); 301 break; 302 case PIN_CONFIG_DRIVE_STRENGTH: 303 ret = uniphier_conf_pin_drive_get(pctldev, pin, &arg); 304 has_arg = true; 305 break; 306 case PIN_CONFIG_INPUT_ENABLE: 307 ret = uniphier_conf_pin_input_enable_get(pctldev, pin); 308 break; 309 default: 310 /* unsupported parameter */ 311 ret = -EINVAL; 312 break; 313 } 314 315 if (ret == 0 && has_arg) 316 *configs = pinconf_to_config_packed(param, arg); 317 318 return ret; 319 } 320 321 static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev, 322 unsigned int pin, 323 enum pin_config_param param, u32 arg) 324 { 325 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 326 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 327 enum uniphier_pin_pull_dir pull_dir = 328 uniphier_pin_get_pull_dir(desc->drv_data); 329 unsigned int pupdctrl, reg, shift; 330 unsigned int val = 1; 331 332 switch (param) { 333 case PIN_CONFIG_BIAS_DISABLE: 334 if (pull_dir == UNIPHIER_PIN_PULL_NONE) 335 return 0; 336 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED || 337 pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED) { 338 dev_err(pctldev->dev, 339 "can not disable pull register for pin %s\n", 340 desc->name); 341 return -EINVAL; 342 } 343 val = 0; 344 break; 345 case PIN_CONFIG_BIAS_PULL_UP: 346 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED && arg != 0) 347 return 0; 348 if (pull_dir != UNIPHIER_PIN_PULL_UP) { 349 dev_err(pctldev->dev, 350 "pull-up is unsupported for pin %s\n", 351 desc->name); 352 return -EINVAL; 353 } 354 if (arg == 0) { 355 dev_err(pctldev->dev, "pull-up can not be total\n"); 356 return -EINVAL; 357 } 358 break; 359 case PIN_CONFIG_BIAS_PULL_DOWN: 360 if (pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED && arg != 0) 361 return 0; 362 if (pull_dir != UNIPHIER_PIN_PULL_DOWN) { 363 dev_err(pctldev->dev, 364 "pull-down is unsupported for pin %s\n", 365 desc->name); 366 return -EINVAL; 367 } 368 if (arg == 0) { 369 dev_err(pctldev->dev, "pull-down can not be total\n"); 370 return -EINVAL; 371 } 372 break; 373 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 374 if (pull_dir == UNIPHIER_PIN_PULL_NONE) { 375 dev_err(pctldev->dev, 376 "pull-up/down is unsupported for pin %s\n", 377 desc->name); 378 return -EINVAL; 379 } 380 381 if (arg == 0) 382 return 0; /* configuration ingored */ 383 break; 384 default: 385 BUG(); 386 } 387 388 pupdctrl = uniphier_pin_get_pupdctrl(desc->drv_data); 389 390 reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4; 391 shift = pupdctrl % 32; 392 393 return regmap_update_bits(priv->regmap, reg, 1 << shift, val << shift); 394 } 395 396 static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev, 397 unsigned int pin, u32 strength) 398 { 399 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 400 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 401 enum uniphier_pin_drv_type type = 402 uniphier_pin_get_drv_type(desc->drv_data); 403 static const unsigned int strength_1bit[] = {4, 8, -1}; 404 static const unsigned int strength_2bit[] = {8, 12, 16, 20, -1}; 405 static const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14, 406 16, -1}; 407 const unsigned int *supported_strength; 408 unsigned int drvctrl, reg, shift, mask, width, val; 409 410 switch (type) { 411 case UNIPHIER_PIN_DRV_1BIT: 412 supported_strength = strength_1bit; 413 reg = UNIPHIER_PINCTRL_DRVCTRL_BASE; 414 width = 1; 415 break; 416 case UNIPHIER_PIN_DRV_2BIT: 417 supported_strength = strength_2bit; 418 reg = UNIPHIER_PINCTRL_DRV2CTRL_BASE; 419 width = 2; 420 break; 421 case UNIPHIER_PIN_DRV_3BIT: 422 supported_strength = strength_3bit; 423 reg = UNIPHIER_PINCTRL_DRV3CTRL_BASE; 424 width = 4; 425 break; 426 default: 427 dev_err(pctldev->dev, 428 "cannot change drive strength for pin %s\n", 429 desc->name); 430 return -EINVAL; 431 } 432 433 for (val = 0; supported_strength[val] > 0; val++) { 434 if (supported_strength[val] > strength) 435 break; 436 } 437 438 if (val == 0) { 439 dev_err(pctldev->dev, 440 "unsupported drive strength %u mA for pin %s\n", 441 strength, desc->name); 442 return -EINVAL; 443 } 444 445 val--; 446 447 drvctrl = uniphier_pin_get_drvctrl(desc->drv_data); 448 drvctrl *= width; 449 450 reg += drvctrl / 32 * 4; 451 shift = drvctrl % 32; 452 mask = (1U << width) - 1; 453 454 return regmap_update_bits(priv->regmap, reg, 455 mask << shift, val << shift); 456 } 457 458 static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev, 459 unsigned int pin, u32 enable) 460 { 461 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 462 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 463 unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data); 464 unsigned int reg, mask; 465 466 /* 467 * Multiple pins share one input enable, per-pin disabling is 468 * impossible. 469 */ 470 if (!(priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) && 471 !enable) 472 return -EINVAL; 473 474 /* UNIPHIER_PIN_IECTRL_NONE means the pin is always input-enabled */ 475 if (iectrl == UNIPHIER_PIN_IECTRL_NONE) 476 return enable ? 0 : -EINVAL; 477 478 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) 479 iectrl = pin; 480 481 reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4; 482 mask = BIT(iectrl % 32); 483 484 return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0); 485 } 486 487 static int uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev, 488 unsigned pin, 489 unsigned long *configs, 490 unsigned num_configs) 491 { 492 int i, ret; 493 494 for (i = 0; i < num_configs; i++) { 495 enum pin_config_param param = 496 pinconf_to_config_param(configs[i]); 497 u32 arg = pinconf_to_config_argument(configs[i]); 498 499 switch (param) { 500 case PIN_CONFIG_BIAS_DISABLE: 501 case PIN_CONFIG_BIAS_PULL_UP: 502 case PIN_CONFIG_BIAS_PULL_DOWN: 503 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 504 ret = uniphier_conf_pin_bias_set(pctldev, pin, 505 param, arg); 506 break; 507 case PIN_CONFIG_DRIVE_STRENGTH: 508 ret = uniphier_conf_pin_drive_set(pctldev, pin, arg); 509 break; 510 case PIN_CONFIG_INPUT_ENABLE: 511 ret = uniphier_conf_pin_input_enable(pctldev, pin, arg); 512 break; 513 default: 514 dev_err(pctldev->dev, 515 "unsupported configuration parameter %u\n", 516 param); 517 return -EINVAL; 518 } 519 520 if (ret) 521 return ret; 522 } 523 524 return 0; 525 } 526 527 static int uniphier_conf_pin_config_group_set(struct pinctrl_dev *pctldev, 528 unsigned selector, 529 unsigned long *configs, 530 unsigned num_configs) 531 { 532 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 533 const unsigned *pins = priv->socdata->groups[selector].pins; 534 unsigned num_pins = priv->socdata->groups[selector].num_pins; 535 int i, ret; 536 537 for (i = 0; i < num_pins; i++) { 538 ret = uniphier_conf_pin_config_set(pctldev, pins[i], 539 configs, num_configs); 540 if (ret) 541 return ret; 542 } 543 544 return 0; 545 } 546 547 static const struct pinconf_ops uniphier_confops = { 548 .is_generic = true, 549 .pin_config_get = uniphier_conf_pin_config_get, 550 .pin_config_set = uniphier_conf_pin_config_set, 551 .pin_config_group_set = uniphier_conf_pin_config_group_set, 552 }; 553 554 static int uniphier_pmx_get_functions_count(struct pinctrl_dev *pctldev) 555 { 556 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 557 558 return priv->socdata->functions_count; 559 } 560 561 static const char *uniphier_pmx_get_function_name(struct pinctrl_dev *pctldev, 562 unsigned selector) 563 { 564 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 565 566 return priv->socdata->functions[selector].name; 567 } 568 569 static int uniphier_pmx_get_function_groups(struct pinctrl_dev *pctldev, 570 unsigned selector, 571 const char * const **groups, 572 unsigned *num_groups) 573 { 574 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 575 576 *groups = priv->socdata->functions[selector].groups; 577 *num_groups = priv->socdata->functions[selector].num_groups; 578 579 return 0; 580 } 581 582 static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin, 583 int muxval) 584 { 585 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 586 unsigned int mux_bits, reg_stride, reg, reg_end, shift, mask; 587 bool load_pinctrl; 588 int ret; 589 590 /* some pins need input-enabling */ 591 ret = uniphier_conf_pin_input_enable(pctldev, pin, 1); 592 if (ret) 593 return ret; 594 595 if (muxval < 0) 596 return 0; /* dedicated pin; nothing to do for pin-mux */ 597 598 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) { 599 /* 600 * Mode reg_offset bit_position 601 * Normal 4 * n shift+3:shift 602 * Debug 4 * n shift+7:shift+4 603 */ 604 mux_bits = 4; 605 reg_stride = 8; 606 load_pinctrl = true; 607 } else { 608 /* 609 * Mode reg_offset bit_position 610 * Normal 8 * n shift+3:shift 611 * Debug 8 * n + 4 shift+3:shift 612 */ 613 mux_bits = 8; 614 reg_stride = 4; 615 load_pinctrl = false; 616 } 617 618 reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; 619 reg_end = reg + reg_stride; 620 shift = pin * mux_bits % 32; 621 mask = (1U << mux_bits) - 1; 622 623 /* 624 * If reg_stride is greater than 4, the MSB of each pinsel shall be 625 * stored in the offset+4. 626 */ 627 for (; reg < reg_end; reg += 4) { 628 ret = regmap_update_bits(priv->regmap, reg, 629 mask << shift, muxval << shift); 630 if (ret) 631 return ret; 632 muxval >>= mux_bits; 633 } 634 635 if (load_pinctrl) { 636 ret = regmap_write(priv->regmap, 637 UNIPHIER_PINCTRL_LOAD_PINMUX, 1); 638 if (ret) 639 return ret; 640 } 641 642 return 0; 643 } 644 645 static int uniphier_pmx_set_mux(struct pinctrl_dev *pctldev, 646 unsigned func_selector, 647 unsigned group_selector) 648 { 649 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 650 const struct uniphier_pinctrl_group *grp = 651 &priv->socdata->groups[group_selector]; 652 int i; 653 int ret; 654 655 for (i = 0; i < grp->num_pins; i++) { 656 ret = uniphier_pmx_set_one_mux(pctldev, grp->pins[i], 657 grp->muxvals[i]); 658 if (ret) 659 return ret; 660 } 661 662 return 0; 663 } 664 665 static int uniphier_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, 666 struct pinctrl_gpio_range *range, 667 unsigned offset) 668 { 669 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 670 unsigned int gpio_offset; 671 int muxval, i; 672 673 if (range->pins) { 674 for (i = 0; i < range->npins; i++) 675 if (range->pins[i] == offset) 676 break; 677 678 if (WARN_ON(i == range->npins)) 679 return -EINVAL; 680 681 gpio_offset = i; 682 } else { 683 gpio_offset = offset - range->pin_base; 684 } 685 686 gpio_offset += range->id; 687 688 muxval = priv->socdata->get_gpio_muxval(offset, gpio_offset); 689 690 return uniphier_pmx_set_one_mux(pctldev, offset, muxval); 691 } 692 693 static const struct pinmux_ops uniphier_pmxops = { 694 .get_functions_count = uniphier_pmx_get_functions_count, 695 .get_function_name = uniphier_pmx_get_function_name, 696 .get_function_groups = uniphier_pmx_get_function_groups, 697 .set_mux = uniphier_pmx_set_mux, 698 .gpio_request_enable = uniphier_pmx_gpio_request_enable, 699 .strict = true, 700 }; 701 702 #ifdef CONFIG_PM_SLEEP 703 static int uniphier_pinctrl_suspend(struct device *dev) 704 { 705 struct uniphier_pinctrl_priv *priv = dev_get_drvdata(dev); 706 struct uniphier_pinctrl_reg_region *r; 707 int ret; 708 709 list_for_each_entry(r, &priv->reg_regions, node) { 710 ret = regmap_bulk_read(priv->regmap, r->base, r->vals, 711 r->nregs); 712 if (ret) 713 return ret; 714 } 715 716 return 0; 717 } 718 719 static int uniphier_pinctrl_resume(struct device *dev) 720 { 721 struct uniphier_pinctrl_priv *priv = dev_get_drvdata(dev); 722 struct uniphier_pinctrl_reg_region *r; 723 int ret; 724 725 list_for_each_entry(r, &priv->reg_regions, node) { 726 ret = regmap_bulk_write(priv->regmap, r->base, r->vals, 727 r->nregs); 728 if (ret) 729 return ret; 730 } 731 732 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) { 733 ret = regmap_write(priv->regmap, 734 UNIPHIER_PINCTRL_LOAD_PINMUX, 1); 735 if (ret) 736 return ret; 737 } 738 739 return 0; 740 } 741 742 static int uniphier_pinctrl_add_reg_region(struct device *dev, 743 struct uniphier_pinctrl_priv *priv, 744 unsigned int base, 745 unsigned int count, 746 unsigned int width) 747 { 748 struct uniphier_pinctrl_reg_region *region; 749 unsigned int nregs; 750 751 if (!count) 752 return 0; 753 754 nregs = DIV_ROUND_UP(count * width, 32); 755 756 region = devm_kzalloc(dev, 757 sizeof(*region) + sizeof(region->vals[0]) * nregs, 758 GFP_KERNEL); 759 if (!region) 760 return -ENOMEM; 761 762 region->base = base; 763 region->nregs = nregs; 764 765 list_add_tail(®ion->node, &priv->reg_regions); 766 767 return 0; 768 } 769 #endif 770 771 static int uniphier_pinctrl_pm_init(struct device *dev, 772 struct uniphier_pinctrl_priv *priv) 773 { 774 #ifdef CONFIG_PM_SLEEP 775 const struct uniphier_pinctrl_socdata *socdata = priv->socdata; 776 unsigned int num_drvctrl = 0; 777 unsigned int num_drv2ctrl = 0; 778 unsigned int num_drv3ctrl = 0; 779 unsigned int num_pupdctrl = 0; 780 unsigned int num_iectrl = 0; 781 unsigned int iectrl, drvctrl, pupdctrl; 782 enum uniphier_pin_drv_type drv_type; 783 enum uniphier_pin_pull_dir pull_dir; 784 int i, ret; 785 786 for (i = 0; i < socdata->npins; i++) { 787 void *drv_data = socdata->pins[i].drv_data; 788 789 drvctrl = uniphier_pin_get_drvctrl(drv_data); 790 drv_type = uniphier_pin_get_drv_type(drv_data); 791 pupdctrl = uniphier_pin_get_pupdctrl(drv_data); 792 pull_dir = uniphier_pin_get_pull_dir(drv_data); 793 iectrl = uniphier_pin_get_iectrl(drv_data); 794 795 switch (drv_type) { 796 case UNIPHIER_PIN_DRV_1BIT: 797 num_drvctrl = max(num_drvctrl, drvctrl + 1); 798 break; 799 case UNIPHIER_PIN_DRV_2BIT: 800 num_drv2ctrl = max(num_drv2ctrl, drvctrl + 1); 801 break; 802 case UNIPHIER_PIN_DRV_3BIT: 803 num_drv3ctrl = max(num_drv3ctrl, drvctrl + 1); 804 break; 805 default: 806 break; 807 } 808 809 if (pull_dir == UNIPHIER_PIN_PULL_UP || 810 pull_dir == UNIPHIER_PIN_PULL_DOWN) 811 num_pupdctrl = max(num_pupdctrl, pupdctrl + 1); 812 813 if (iectrl != UNIPHIER_PIN_IECTRL_NONE) { 814 if (socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) 815 iectrl = i; 816 num_iectrl = max(num_iectrl, iectrl + 1); 817 } 818 } 819 820 INIT_LIST_HEAD(&priv->reg_regions); 821 822 ret = uniphier_pinctrl_add_reg_region(dev, priv, 823 UNIPHIER_PINCTRL_PINMUX_BASE, 824 socdata->npins, 8); 825 if (ret) 826 return ret; 827 828 ret = uniphier_pinctrl_add_reg_region(dev, priv, 829 UNIPHIER_PINCTRL_DRVCTRL_BASE, 830 num_drvctrl, 1); 831 if (ret) 832 return ret; 833 834 ret = uniphier_pinctrl_add_reg_region(dev, priv, 835 UNIPHIER_PINCTRL_DRV2CTRL_BASE, 836 num_drv2ctrl, 2); 837 if (ret) 838 return ret; 839 840 ret = uniphier_pinctrl_add_reg_region(dev, priv, 841 UNIPHIER_PINCTRL_DRV3CTRL_BASE, 842 num_drv3ctrl, 3); 843 if (ret) 844 return ret; 845 846 ret = uniphier_pinctrl_add_reg_region(dev, priv, 847 UNIPHIER_PINCTRL_PUPDCTRL_BASE, 848 num_pupdctrl, 1); 849 if (ret) 850 return ret; 851 852 ret = uniphier_pinctrl_add_reg_region(dev, priv, 853 UNIPHIER_PINCTRL_IECTRL_BASE, 854 num_iectrl, 1); 855 if (ret) 856 return ret; 857 #endif 858 return 0; 859 } 860 861 const struct dev_pm_ops uniphier_pinctrl_pm_ops = { 862 SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_pinctrl_suspend, 863 uniphier_pinctrl_resume) 864 }; 865 866 int uniphier_pinctrl_probe(struct platform_device *pdev, 867 struct uniphier_pinctrl_socdata *socdata) 868 { 869 struct device *dev = &pdev->dev; 870 struct uniphier_pinctrl_priv *priv; 871 struct device_node *parent; 872 int ret; 873 874 if (!socdata || 875 !socdata->pins || !socdata->npins || 876 !socdata->groups || !socdata->groups_count || 877 !socdata->functions || !socdata->functions_count) { 878 dev_err(dev, "pinctrl socdata lacks necessary members\n"); 879 return -EINVAL; 880 } 881 882 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 883 if (!priv) 884 return -ENOMEM; 885 886 parent = of_get_parent(dev->of_node); 887 priv->regmap = syscon_node_to_regmap(parent); 888 of_node_put(parent); 889 890 if (IS_ERR(priv->regmap)) { 891 dev_err(dev, "failed to get regmap\n"); 892 return PTR_ERR(priv->regmap); 893 } 894 895 priv->socdata = socdata; 896 priv->pctldesc.name = dev->driver->name; 897 priv->pctldesc.pins = socdata->pins; 898 priv->pctldesc.npins = socdata->npins; 899 priv->pctldesc.pctlops = &uniphier_pctlops; 900 priv->pctldesc.pmxops = &uniphier_pmxops; 901 priv->pctldesc.confops = &uniphier_confops; 902 priv->pctldesc.owner = dev->driver->owner; 903 904 ret = uniphier_pinctrl_pm_init(dev, priv); 905 if (ret) 906 return ret; 907 908 priv->pctldev = devm_pinctrl_register(dev, &priv->pctldesc, priv); 909 if (IS_ERR(priv->pctldev)) { 910 dev_err(dev, "failed to register UniPhier pinctrl driver\n"); 911 return PTR_ERR(priv->pctldev); 912 } 913 914 platform_set_drvdata(pdev, priv); 915 916 return 0; 917 } 918