1 /* 2 * Copyright (C) 2015-2017 Socionext Inc. 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/list.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/of.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 26 #include "../core.h" 27 #include "../pinctrl-utils.h" 28 #include "pinctrl-uniphier.h" 29 30 #define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000 31 #define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700 32 #define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x1800 33 #define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x1900 34 #define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x1980 35 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00 36 #define UNIPHIER_PINCTRL_IECTRL_BASE 0x1d00 37 38 struct uniphier_pinctrl_reg_region { 39 struct list_head node; 40 unsigned int base; 41 unsigned int nregs; 42 u32 vals[0]; 43 }; 44 45 struct uniphier_pinctrl_priv { 46 struct pinctrl_desc pctldesc; 47 struct pinctrl_dev *pctldev; 48 struct regmap *regmap; 49 struct uniphier_pinctrl_socdata *socdata; 50 struct list_head reg_regions; 51 }; 52 53 static int uniphier_pctl_get_groups_count(struct pinctrl_dev *pctldev) 54 { 55 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 56 57 return priv->socdata->groups_count; 58 } 59 60 static const char *uniphier_pctl_get_group_name(struct pinctrl_dev *pctldev, 61 unsigned selector) 62 { 63 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 64 65 return priv->socdata->groups[selector].name; 66 } 67 68 static int uniphier_pctl_get_group_pins(struct pinctrl_dev *pctldev, 69 unsigned selector, 70 const unsigned **pins, 71 unsigned *num_pins) 72 { 73 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 74 75 *pins = priv->socdata->groups[selector].pins; 76 *num_pins = priv->socdata->groups[selector].num_pins; 77 78 return 0; 79 } 80 81 #ifdef CONFIG_DEBUG_FS 82 static void uniphier_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, 83 struct seq_file *s, unsigned offset) 84 { 85 const struct pin_desc *desc = pin_desc_get(pctldev, offset); 86 const char *pull_dir, *drv_type; 87 88 switch (uniphier_pin_get_pull_dir(desc->drv_data)) { 89 case UNIPHIER_PIN_PULL_UP: 90 pull_dir = "UP"; 91 break; 92 case UNIPHIER_PIN_PULL_DOWN: 93 pull_dir = "DOWN"; 94 break; 95 case UNIPHIER_PIN_PULL_UP_FIXED: 96 pull_dir = "UP(FIXED)"; 97 break; 98 case UNIPHIER_PIN_PULL_DOWN_FIXED: 99 pull_dir = "DOWN(FIXED)"; 100 break; 101 case UNIPHIER_PIN_PULL_NONE: 102 pull_dir = "NONE"; 103 break; 104 default: 105 BUG(); 106 } 107 108 switch (uniphier_pin_get_drv_type(desc->drv_data)) { 109 case UNIPHIER_PIN_DRV_1BIT: 110 drv_type = "4/8(mA)"; 111 break; 112 case UNIPHIER_PIN_DRV_2BIT: 113 drv_type = "8/12/16/20(mA)"; 114 break; 115 case UNIPHIER_PIN_DRV_3BIT: 116 drv_type = "4/5/7/9/11/12/14/16(mA)"; 117 break; 118 case UNIPHIER_PIN_DRV_FIXED4: 119 drv_type = "4(mA)"; 120 break; 121 case UNIPHIER_PIN_DRV_FIXED5: 122 drv_type = "5(mA)"; 123 break; 124 case UNIPHIER_PIN_DRV_FIXED8: 125 drv_type = "8(mA)"; 126 break; 127 case UNIPHIER_PIN_DRV_NONE: 128 drv_type = "NONE"; 129 break; 130 default: 131 BUG(); 132 } 133 134 seq_printf(s, " PULL_DIR=%s DRV_TYPE=%s", pull_dir, drv_type); 135 } 136 #endif 137 138 static const struct pinctrl_ops uniphier_pctlops = { 139 .get_groups_count = uniphier_pctl_get_groups_count, 140 .get_group_name = uniphier_pctl_get_group_name, 141 .get_group_pins = uniphier_pctl_get_group_pins, 142 #ifdef CONFIG_DEBUG_FS 143 .pin_dbg_show = uniphier_pctl_pin_dbg_show, 144 #endif 145 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 146 .dt_free_map = pinctrl_utils_free_map, 147 }; 148 149 static const unsigned int uniphier_conf_drv_strengths_1bit[] = {4, 8}; 150 static const unsigned int uniphier_conf_drv_strengths_2bit[] = {8, 12, 16, 20}; 151 static const unsigned int uniphier_conf_drv_strengths_3bit[] = {4, 5, 7, 9, 11, 152 12, 14, 16}; 153 static const unsigned int uniphier_conf_drv_strengths_fixed4[] = {4}; 154 static const unsigned int uniphier_conf_drv_strengths_fixed5[] = {5}; 155 static const unsigned int uniphier_conf_drv_strengths_fixed8[] = {8}; 156 157 static int uniphier_conf_get_drvctrl_data(struct pinctrl_dev *pctldev, 158 unsigned int pin, unsigned int *reg, 159 unsigned int *shift, 160 unsigned int *mask, 161 const unsigned int **strengths) 162 { 163 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 164 enum uniphier_pin_drv_type type = 165 uniphier_pin_get_drv_type(desc->drv_data); 166 unsigned int base = 0; 167 unsigned int stride = 0; 168 unsigned int width = 0; 169 unsigned int drvctrl; 170 171 switch (type) { 172 case UNIPHIER_PIN_DRV_1BIT: 173 *strengths = uniphier_conf_drv_strengths_1bit; 174 base = UNIPHIER_PINCTRL_DRVCTRL_BASE; 175 stride = 1; 176 width = 1; 177 break; 178 case UNIPHIER_PIN_DRV_2BIT: 179 *strengths = uniphier_conf_drv_strengths_2bit; 180 base = UNIPHIER_PINCTRL_DRV2CTRL_BASE; 181 stride = 2; 182 width = 2; 183 break; 184 case UNIPHIER_PIN_DRV_3BIT: 185 *strengths = uniphier_conf_drv_strengths_3bit; 186 base = UNIPHIER_PINCTRL_DRV3CTRL_BASE; 187 stride = 4; 188 width = 3; 189 break; 190 case UNIPHIER_PIN_DRV_FIXED4: 191 *strengths = uniphier_conf_drv_strengths_fixed4; 192 break; 193 case UNIPHIER_PIN_DRV_FIXED5: 194 *strengths = uniphier_conf_drv_strengths_fixed5; 195 break; 196 case UNIPHIER_PIN_DRV_FIXED8: 197 *strengths = uniphier_conf_drv_strengths_fixed8; 198 break; 199 default: 200 /* drive strength control is not supported for this pin */ 201 return -EINVAL; 202 } 203 204 drvctrl = uniphier_pin_get_drvctrl(desc->drv_data); 205 drvctrl *= stride; 206 207 *reg = base + drvctrl / 32 * 4; 208 *shift = drvctrl % 32; 209 *mask = (1U << width) - 1; 210 211 return 0; 212 } 213 214 static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev, 215 unsigned int pin, 216 enum pin_config_param param) 217 { 218 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 219 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 220 enum uniphier_pin_pull_dir pull_dir = 221 uniphier_pin_get_pull_dir(desc->drv_data); 222 unsigned int pupdctrl, reg, shift, val; 223 unsigned int expected = 1; 224 int ret; 225 226 switch (param) { 227 case PIN_CONFIG_BIAS_DISABLE: 228 if (pull_dir == UNIPHIER_PIN_PULL_NONE) 229 return 0; 230 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED || 231 pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED) 232 return -EINVAL; 233 expected = 0; 234 break; 235 case PIN_CONFIG_BIAS_PULL_UP: 236 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED) 237 return 0; 238 if (pull_dir != UNIPHIER_PIN_PULL_UP) 239 return -EINVAL; 240 break; 241 case PIN_CONFIG_BIAS_PULL_DOWN: 242 if (pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED) 243 return 0; 244 if (pull_dir != UNIPHIER_PIN_PULL_DOWN) 245 return -EINVAL; 246 break; 247 default: 248 BUG(); 249 } 250 251 pupdctrl = uniphier_pin_get_pupdctrl(desc->drv_data); 252 253 reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4; 254 shift = pupdctrl % 32; 255 256 ret = regmap_read(priv->regmap, reg, &val); 257 if (ret) 258 return ret; 259 260 val = (val >> shift) & 1; 261 262 return (val == expected) ? 0 : -EINVAL; 263 } 264 265 static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev, 266 unsigned int pin, u32 *strength) 267 { 268 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 269 unsigned int reg, shift, mask, val; 270 const unsigned int *strengths; 271 int ret; 272 273 ret = uniphier_conf_get_drvctrl_data(pctldev, pin, ®, &shift, 274 &mask, &strengths); 275 if (ret) 276 return ret; 277 278 if (mask) { 279 ret = regmap_read(priv->regmap, reg, &val); 280 if (ret) 281 return ret; 282 } else { 283 val = 0; 284 } 285 286 *strength = strengths[(val >> shift) & mask]; 287 288 return 0; 289 } 290 291 static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev, 292 unsigned int pin) 293 { 294 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 295 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 296 unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data); 297 unsigned int reg, mask, val; 298 int ret; 299 300 if (iectrl == UNIPHIER_PIN_IECTRL_NONE) 301 /* This pin is always input-enabled. */ 302 return 0; 303 304 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) 305 iectrl = pin; 306 307 reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4; 308 mask = BIT(iectrl % 32); 309 310 ret = regmap_read(priv->regmap, reg, &val); 311 if (ret) 312 return ret; 313 314 return val & mask ? 0 : -EINVAL; 315 } 316 317 static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev, 318 unsigned pin, 319 unsigned long *configs) 320 { 321 enum pin_config_param param = pinconf_to_config_param(*configs); 322 bool has_arg = false; 323 u32 arg; 324 int ret; 325 326 switch (param) { 327 case PIN_CONFIG_BIAS_DISABLE: 328 case PIN_CONFIG_BIAS_PULL_UP: 329 case PIN_CONFIG_BIAS_PULL_DOWN: 330 ret = uniphier_conf_pin_bias_get(pctldev, pin, param); 331 break; 332 case PIN_CONFIG_DRIVE_STRENGTH: 333 ret = uniphier_conf_pin_drive_get(pctldev, pin, &arg); 334 has_arg = true; 335 break; 336 case PIN_CONFIG_INPUT_ENABLE: 337 ret = uniphier_conf_pin_input_enable_get(pctldev, pin); 338 break; 339 default: 340 /* unsupported parameter */ 341 ret = -EINVAL; 342 break; 343 } 344 345 if (ret == 0 && has_arg) 346 *configs = pinconf_to_config_packed(param, arg); 347 348 return ret; 349 } 350 351 static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev, 352 unsigned int pin, 353 enum pin_config_param param, u32 arg) 354 { 355 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 356 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 357 enum uniphier_pin_pull_dir pull_dir = 358 uniphier_pin_get_pull_dir(desc->drv_data); 359 unsigned int pupdctrl, reg, shift; 360 unsigned int val = 1; 361 362 switch (param) { 363 case PIN_CONFIG_BIAS_DISABLE: 364 if (pull_dir == UNIPHIER_PIN_PULL_NONE) 365 return 0; 366 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED || 367 pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED) { 368 dev_err(pctldev->dev, 369 "can not disable pull register for pin %s\n", 370 desc->name); 371 return -EINVAL; 372 } 373 val = 0; 374 break; 375 case PIN_CONFIG_BIAS_PULL_UP: 376 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED && arg != 0) 377 return 0; 378 if (pull_dir != UNIPHIER_PIN_PULL_UP) { 379 dev_err(pctldev->dev, 380 "pull-up is unsupported for pin %s\n", 381 desc->name); 382 return -EINVAL; 383 } 384 if (arg == 0) { 385 dev_err(pctldev->dev, "pull-up can not be total\n"); 386 return -EINVAL; 387 } 388 break; 389 case PIN_CONFIG_BIAS_PULL_DOWN: 390 if (pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED && arg != 0) 391 return 0; 392 if (pull_dir != UNIPHIER_PIN_PULL_DOWN) { 393 dev_err(pctldev->dev, 394 "pull-down is unsupported for pin %s\n", 395 desc->name); 396 return -EINVAL; 397 } 398 if (arg == 0) { 399 dev_err(pctldev->dev, "pull-down can not be total\n"); 400 return -EINVAL; 401 } 402 break; 403 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 404 if (pull_dir == UNIPHIER_PIN_PULL_NONE) { 405 dev_err(pctldev->dev, 406 "pull-up/down is unsupported for pin %s\n", 407 desc->name); 408 return -EINVAL; 409 } 410 411 if (arg == 0) 412 return 0; /* configuration ingored */ 413 break; 414 default: 415 BUG(); 416 } 417 418 pupdctrl = uniphier_pin_get_pupdctrl(desc->drv_data); 419 420 reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4; 421 shift = pupdctrl % 32; 422 423 return regmap_update_bits(priv->regmap, reg, 1 << shift, val << shift); 424 } 425 426 static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev, 427 unsigned int pin, u32 strength) 428 { 429 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 430 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 431 unsigned int reg, shift, mask, val; 432 const unsigned int *strengths; 433 int ret; 434 435 ret = uniphier_conf_get_drvctrl_data(pctldev, pin, ®, &shift, 436 &mask, &strengths); 437 if (ret) { 438 dev_err(pctldev->dev, "cannot set drive strength for pin %s\n", 439 desc->name); 440 return ret; 441 } 442 443 for (val = 0; val <= mask; val++) { 444 if (strengths[val] > strength) 445 break; 446 } 447 448 if (val == 0) { 449 dev_err(pctldev->dev, 450 "unsupported drive strength %u mA for pin %s\n", 451 strength, desc->name); 452 return -EINVAL; 453 } 454 455 if (!mask) 456 return 0; 457 458 val--; 459 460 return regmap_update_bits(priv->regmap, reg, 461 mask << shift, val << shift); 462 } 463 464 static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev, 465 unsigned int pin, u32 enable) 466 { 467 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 468 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 469 unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data); 470 unsigned int reg, mask; 471 472 /* 473 * Multiple pins share one input enable, per-pin disabling is 474 * impossible. 475 */ 476 if (!(priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) && 477 !enable) 478 return -EINVAL; 479 480 /* UNIPHIER_PIN_IECTRL_NONE means the pin is always input-enabled */ 481 if (iectrl == UNIPHIER_PIN_IECTRL_NONE) 482 return enable ? 0 : -EINVAL; 483 484 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) 485 iectrl = pin; 486 487 reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4; 488 mask = BIT(iectrl % 32); 489 490 return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0); 491 } 492 493 static int uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev, 494 unsigned pin, 495 unsigned long *configs, 496 unsigned num_configs) 497 { 498 int i, ret; 499 500 for (i = 0; i < num_configs; i++) { 501 enum pin_config_param param = 502 pinconf_to_config_param(configs[i]); 503 u32 arg = pinconf_to_config_argument(configs[i]); 504 505 switch (param) { 506 case PIN_CONFIG_BIAS_DISABLE: 507 case PIN_CONFIG_BIAS_PULL_UP: 508 case PIN_CONFIG_BIAS_PULL_DOWN: 509 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 510 ret = uniphier_conf_pin_bias_set(pctldev, pin, 511 param, arg); 512 break; 513 case PIN_CONFIG_DRIVE_STRENGTH: 514 ret = uniphier_conf_pin_drive_set(pctldev, pin, arg); 515 break; 516 case PIN_CONFIG_INPUT_ENABLE: 517 ret = uniphier_conf_pin_input_enable(pctldev, pin, arg); 518 break; 519 default: 520 dev_err(pctldev->dev, 521 "unsupported configuration parameter %u\n", 522 param); 523 return -EINVAL; 524 } 525 526 if (ret) 527 return ret; 528 } 529 530 return 0; 531 } 532 533 static int uniphier_conf_pin_config_group_set(struct pinctrl_dev *pctldev, 534 unsigned selector, 535 unsigned long *configs, 536 unsigned num_configs) 537 { 538 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 539 const unsigned *pins = priv->socdata->groups[selector].pins; 540 unsigned num_pins = priv->socdata->groups[selector].num_pins; 541 int i, ret; 542 543 for (i = 0; i < num_pins; i++) { 544 ret = uniphier_conf_pin_config_set(pctldev, pins[i], 545 configs, num_configs); 546 if (ret) 547 return ret; 548 } 549 550 return 0; 551 } 552 553 static const struct pinconf_ops uniphier_confops = { 554 .is_generic = true, 555 .pin_config_get = uniphier_conf_pin_config_get, 556 .pin_config_set = uniphier_conf_pin_config_set, 557 .pin_config_group_set = uniphier_conf_pin_config_group_set, 558 }; 559 560 static int uniphier_pmx_get_functions_count(struct pinctrl_dev *pctldev) 561 { 562 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 563 564 return priv->socdata->functions_count; 565 } 566 567 static const char *uniphier_pmx_get_function_name(struct pinctrl_dev *pctldev, 568 unsigned selector) 569 { 570 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 571 572 return priv->socdata->functions[selector].name; 573 } 574 575 static int uniphier_pmx_get_function_groups(struct pinctrl_dev *pctldev, 576 unsigned selector, 577 const char * const **groups, 578 unsigned *num_groups) 579 { 580 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 581 582 *groups = priv->socdata->functions[selector].groups; 583 *num_groups = priv->socdata->functions[selector].num_groups; 584 585 return 0; 586 } 587 588 static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin, 589 int muxval) 590 { 591 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 592 unsigned int mux_bits, reg_stride, reg, reg_end, shift, mask; 593 bool load_pinctrl; 594 int ret; 595 596 /* some pins need input-enabling */ 597 ret = uniphier_conf_pin_input_enable(pctldev, pin, 1); 598 if (ret) 599 return ret; 600 601 if (muxval < 0) 602 return 0; /* dedicated pin; nothing to do for pin-mux */ 603 604 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) { 605 /* 606 * Mode reg_offset bit_position 607 * Normal 4 * n shift+3:shift 608 * Debug 4 * n shift+7:shift+4 609 */ 610 mux_bits = 4; 611 reg_stride = 8; 612 load_pinctrl = true; 613 } else { 614 /* 615 * Mode reg_offset bit_position 616 * Normal 8 * n shift+3:shift 617 * Debug 8 * n + 4 shift+3:shift 618 */ 619 mux_bits = 8; 620 reg_stride = 4; 621 load_pinctrl = false; 622 } 623 624 reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; 625 reg_end = reg + reg_stride; 626 shift = pin * mux_bits % 32; 627 mask = (1U << mux_bits) - 1; 628 629 /* 630 * If reg_stride is greater than 4, the MSB of each pinsel shall be 631 * stored in the offset+4. 632 */ 633 for (; reg < reg_end; reg += 4) { 634 ret = regmap_update_bits(priv->regmap, reg, 635 mask << shift, muxval << shift); 636 if (ret) 637 return ret; 638 muxval >>= mux_bits; 639 } 640 641 if (load_pinctrl) { 642 ret = regmap_write(priv->regmap, 643 UNIPHIER_PINCTRL_LOAD_PINMUX, 1); 644 if (ret) 645 return ret; 646 } 647 648 return 0; 649 } 650 651 static int uniphier_pmx_set_mux(struct pinctrl_dev *pctldev, 652 unsigned func_selector, 653 unsigned group_selector) 654 { 655 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 656 const struct uniphier_pinctrl_group *grp = 657 &priv->socdata->groups[group_selector]; 658 int i; 659 int ret; 660 661 for (i = 0; i < grp->num_pins; i++) { 662 ret = uniphier_pmx_set_one_mux(pctldev, grp->pins[i], 663 grp->muxvals[i]); 664 if (ret) 665 return ret; 666 } 667 668 return 0; 669 } 670 671 static int uniphier_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, 672 struct pinctrl_gpio_range *range, 673 unsigned offset) 674 { 675 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 676 unsigned int gpio_offset; 677 int muxval, i; 678 679 if (range->pins) { 680 for (i = 0; i < range->npins; i++) 681 if (range->pins[i] == offset) 682 break; 683 684 if (WARN_ON(i == range->npins)) 685 return -EINVAL; 686 687 gpio_offset = i; 688 } else { 689 gpio_offset = offset - range->pin_base; 690 } 691 692 gpio_offset += range->id; 693 694 muxval = priv->socdata->get_gpio_muxval(offset, gpio_offset); 695 696 return uniphier_pmx_set_one_mux(pctldev, offset, muxval); 697 } 698 699 static const struct pinmux_ops uniphier_pmxops = { 700 .get_functions_count = uniphier_pmx_get_functions_count, 701 .get_function_name = uniphier_pmx_get_function_name, 702 .get_function_groups = uniphier_pmx_get_function_groups, 703 .set_mux = uniphier_pmx_set_mux, 704 .gpio_request_enable = uniphier_pmx_gpio_request_enable, 705 .strict = true, 706 }; 707 708 #ifdef CONFIG_PM_SLEEP 709 static int uniphier_pinctrl_suspend(struct device *dev) 710 { 711 struct uniphier_pinctrl_priv *priv = dev_get_drvdata(dev); 712 struct uniphier_pinctrl_reg_region *r; 713 int ret; 714 715 list_for_each_entry(r, &priv->reg_regions, node) { 716 ret = regmap_bulk_read(priv->regmap, r->base, r->vals, 717 r->nregs); 718 if (ret) 719 return ret; 720 } 721 722 return 0; 723 } 724 725 static int uniphier_pinctrl_resume(struct device *dev) 726 { 727 struct uniphier_pinctrl_priv *priv = dev_get_drvdata(dev); 728 struct uniphier_pinctrl_reg_region *r; 729 int ret; 730 731 list_for_each_entry(r, &priv->reg_regions, node) { 732 ret = regmap_bulk_write(priv->regmap, r->base, r->vals, 733 r->nregs); 734 if (ret) 735 return ret; 736 } 737 738 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) { 739 ret = regmap_write(priv->regmap, 740 UNIPHIER_PINCTRL_LOAD_PINMUX, 1); 741 if (ret) 742 return ret; 743 } 744 745 return 0; 746 } 747 748 static int uniphier_pinctrl_add_reg_region(struct device *dev, 749 struct uniphier_pinctrl_priv *priv, 750 unsigned int base, 751 unsigned int count, 752 unsigned int width) 753 { 754 struct uniphier_pinctrl_reg_region *region; 755 unsigned int nregs; 756 757 if (!count) 758 return 0; 759 760 nregs = DIV_ROUND_UP(count * width, 32); 761 762 region = devm_kzalloc(dev, struct_size(region, vals, nregs), 763 GFP_KERNEL); 764 if (!region) 765 return -ENOMEM; 766 767 region->base = base; 768 region->nregs = nregs; 769 770 list_add_tail(®ion->node, &priv->reg_regions); 771 772 return 0; 773 } 774 #endif 775 776 static int uniphier_pinctrl_pm_init(struct device *dev, 777 struct uniphier_pinctrl_priv *priv) 778 { 779 #ifdef CONFIG_PM_SLEEP 780 const struct uniphier_pinctrl_socdata *socdata = priv->socdata; 781 unsigned int num_drvctrl = 0; 782 unsigned int num_drv2ctrl = 0; 783 unsigned int num_drv3ctrl = 0; 784 unsigned int num_pupdctrl = 0; 785 unsigned int num_iectrl = 0; 786 unsigned int iectrl, drvctrl, pupdctrl; 787 enum uniphier_pin_drv_type drv_type; 788 enum uniphier_pin_pull_dir pull_dir; 789 int i, ret; 790 791 for (i = 0; i < socdata->npins; i++) { 792 void *drv_data = socdata->pins[i].drv_data; 793 794 drvctrl = uniphier_pin_get_drvctrl(drv_data); 795 drv_type = uniphier_pin_get_drv_type(drv_data); 796 pupdctrl = uniphier_pin_get_pupdctrl(drv_data); 797 pull_dir = uniphier_pin_get_pull_dir(drv_data); 798 iectrl = uniphier_pin_get_iectrl(drv_data); 799 800 switch (drv_type) { 801 case UNIPHIER_PIN_DRV_1BIT: 802 num_drvctrl = max(num_drvctrl, drvctrl + 1); 803 break; 804 case UNIPHIER_PIN_DRV_2BIT: 805 num_drv2ctrl = max(num_drv2ctrl, drvctrl + 1); 806 break; 807 case UNIPHIER_PIN_DRV_3BIT: 808 num_drv3ctrl = max(num_drv3ctrl, drvctrl + 1); 809 break; 810 default: 811 break; 812 } 813 814 if (pull_dir == UNIPHIER_PIN_PULL_UP || 815 pull_dir == UNIPHIER_PIN_PULL_DOWN) 816 num_pupdctrl = max(num_pupdctrl, pupdctrl + 1); 817 818 if (iectrl != UNIPHIER_PIN_IECTRL_NONE) { 819 if (socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) 820 iectrl = i; 821 num_iectrl = max(num_iectrl, iectrl + 1); 822 } 823 } 824 825 INIT_LIST_HEAD(&priv->reg_regions); 826 827 ret = uniphier_pinctrl_add_reg_region(dev, priv, 828 UNIPHIER_PINCTRL_PINMUX_BASE, 829 socdata->npins, 8); 830 if (ret) 831 return ret; 832 833 ret = uniphier_pinctrl_add_reg_region(dev, priv, 834 UNIPHIER_PINCTRL_DRVCTRL_BASE, 835 num_drvctrl, 1); 836 if (ret) 837 return ret; 838 839 ret = uniphier_pinctrl_add_reg_region(dev, priv, 840 UNIPHIER_PINCTRL_DRV2CTRL_BASE, 841 num_drv2ctrl, 2); 842 if (ret) 843 return ret; 844 845 ret = uniphier_pinctrl_add_reg_region(dev, priv, 846 UNIPHIER_PINCTRL_DRV3CTRL_BASE, 847 num_drv3ctrl, 3); 848 if (ret) 849 return ret; 850 851 ret = uniphier_pinctrl_add_reg_region(dev, priv, 852 UNIPHIER_PINCTRL_PUPDCTRL_BASE, 853 num_pupdctrl, 1); 854 if (ret) 855 return ret; 856 857 ret = uniphier_pinctrl_add_reg_region(dev, priv, 858 UNIPHIER_PINCTRL_IECTRL_BASE, 859 num_iectrl, 1); 860 if (ret) 861 return ret; 862 #endif 863 return 0; 864 } 865 866 const struct dev_pm_ops uniphier_pinctrl_pm_ops = { 867 SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_pinctrl_suspend, 868 uniphier_pinctrl_resume) 869 }; 870 871 int uniphier_pinctrl_probe(struct platform_device *pdev, 872 struct uniphier_pinctrl_socdata *socdata) 873 { 874 struct device *dev = &pdev->dev; 875 struct uniphier_pinctrl_priv *priv; 876 struct device_node *parent; 877 int ret; 878 879 if (!socdata || 880 !socdata->pins || !socdata->npins || 881 !socdata->groups || !socdata->groups_count || 882 !socdata->functions || !socdata->functions_count) { 883 dev_err(dev, "pinctrl socdata lacks necessary members\n"); 884 return -EINVAL; 885 } 886 887 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 888 if (!priv) 889 return -ENOMEM; 890 891 parent = of_get_parent(dev->of_node); 892 priv->regmap = syscon_node_to_regmap(parent); 893 of_node_put(parent); 894 895 if (IS_ERR(priv->regmap)) { 896 dev_err(dev, "failed to get regmap\n"); 897 return PTR_ERR(priv->regmap); 898 } 899 900 priv->socdata = socdata; 901 priv->pctldesc.name = dev->driver->name; 902 priv->pctldesc.pins = socdata->pins; 903 priv->pctldesc.npins = socdata->npins; 904 priv->pctldesc.pctlops = &uniphier_pctlops; 905 priv->pctldesc.pmxops = &uniphier_pmxops; 906 priv->pctldesc.confops = &uniphier_confops; 907 priv->pctldesc.owner = dev->driver->owner; 908 909 ret = uniphier_pinctrl_pm_init(dev, priv); 910 if (ret) 911 return ret; 912 913 priv->pctldev = devm_pinctrl_register(dev, &priv->pctldesc, priv); 914 if (IS_ERR(priv->pctldev)) { 915 dev_err(dev, "failed to register UniPhier pinctrl driver\n"); 916 return PTR_ERR(priv->pctldev); 917 } 918 919 platform_set_drvdata(pdev, priv); 920 921 return 0; 922 } 923