1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Pinctrl data for the NVIDIA Tegra30 pinmux
4  *
5  * Author: Stephen Warren <swarren@nvidia.com>
6  *
7  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
8  */
9 
10 #include <linux/init.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/pinctrl/pinctrl.h>
14 #include <linux/pinctrl/pinmux.h>
15 
16 #include "pinctrl-tegra.h"
17 
18 /*
19  * Most pins affected by the pinmux can also be GPIOs. Define these first.
20  * These must match how the GPIO driver names/numbers its pins.
21  */
22 #define _GPIO(offset)			(offset)
23 
24 #define TEGRA_PIN_CLK_32K_OUT_PA0	_GPIO(0)
25 #define TEGRA_PIN_UART3_CTS_N_PA1	_GPIO(1)
26 #define TEGRA_PIN_DAP2_FS_PA2		_GPIO(2)
27 #define TEGRA_PIN_DAP2_SCLK_PA3		_GPIO(3)
28 #define TEGRA_PIN_DAP2_DIN_PA4		_GPIO(4)
29 #define TEGRA_PIN_DAP2_DOUT_PA5		_GPIO(5)
30 #define TEGRA_PIN_SDMMC3_CLK_PA6	_GPIO(6)
31 #define TEGRA_PIN_SDMMC3_CMD_PA7	_GPIO(7)
32 #define TEGRA_PIN_GMI_A17_PB0		_GPIO(8)
33 #define TEGRA_PIN_GMI_A18_PB1		_GPIO(9)
34 #define TEGRA_PIN_LCD_PWR0_PB2		_GPIO(10)
35 #define TEGRA_PIN_LCD_PCLK_PB3		_GPIO(11)
36 #define TEGRA_PIN_SDMMC3_DAT3_PB4	_GPIO(12)
37 #define TEGRA_PIN_SDMMC3_DAT2_PB5	_GPIO(13)
38 #define TEGRA_PIN_SDMMC3_DAT1_PB6	_GPIO(14)
39 #define TEGRA_PIN_SDMMC3_DAT0_PB7	_GPIO(15)
40 #define TEGRA_PIN_UART3_RTS_N_PC0	_GPIO(16)
41 #define TEGRA_PIN_LCD_PWR1_PC1		_GPIO(17)
42 #define TEGRA_PIN_UART2_TXD_PC2		_GPIO(18)
43 #define TEGRA_PIN_UART2_RXD_PC3		_GPIO(19)
44 #define TEGRA_PIN_GEN1_I2C_SCL_PC4	_GPIO(20)
45 #define TEGRA_PIN_GEN1_I2C_SDA_PC5	_GPIO(21)
46 #define TEGRA_PIN_LCD_PWR2_PC6		_GPIO(22)
47 #define TEGRA_PIN_GMI_WP_N_PC7		_GPIO(23)
48 #define TEGRA_PIN_SDMMC3_DAT5_PD0	_GPIO(24)
49 #define TEGRA_PIN_SDMMC3_DAT4_PD1	_GPIO(25)
50 #define TEGRA_PIN_LCD_DC1_PD2		_GPIO(26)
51 #define TEGRA_PIN_SDMMC3_DAT6_PD3	_GPIO(27)
52 #define TEGRA_PIN_SDMMC3_DAT7_PD4	_GPIO(28)
53 #define TEGRA_PIN_VI_D1_PD5		_GPIO(29)
54 #define TEGRA_PIN_VI_VSYNC_PD6		_GPIO(30)
55 #define TEGRA_PIN_VI_HSYNC_PD7		_GPIO(31)
56 #define TEGRA_PIN_LCD_D0_PE0		_GPIO(32)
57 #define TEGRA_PIN_LCD_D1_PE1		_GPIO(33)
58 #define TEGRA_PIN_LCD_D2_PE2		_GPIO(34)
59 #define TEGRA_PIN_LCD_D3_PE3		_GPIO(35)
60 #define TEGRA_PIN_LCD_D4_PE4		_GPIO(36)
61 #define TEGRA_PIN_LCD_D5_PE5		_GPIO(37)
62 #define TEGRA_PIN_LCD_D6_PE6		_GPIO(38)
63 #define TEGRA_PIN_LCD_D7_PE7		_GPIO(39)
64 #define TEGRA_PIN_LCD_D8_PF0		_GPIO(40)
65 #define TEGRA_PIN_LCD_D9_PF1		_GPIO(41)
66 #define TEGRA_PIN_LCD_D10_PF2		_GPIO(42)
67 #define TEGRA_PIN_LCD_D11_PF3		_GPIO(43)
68 #define TEGRA_PIN_LCD_D12_PF4		_GPIO(44)
69 #define TEGRA_PIN_LCD_D13_PF5		_GPIO(45)
70 #define TEGRA_PIN_LCD_D14_PF6		_GPIO(46)
71 #define TEGRA_PIN_LCD_D15_PF7		_GPIO(47)
72 #define TEGRA_PIN_GMI_AD0_PG0		_GPIO(48)
73 #define TEGRA_PIN_GMI_AD1_PG1		_GPIO(49)
74 #define TEGRA_PIN_GMI_AD2_PG2		_GPIO(50)
75 #define TEGRA_PIN_GMI_AD3_PG3		_GPIO(51)
76 #define TEGRA_PIN_GMI_AD4_PG4		_GPIO(52)
77 #define TEGRA_PIN_GMI_AD5_PG5		_GPIO(53)
78 #define TEGRA_PIN_GMI_AD6_PG6		_GPIO(54)
79 #define TEGRA_PIN_GMI_AD7_PG7		_GPIO(55)
80 #define TEGRA_PIN_GMI_AD8_PH0		_GPIO(56)
81 #define TEGRA_PIN_GMI_AD9_PH1		_GPIO(57)
82 #define TEGRA_PIN_GMI_AD10_PH2		_GPIO(58)
83 #define TEGRA_PIN_GMI_AD11_PH3		_GPIO(59)
84 #define TEGRA_PIN_GMI_AD12_PH4		_GPIO(60)
85 #define TEGRA_PIN_GMI_AD13_PH5		_GPIO(61)
86 #define TEGRA_PIN_GMI_AD14_PH6		_GPIO(62)
87 #define TEGRA_PIN_GMI_AD15_PH7		_GPIO(63)
88 #define TEGRA_PIN_GMI_WR_N_PI0		_GPIO(64)
89 #define TEGRA_PIN_GMI_OE_N_PI1		_GPIO(65)
90 #define TEGRA_PIN_GMI_DQS_PI2		_GPIO(66)
91 #define TEGRA_PIN_GMI_CS6_N_PI3		_GPIO(67)
92 #define TEGRA_PIN_GMI_RST_N_PI4		_GPIO(68)
93 #define TEGRA_PIN_GMI_IORDY_PI5		_GPIO(69)
94 #define TEGRA_PIN_GMI_CS7_N_PI6		_GPIO(70)
95 #define TEGRA_PIN_GMI_WAIT_PI7		_GPIO(71)
96 #define TEGRA_PIN_GMI_CS0_N_PJ0		_GPIO(72)
97 #define TEGRA_PIN_LCD_DE_PJ1		_GPIO(73)
98 #define TEGRA_PIN_GMI_CS1_N_PJ2		_GPIO(74)
99 #define TEGRA_PIN_LCD_HSYNC_PJ3		_GPIO(75)
100 #define TEGRA_PIN_LCD_VSYNC_PJ4		_GPIO(76)
101 #define TEGRA_PIN_UART2_CTS_N_PJ5	_GPIO(77)
102 #define TEGRA_PIN_UART2_RTS_N_PJ6	_GPIO(78)
103 #define TEGRA_PIN_GMI_A16_PJ7		_GPIO(79)
104 #define TEGRA_PIN_GMI_ADV_N_PK0		_GPIO(80)
105 #define TEGRA_PIN_GMI_CLK_PK1		_GPIO(81)
106 #define TEGRA_PIN_GMI_CS4_N_PK2		_GPIO(82)
107 #define TEGRA_PIN_GMI_CS2_N_PK3		_GPIO(83)
108 #define TEGRA_PIN_GMI_CS3_N_PK4		_GPIO(84)
109 #define TEGRA_PIN_SPDIF_OUT_PK5		_GPIO(85)
110 #define TEGRA_PIN_SPDIF_IN_PK6		_GPIO(86)
111 #define TEGRA_PIN_GMI_A19_PK7		_GPIO(87)
112 #define TEGRA_PIN_VI_D2_PL0		_GPIO(88)
113 #define TEGRA_PIN_VI_D3_PL1		_GPIO(89)
114 #define TEGRA_PIN_VI_D4_PL2		_GPIO(90)
115 #define TEGRA_PIN_VI_D5_PL3		_GPIO(91)
116 #define TEGRA_PIN_VI_D6_PL4		_GPIO(92)
117 #define TEGRA_PIN_VI_D7_PL5		_GPIO(93)
118 #define TEGRA_PIN_VI_D8_PL6		_GPIO(94)
119 #define TEGRA_PIN_VI_D9_PL7		_GPIO(95)
120 #define TEGRA_PIN_LCD_D16_PM0		_GPIO(96)
121 #define TEGRA_PIN_LCD_D17_PM1		_GPIO(97)
122 #define TEGRA_PIN_LCD_D18_PM2		_GPIO(98)
123 #define TEGRA_PIN_LCD_D19_PM3		_GPIO(99)
124 #define TEGRA_PIN_LCD_D20_PM4		_GPIO(100)
125 #define TEGRA_PIN_LCD_D21_PM5		_GPIO(101)
126 #define TEGRA_PIN_LCD_D22_PM6		_GPIO(102)
127 #define TEGRA_PIN_LCD_D23_PM7		_GPIO(103)
128 #define TEGRA_PIN_DAP1_FS_PN0		_GPIO(104)
129 #define TEGRA_PIN_DAP1_DIN_PN1		_GPIO(105)
130 #define TEGRA_PIN_DAP1_DOUT_PN2		_GPIO(106)
131 #define TEGRA_PIN_DAP1_SCLK_PN3		_GPIO(107)
132 #define TEGRA_PIN_LCD_CS0_N_PN4		_GPIO(108)
133 #define TEGRA_PIN_LCD_SDOUT_PN5		_GPIO(109)
134 #define TEGRA_PIN_LCD_DC0_PN6		_GPIO(110)
135 #define TEGRA_PIN_HDMI_INT_PN7		_GPIO(111)
136 #define TEGRA_PIN_ULPI_DATA7_PO0	_GPIO(112)
137 #define TEGRA_PIN_ULPI_DATA0_PO1	_GPIO(113)
138 #define TEGRA_PIN_ULPI_DATA1_PO2	_GPIO(114)
139 #define TEGRA_PIN_ULPI_DATA2_PO3	_GPIO(115)
140 #define TEGRA_PIN_ULPI_DATA3_PO4	_GPIO(116)
141 #define TEGRA_PIN_ULPI_DATA4_PO5	_GPIO(117)
142 #define TEGRA_PIN_ULPI_DATA5_PO6	_GPIO(118)
143 #define TEGRA_PIN_ULPI_DATA6_PO7	_GPIO(119)
144 #define TEGRA_PIN_DAP3_FS_PP0		_GPIO(120)
145 #define TEGRA_PIN_DAP3_DIN_PP1		_GPIO(121)
146 #define TEGRA_PIN_DAP3_DOUT_PP2		_GPIO(122)
147 #define TEGRA_PIN_DAP3_SCLK_PP3		_GPIO(123)
148 #define TEGRA_PIN_DAP4_FS_PP4		_GPIO(124)
149 #define TEGRA_PIN_DAP4_DIN_PP5		_GPIO(125)
150 #define TEGRA_PIN_DAP4_DOUT_PP6		_GPIO(126)
151 #define TEGRA_PIN_DAP4_SCLK_PP7		_GPIO(127)
152 #define TEGRA_PIN_KB_COL0_PQ0		_GPIO(128)
153 #define TEGRA_PIN_KB_COL1_PQ1		_GPIO(129)
154 #define TEGRA_PIN_KB_COL2_PQ2		_GPIO(130)
155 #define TEGRA_PIN_KB_COL3_PQ3		_GPIO(131)
156 #define TEGRA_PIN_KB_COL4_PQ4		_GPIO(132)
157 #define TEGRA_PIN_KB_COL5_PQ5		_GPIO(133)
158 #define TEGRA_PIN_KB_COL6_PQ6		_GPIO(134)
159 #define TEGRA_PIN_KB_COL7_PQ7		_GPIO(135)
160 #define TEGRA_PIN_KB_ROW0_PR0		_GPIO(136)
161 #define TEGRA_PIN_KB_ROW1_PR1		_GPIO(137)
162 #define TEGRA_PIN_KB_ROW2_PR2		_GPIO(138)
163 #define TEGRA_PIN_KB_ROW3_PR3		_GPIO(139)
164 #define TEGRA_PIN_KB_ROW4_PR4		_GPIO(140)
165 #define TEGRA_PIN_KB_ROW5_PR5		_GPIO(141)
166 #define TEGRA_PIN_KB_ROW6_PR6		_GPIO(142)
167 #define TEGRA_PIN_KB_ROW7_PR7		_GPIO(143)
168 #define TEGRA_PIN_KB_ROW8_PS0		_GPIO(144)
169 #define TEGRA_PIN_KB_ROW9_PS1		_GPIO(145)
170 #define TEGRA_PIN_KB_ROW10_PS2		_GPIO(146)
171 #define TEGRA_PIN_KB_ROW11_PS3		_GPIO(147)
172 #define TEGRA_PIN_KB_ROW12_PS4		_GPIO(148)
173 #define TEGRA_PIN_KB_ROW13_PS5		_GPIO(149)
174 #define TEGRA_PIN_KB_ROW14_PS6		_GPIO(150)
175 #define TEGRA_PIN_KB_ROW15_PS7		_GPIO(151)
176 #define TEGRA_PIN_VI_PCLK_PT0		_GPIO(152)
177 #define TEGRA_PIN_VI_MCLK_PT1		_GPIO(153)
178 #define TEGRA_PIN_VI_D10_PT2		_GPIO(154)
179 #define TEGRA_PIN_VI_D11_PT3		_GPIO(155)
180 #define TEGRA_PIN_VI_D0_PT4		_GPIO(156)
181 #define TEGRA_PIN_GEN2_I2C_SCL_PT5	_GPIO(157)
182 #define TEGRA_PIN_GEN2_I2C_SDA_PT6	_GPIO(158)
183 #define TEGRA_PIN_SDMMC4_CMD_PT7	_GPIO(159)
184 #define TEGRA_PIN_PU0			_GPIO(160)
185 #define TEGRA_PIN_PU1			_GPIO(161)
186 #define TEGRA_PIN_PU2			_GPIO(162)
187 #define TEGRA_PIN_PU3			_GPIO(163)
188 #define TEGRA_PIN_PU4			_GPIO(164)
189 #define TEGRA_PIN_PU5			_GPIO(165)
190 #define TEGRA_PIN_PU6			_GPIO(166)
191 #define TEGRA_PIN_JTAG_RTCK_PU7		_GPIO(167)
192 #define TEGRA_PIN_PV0			_GPIO(168)
193 #define TEGRA_PIN_PV1			_GPIO(169)
194 #define TEGRA_PIN_PV2			_GPIO(170)
195 #define TEGRA_PIN_PV3			_GPIO(171)
196 #define TEGRA_PIN_DDC_SCL_PV4		_GPIO(172)
197 #define TEGRA_PIN_DDC_SDA_PV5		_GPIO(173)
198 #define TEGRA_PIN_CRT_HSYNC_PV6		_GPIO(174)
199 #define TEGRA_PIN_CRT_VSYNC_PV7		_GPIO(175)
200 #define TEGRA_PIN_LCD_CS1_N_PW0		_GPIO(176)
201 #define TEGRA_PIN_LCD_M1_PW1		_GPIO(177)
202 #define TEGRA_PIN_SPI2_CS1_N_PW2	_GPIO(178)
203 #define TEGRA_PIN_SPI2_CS2_N_PW3	_GPIO(179)
204 #define TEGRA_PIN_CLK1_OUT_PW4		_GPIO(180)
205 #define TEGRA_PIN_CLK2_OUT_PW5		_GPIO(181)
206 #define TEGRA_PIN_UART3_TXD_PW6		_GPIO(182)
207 #define TEGRA_PIN_UART3_RXD_PW7		_GPIO(183)
208 #define TEGRA_PIN_SPI2_MOSI_PX0		_GPIO(184)
209 #define TEGRA_PIN_SPI2_MISO_PX1		_GPIO(185)
210 #define TEGRA_PIN_SPI2_SCK_PX2		_GPIO(186)
211 #define TEGRA_PIN_SPI2_CS0_N_PX3	_GPIO(187)
212 #define TEGRA_PIN_SPI1_MOSI_PX4		_GPIO(188)
213 #define TEGRA_PIN_SPI1_SCK_PX5		_GPIO(189)
214 #define TEGRA_PIN_SPI1_CS0_N_PX6	_GPIO(190)
215 #define TEGRA_PIN_SPI1_MISO_PX7		_GPIO(191)
216 #define TEGRA_PIN_ULPI_CLK_PY0		_GPIO(192)
217 #define TEGRA_PIN_ULPI_DIR_PY1		_GPIO(193)
218 #define TEGRA_PIN_ULPI_NXT_PY2		_GPIO(194)
219 #define TEGRA_PIN_ULPI_STP_PY3		_GPIO(195)
220 #define TEGRA_PIN_SDMMC1_DAT3_PY4	_GPIO(196)
221 #define TEGRA_PIN_SDMMC1_DAT2_PY5	_GPIO(197)
222 #define TEGRA_PIN_SDMMC1_DAT1_PY6	_GPIO(198)
223 #define TEGRA_PIN_SDMMC1_DAT0_PY7	_GPIO(199)
224 #define TEGRA_PIN_SDMMC1_CLK_PZ0	_GPIO(200)
225 #define TEGRA_PIN_SDMMC1_CMD_PZ1	_GPIO(201)
226 #define TEGRA_PIN_LCD_SDIN_PZ2		_GPIO(202)
227 #define TEGRA_PIN_LCD_WR_N_PZ3		_GPIO(203)
228 #define TEGRA_PIN_LCD_SCK_PZ4		_GPIO(204)
229 #define TEGRA_PIN_SYS_CLK_REQ_PZ5	_GPIO(205)
230 #define TEGRA_PIN_PWR_I2C_SCL_PZ6	_GPIO(206)
231 #define TEGRA_PIN_PWR_I2C_SDA_PZ7	_GPIO(207)
232 #define TEGRA_PIN_SDMMC4_DAT0_PAA0	_GPIO(208)
233 #define TEGRA_PIN_SDMMC4_DAT1_PAA1	_GPIO(209)
234 #define TEGRA_PIN_SDMMC4_DAT2_PAA2	_GPIO(210)
235 #define TEGRA_PIN_SDMMC4_DAT3_PAA3	_GPIO(211)
236 #define TEGRA_PIN_SDMMC4_DAT4_PAA4	_GPIO(212)
237 #define TEGRA_PIN_SDMMC4_DAT5_PAA5	_GPIO(213)
238 #define TEGRA_PIN_SDMMC4_DAT6_PAA6	_GPIO(214)
239 #define TEGRA_PIN_SDMMC4_DAT7_PAA7	_GPIO(215)
240 #define TEGRA_PIN_PBB0			_GPIO(216)
241 #define TEGRA_PIN_CAM_I2C_SCL_PBB1	_GPIO(217)
242 #define TEGRA_PIN_CAM_I2C_SDA_PBB2	_GPIO(218)
243 #define TEGRA_PIN_PBB3			_GPIO(219)
244 #define TEGRA_PIN_PBB4			_GPIO(220)
245 #define TEGRA_PIN_PBB5			_GPIO(221)
246 #define TEGRA_PIN_PBB6			_GPIO(222)
247 #define TEGRA_PIN_PBB7			_GPIO(223)
248 #define TEGRA_PIN_CAM_MCLK_PCC0		_GPIO(224)
249 #define TEGRA_PIN_PCC1			_GPIO(225)
250 #define TEGRA_PIN_PCC2			_GPIO(226)
251 #define TEGRA_PIN_SDMMC4_RST_N_PCC3	_GPIO(227)
252 #define TEGRA_PIN_SDMMC4_CLK_PCC4	_GPIO(228)
253 #define TEGRA_PIN_CLK2_REQ_PCC5		_GPIO(229)
254 #define TEGRA_PIN_PEX_L2_RST_N_PCC6	_GPIO(230)
255 #define TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7	_GPIO(231)
256 #define TEGRA_PIN_PEX_L0_PRSNT_N_PDD0	_GPIO(232)
257 #define TEGRA_PIN_PEX_L0_RST_N_PDD1	_GPIO(233)
258 #define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2	_GPIO(234)
259 #define TEGRA_PIN_PEX_WAKE_N_PDD3	_GPIO(235)
260 #define TEGRA_PIN_PEX_L1_PRSNT_N_PDD4	_GPIO(236)
261 #define TEGRA_PIN_PEX_L1_RST_N_PDD5	_GPIO(237)
262 #define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6	_GPIO(238)
263 #define TEGRA_PIN_PEX_L2_PRSNT_N_PDD7	_GPIO(239)
264 #define TEGRA_PIN_CLK3_OUT_PEE0		_GPIO(240)
265 #define TEGRA_PIN_CLK3_REQ_PEE1		_GPIO(241)
266 #define TEGRA_PIN_CLK1_REQ_PEE2		_GPIO(242)
267 #define TEGRA_PIN_HDMI_CEC_PEE3		_GPIO(243)
268 #define TEGRA_PIN_PEE4			_GPIO(244)
269 #define TEGRA_PIN_PEE5			_GPIO(245)
270 #define TEGRA_PIN_PEE6			_GPIO(246)
271 #define TEGRA_PIN_PEE7			_GPIO(247)
272 
273 /* All non-GPIO pins follow */
274 #define NUM_GPIOS			(TEGRA_PIN_PEE7 + 1)
275 #define _PIN(offset)			(NUM_GPIOS + (offset))
276 
277 /* Non-GPIO pins */
278 #define TEGRA_PIN_CLK_32K_IN		_PIN(0)
279 #define TEGRA_PIN_CORE_PWR_REQ		_PIN(1)
280 #define TEGRA_PIN_CPU_PWR_REQ		_PIN(2)
281 #define TEGRA_PIN_JTAG_TCK		_PIN(3)
282 #define TEGRA_PIN_JTAG_TDI		_PIN(4)
283 #define TEGRA_PIN_JTAG_TDO		_PIN(5)
284 #define TEGRA_PIN_JTAG_TMS		_PIN(6)
285 #define TEGRA_PIN_JTAG_TRST_N		_PIN(7)
286 #define TEGRA_PIN_OWR			_PIN(8)
287 #define TEGRA_PIN_PWR_INT_N		_PIN(9)
288 #define TEGRA_PIN_SYS_RESET_N		_PIN(10)
289 #define TEGRA_PIN_TEST_MODE_EN		_PIN(11)
290 
291 static const struct pinctrl_pin_desc tegra30_pins[] = {
292 	PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
293 	PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
294 	PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
295 	PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
296 	PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
297 	PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
298 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
299 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
300 	PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
301 	PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
302 	PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
303 	PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
304 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
305 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
306 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
307 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
308 	PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
309 	PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
310 	PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
311 	PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
312 	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
313 	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
314 	PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
315 	PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
316 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT5_PD0, "SDMMC3_DAT5 PD0"),
317 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, "SDMMC3_DAT4 PD1"),
318 	PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, "LCD_DC1 PD2"),
319 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, "SDMMC3_DAT6 PD3"),
320 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, "SDMMC3_DAT7 PD4"),
321 	PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
322 	PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
323 	PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
324 	PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
325 	PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
326 	PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
327 	PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
328 	PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
329 	PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
330 	PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
331 	PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
332 	PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
333 	PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
334 	PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
335 	PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
336 	PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
337 	PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
338 	PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
339 	PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
340 	PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
341 	PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
342 	PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
343 	PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
344 	PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
345 	PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
346 	PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
347 	PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
348 	PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
349 	PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
350 	PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
351 	PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
352 	PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
353 	PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
354 	PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
355 	PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
356 	PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
357 	PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
358 	PINCTRL_PIN(TEGRA_PIN_GMI_DQS_PI2, "GMI_DQS PI2"),
359 	PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
360 	PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
361 	PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
362 	PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
363 	PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
364 	PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
365 	PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
366 	PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
367 	PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
368 	PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
369 	PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
370 	PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
371 	PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
372 	PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
373 	PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
374 	PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
375 	PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
376 	PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
377 	PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
378 	PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
379 	PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
380 	PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
381 	PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
382 	PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
383 	PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
384 	PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
385 	PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
386 	PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
387 	PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
388 	PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
389 	PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
390 	PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
391 	PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
392 	PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
393 	PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
394 	PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
395 	PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
396 	PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
397 	PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
398 	PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
399 	PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
400 	PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
401 	PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
402 	PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
403 	PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
404 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
405 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
406 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
407 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
408 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
409 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
410 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
411 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
412 	PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
413 	PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
414 	PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
415 	PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
416 	PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
417 	PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
418 	PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
419 	PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
420 	PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
421 	PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
422 	PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
423 	PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
424 	PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
425 	PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
426 	PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
427 	PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
428 	PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
429 	PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
430 	PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
431 	PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
432 	PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
433 	PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
434 	PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
435 	PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
436 	PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
437 	PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
438 	PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
439 	PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
440 	PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
441 	PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
442 	PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
443 	PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
444 	PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
445 	PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
446 	PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VI_D10 PT2"),
447 	PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
448 	PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
449 	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
450 	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
451 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
452 	PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
453 	PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
454 	PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
455 	PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
456 	PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
457 	PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
458 	PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
459 	PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
460 	PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
461 	PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
462 	PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
463 	PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
464 	PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
465 	PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
466 	PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC_PV6, "CRT_HSYNC PV6"),
467 	PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC_PV7, "CRT_VSYNC PV7"),
468 	PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
469 	PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
470 	PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
471 	PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
472 	PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
473 	PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
474 	PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
475 	PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
476 	PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
477 	PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
478 	PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
479 	PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
480 	PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
481 	PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
482 	PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
483 	PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
484 	PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
485 	PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
486 	PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
487 	PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
488 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
489 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
490 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
491 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
492 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
493 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
494 	PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
495 	PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
496 	PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
497 	PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
498 	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
499 	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
500 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
501 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
502 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
503 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
504 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
505 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
506 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
507 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
508 	PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
509 	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
510 	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
511 	PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
512 	PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
513 	PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
514 	PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
515 	PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
516 	PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
517 	PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
518 	PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
519 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_RST_N_PCC3, "SDMMC4_RST_N PCC3"),
520 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
521 	PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
522 	PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PCC6, "PEX_L2_RST_N PCC6"),
523 	PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7, "PEX_L2_CLKREQ_N PCC7"),
524 	PINCTRL_PIN(TEGRA_PIN_PEX_L0_PRSNT_N_PDD0, "PEX_L0_PRSNT_N PDD0"),
525 	PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
526 	PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
527 	PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
528 	PINCTRL_PIN(TEGRA_PIN_PEX_L1_PRSNT_N_PDD4, "PEX_L1_PRSNT_N PDD4"),
529 	PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
530 	PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
531 	PINCTRL_PIN(TEGRA_PIN_PEX_L2_PRSNT_N_PDD7, "PEX_L2_PRSNT_N PDD7"),
532 	PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
533 	PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
534 	PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
535 	PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
536 	PINCTRL_PIN(TEGRA_PIN_PEE4, "PEE4"),
537 	PINCTRL_PIN(TEGRA_PIN_PEE5, "PEE5"),
538 	PINCTRL_PIN(TEGRA_PIN_PEE6, "PEE6"),
539 	PINCTRL_PIN(TEGRA_PIN_PEE7, "PEE7"),
540 	PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
541 	PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
542 	PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
543 	PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
544 	PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
545 	PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
546 	PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
547 	PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
548 	PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
549 	PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
550 	PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
551 	PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
552 };
553 
554 static const unsigned clk_32k_out_pa0_pins[] = {
555 	TEGRA_PIN_CLK_32K_OUT_PA0,
556 };
557 
558 static const unsigned uart3_cts_n_pa1_pins[] = {
559 	TEGRA_PIN_UART3_CTS_N_PA1,
560 };
561 
562 static const unsigned dap2_fs_pa2_pins[] = {
563 	TEGRA_PIN_DAP2_FS_PA2,
564 };
565 
566 static const unsigned dap2_sclk_pa3_pins[] = {
567 	TEGRA_PIN_DAP2_SCLK_PA3,
568 };
569 
570 static const unsigned dap2_din_pa4_pins[] = {
571 	TEGRA_PIN_DAP2_DIN_PA4,
572 };
573 
574 static const unsigned dap2_dout_pa5_pins[] = {
575 	TEGRA_PIN_DAP2_DOUT_PA5,
576 };
577 
578 static const unsigned sdmmc3_clk_pa6_pins[] = {
579 	TEGRA_PIN_SDMMC3_CLK_PA6,
580 };
581 
582 static const unsigned sdmmc3_cmd_pa7_pins[] = {
583 	TEGRA_PIN_SDMMC3_CMD_PA7,
584 };
585 
586 static const unsigned gmi_a17_pb0_pins[] = {
587 	TEGRA_PIN_GMI_A17_PB0,
588 };
589 
590 static const unsigned gmi_a18_pb1_pins[] = {
591 	TEGRA_PIN_GMI_A18_PB1,
592 };
593 
594 static const unsigned lcd_pwr0_pb2_pins[] = {
595 	TEGRA_PIN_LCD_PWR0_PB2,
596 };
597 
598 static const unsigned lcd_pclk_pb3_pins[] = {
599 	TEGRA_PIN_LCD_PCLK_PB3,
600 };
601 
602 static const unsigned sdmmc3_dat3_pb4_pins[] = {
603 	TEGRA_PIN_SDMMC3_DAT3_PB4,
604 };
605 
606 static const unsigned sdmmc3_dat2_pb5_pins[] = {
607 	TEGRA_PIN_SDMMC3_DAT2_PB5,
608 };
609 
610 static const unsigned sdmmc3_dat1_pb6_pins[] = {
611 	TEGRA_PIN_SDMMC3_DAT1_PB6,
612 };
613 
614 static const unsigned sdmmc3_dat0_pb7_pins[] = {
615 	TEGRA_PIN_SDMMC3_DAT0_PB7,
616 };
617 
618 static const unsigned uart3_rts_n_pc0_pins[] = {
619 	TEGRA_PIN_UART3_RTS_N_PC0,
620 };
621 
622 static const unsigned lcd_pwr1_pc1_pins[] = {
623 	TEGRA_PIN_LCD_PWR1_PC1,
624 };
625 
626 static const unsigned uart2_txd_pc2_pins[] = {
627 	TEGRA_PIN_UART2_TXD_PC2,
628 };
629 
630 static const unsigned uart2_rxd_pc3_pins[] = {
631 	TEGRA_PIN_UART2_RXD_PC3,
632 };
633 
634 static const unsigned gen1_i2c_scl_pc4_pins[] = {
635 	TEGRA_PIN_GEN1_I2C_SCL_PC4,
636 };
637 
638 static const unsigned gen1_i2c_sda_pc5_pins[] = {
639 	TEGRA_PIN_GEN1_I2C_SDA_PC5,
640 };
641 
642 static const unsigned lcd_pwr2_pc6_pins[] = {
643 	TEGRA_PIN_LCD_PWR2_PC6,
644 };
645 
646 static const unsigned gmi_wp_n_pc7_pins[] = {
647 	TEGRA_PIN_GMI_WP_N_PC7,
648 };
649 
650 static const unsigned sdmmc3_dat5_pd0_pins[] = {
651 	TEGRA_PIN_SDMMC3_DAT5_PD0,
652 };
653 
654 static const unsigned sdmmc3_dat4_pd1_pins[] = {
655 	TEGRA_PIN_SDMMC3_DAT4_PD1,
656 };
657 
658 static const unsigned lcd_dc1_pd2_pins[] = {
659 	TEGRA_PIN_LCD_DC1_PD2,
660 };
661 
662 static const unsigned sdmmc3_dat6_pd3_pins[] = {
663 	TEGRA_PIN_SDMMC3_DAT6_PD3,
664 };
665 
666 static const unsigned sdmmc3_dat7_pd4_pins[] = {
667 	TEGRA_PIN_SDMMC3_DAT7_PD4,
668 };
669 
670 static const unsigned vi_d1_pd5_pins[] = {
671 	TEGRA_PIN_VI_D1_PD5,
672 };
673 
674 static const unsigned vi_vsync_pd6_pins[] = {
675 	TEGRA_PIN_VI_VSYNC_PD6,
676 };
677 
678 static const unsigned vi_hsync_pd7_pins[] = {
679 	TEGRA_PIN_VI_HSYNC_PD7,
680 };
681 
682 static const unsigned lcd_d0_pe0_pins[] = {
683 	TEGRA_PIN_LCD_D0_PE0,
684 };
685 
686 static const unsigned lcd_d1_pe1_pins[] = {
687 	TEGRA_PIN_LCD_D1_PE1,
688 };
689 
690 static const unsigned lcd_d2_pe2_pins[] = {
691 	TEGRA_PIN_LCD_D2_PE2,
692 };
693 
694 static const unsigned lcd_d3_pe3_pins[] = {
695 	TEGRA_PIN_LCD_D3_PE3,
696 };
697 
698 static const unsigned lcd_d4_pe4_pins[] = {
699 	TEGRA_PIN_LCD_D4_PE4,
700 };
701 
702 static const unsigned lcd_d5_pe5_pins[] = {
703 	TEGRA_PIN_LCD_D5_PE5,
704 };
705 
706 static const unsigned lcd_d6_pe6_pins[] = {
707 	TEGRA_PIN_LCD_D6_PE6,
708 };
709 
710 static const unsigned lcd_d7_pe7_pins[] = {
711 	TEGRA_PIN_LCD_D7_PE7,
712 };
713 
714 static const unsigned lcd_d8_pf0_pins[] = {
715 	TEGRA_PIN_LCD_D8_PF0,
716 };
717 
718 static const unsigned lcd_d9_pf1_pins[] = {
719 	TEGRA_PIN_LCD_D9_PF1,
720 };
721 
722 static const unsigned lcd_d10_pf2_pins[] = {
723 	TEGRA_PIN_LCD_D10_PF2,
724 };
725 
726 static const unsigned lcd_d11_pf3_pins[] = {
727 	TEGRA_PIN_LCD_D11_PF3,
728 };
729 
730 static const unsigned lcd_d12_pf4_pins[] = {
731 	TEGRA_PIN_LCD_D12_PF4,
732 };
733 
734 static const unsigned lcd_d13_pf5_pins[] = {
735 	TEGRA_PIN_LCD_D13_PF5,
736 };
737 
738 static const unsigned lcd_d14_pf6_pins[] = {
739 	TEGRA_PIN_LCD_D14_PF6,
740 };
741 
742 static const unsigned lcd_d15_pf7_pins[] = {
743 	TEGRA_PIN_LCD_D15_PF7,
744 };
745 
746 static const unsigned gmi_ad0_pg0_pins[] = {
747 	TEGRA_PIN_GMI_AD0_PG0,
748 };
749 
750 static const unsigned gmi_ad1_pg1_pins[] = {
751 	TEGRA_PIN_GMI_AD1_PG1,
752 };
753 
754 static const unsigned gmi_ad2_pg2_pins[] = {
755 	TEGRA_PIN_GMI_AD2_PG2,
756 };
757 
758 static const unsigned gmi_ad3_pg3_pins[] = {
759 	TEGRA_PIN_GMI_AD3_PG3,
760 };
761 
762 static const unsigned gmi_ad4_pg4_pins[] = {
763 	TEGRA_PIN_GMI_AD4_PG4,
764 };
765 
766 static const unsigned gmi_ad5_pg5_pins[] = {
767 	TEGRA_PIN_GMI_AD5_PG5,
768 };
769 
770 static const unsigned gmi_ad6_pg6_pins[] = {
771 	TEGRA_PIN_GMI_AD6_PG6,
772 };
773 
774 static const unsigned gmi_ad7_pg7_pins[] = {
775 	TEGRA_PIN_GMI_AD7_PG7,
776 };
777 
778 static const unsigned gmi_ad8_ph0_pins[] = {
779 	TEGRA_PIN_GMI_AD8_PH0,
780 };
781 
782 static const unsigned gmi_ad9_ph1_pins[] = {
783 	TEGRA_PIN_GMI_AD9_PH1,
784 };
785 
786 static const unsigned gmi_ad10_ph2_pins[] = {
787 	TEGRA_PIN_GMI_AD10_PH2,
788 };
789 
790 static const unsigned gmi_ad11_ph3_pins[] = {
791 	TEGRA_PIN_GMI_AD11_PH3,
792 };
793 
794 static const unsigned gmi_ad12_ph4_pins[] = {
795 	TEGRA_PIN_GMI_AD12_PH4,
796 };
797 
798 static const unsigned gmi_ad13_ph5_pins[] = {
799 	TEGRA_PIN_GMI_AD13_PH5,
800 };
801 
802 static const unsigned gmi_ad14_ph6_pins[] = {
803 	TEGRA_PIN_GMI_AD14_PH6,
804 };
805 
806 static const unsigned gmi_ad15_ph7_pins[] = {
807 	TEGRA_PIN_GMI_AD15_PH7,
808 };
809 
810 static const unsigned gmi_wr_n_pi0_pins[] = {
811 	TEGRA_PIN_GMI_WR_N_PI0,
812 };
813 
814 static const unsigned gmi_oe_n_pi1_pins[] = {
815 	TEGRA_PIN_GMI_OE_N_PI1,
816 };
817 
818 static const unsigned gmi_dqs_pi2_pins[] = {
819 	TEGRA_PIN_GMI_DQS_PI2,
820 };
821 
822 static const unsigned gmi_cs6_n_pi3_pins[] = {
823 	TEGRA_PIN_GMI_CS6_N_PI3,
824 };
825 
826 static const unsigned gmi_rst_n_pi4_pins[] = {
827 	TEGRA_PIN_GMI_RST_N_PI4,
828 };
829 
830 static const unsigned gmi_iordy_pi5_pins[] = {
831 	TEGRA_PIN_GMI_IORDY_PI5,
832 };
833 
834 static const unsigned gmi_cs7_n_pi6_pins[] = {
835 	TEGRA_PIN_GMI_CS7_N_PI6,
836 };
837 
838 static const unsigned gmi_wait_pi7_pins[] = {
839 	TEGRA_PIN_GMI_WAIT_PI7,
840 };
841 
842 static const unsigned gmi_cs0_n_pj0_pins[] = {
843 	TEGRA_PIN_GMI_CS0_N_PJ0,
844 };
845 
846 static const unsigned lcd_de_pj1_pins[] = {
847 	TEGRA_PIN_LCD_DE_PJ1,
848 };
849 
850 static const unsigned gmi_cs1_n_pj2_pins[] = {
851 	TEGRA_PIN_GMI_CS1_N_PJ2,
852 };
853 
854 static const unsigned lcd_hsync_pj3_pins[] = {
855 	TEGRA_PIN_LCD_HSYNC_PJ3,
856 };
857 
858 static const unsigned lcd_vsync_pj4_pins[] = {
859 	TEGRA_PIN_LCD_VSYNC_PJ4,
860 };
861 
862 static const unsigned uart2_cts_n_pj5_pins[] = {
863 	TEGRA_PIN_UART2_CTS_N_PJ5,
864 };
865 
866 static const unsigned uart2_rts_n_pj6_pins[] = {
867 	TEGRA_PIN_UART2_RTS_N_PJ6,
868 };
869 
870 static const unsigned gmi_a16_pj7_pins[] = {
871 	TEGRA_PIN_GMI_A16_PJ7,
872 };
873 
874 static const unsigned gmi_adv_n_pk0_pins[] = {
875 	TEGRA_PIN_GMI_ADV_N_PK0,
876 };
877 
878 static const unsigned gmi_clk_pk1_pins[] = {
879 	TEGRA_PIN_GMI_CLK_PK1,
880 };
881 
882 static const unsigned gmi_cs4_n_pk2_pins[] = {
883 	TEGRA_PIN_GMI_CS4_N_PK2,
884 };
885 
886 static const unsigned gmi_cs2_n_pk3_pins[] = {
887 	TEGRA_PIN_GMI_CS2_N_PK3,
888 };
889 
890 static const unsigned gmi_cs3_n_pk4_pins[] = {
891 	TEGRA_PIN_GMI_CS3_N_PK4,
892 };
893 
894 static const unsigned spdif_out_pk5_pins[] = {
895 	TEGRA_PIN_SPDIF_OUT_PK5,
896 };
897 
898 static const unsigned spdif_in_pk6_pins[] = {
899 	TEGRA_PIN_SPDIF_IN_PK6,
900 };
901 
902 static const unsigned gmi_a19_pk7_pins[] = {
903 	TEGRA_PIN_GMI_A19_PK7,
904 };
905 
906 static const unsigned vi_d2_pl0_pins[] = {
907 	TEGRA_PIN_VI_D2_PL0,
908 };
909 
910 static const unsigned vi_d3_pl1_pins[] = {
911 	TEGRA_PIN_VI_D3_PL1,
912 };
913 
914 static const unsigned vi_d4_pl2_pins[] = {
915 	TEGRA_PIN_VI_D4_PL2,
916 };
917 
918 static const unsigned vi_d5_pl3_pins[] = {
919 	TEGRA_PIN_VI_D5_PL3,
920 };
921 
922 static const unsigned vi_d6_pl4_pins[] = {
923 	TEGRA_PIN_VI_D6_PL4,
924 };
925 
926 static const unsigned vi_d7_pl5_pins[] = {
927 	TEGRA_PIN_VI_D7_PL5,
928 };
929 
930 static const unsigned vi_d8_pl6_pins[] = {
931 	TEGRA_PIN_VI_D8_PL6,
932 };
933 
934 static const unsigned vi_d9_pl7_pins[] = {
935 	TEGRA_PIN_VI_D9_PL7,
936 };
937 
938 static const unsigned lcd_d16_pm0_pins[] = {
939 	TEGRA_PIN_LCD_D16_PM0,
940 };
941 
942 static const unsigned lcd_d17_pm1_pins[] = {
943 	TEGRA_PIN_LCD_D17_PM1,
944 };
945 
946 static const unsigned lcd_d18_pm2_pins[] = {
947 	TEGRA_PIN_LCD_D18_PM2,
948 };
949 
950 static const unsigned lcd_d19_pm3_pins[] = {
951 	TEGRA_PIN_LCD_D19_PM3,
952 };
953 
954 static const unsigned lcd_d20_pm4_pins[] = {
955 	TEGRA_PIN_LCD_D20_PM4,
956 };
957 
958 static const unsigned lcd_d21_pm5_pins[] = {
959 	TEGRA_PIN_LCD_D21_PM5,
960 };
961 
962 static const unsigned lcd_d22_pm6_pins[] = {
963 	TEGRA_PIN_LCD_D22_PM6,
964 };
965 
966 static const unsigned lcd_d23_pm7_pins[] = {
967 	TEGRA_PIN_LCD_D23_PM7,
968 };
969 
970 static const unsigned dap1_fs_pn0_pins[] = {
971 	TEGRA_PIN_DAP1_FS_PN0,
972 };
973 
974 static const unsigned dap1_din_pn1_pins[] = {
975 	TEGRA_PIN_DAP1_DIN_PN1,
976 };
977 
978 static const unsigned dap1_dout_pn2_pins[] = {
979 	TEGRA_PIN_DAP1_DOUT_PN2,
980 };
981 
982 static const unsigned dap1_sclk_pn3_pins[] = {
983 	TEGRA_PIN_DAP1_SCLK_PN3,
984 };
985 
986 static const unsigned lcd_cs0_n_pn4_pins[] = {
987 	TEGRA_PIN_LCD_CS0_N_PN4,
988 };
989 
990 static const unsigned lcd_sdout_pn5_pins[] = {
991 	TEGRA_PIN_LCD_SDOUT_PN5,
992 };
993 
994 static const unsigned lcd_dc0_pn6_pins[] = {
995 	TEGRA_PIN_LCD_DC0_PN6,
996 };
997 
998 static const unsigned hdmi_int_pn7_pins[] = {
999 	TEGRA_PIN_HDMI_INT_PN7,
1000 };
1001 
1002 static const unsigned ulpi_data7_po0_pins[] = {
1003 	TEGRA_PIN_ULPI_DATA7_PO0,
1004 };
1005 
1006 static const unsigned ulpi_data0_po1_pins[] = {
1007 	TEGRA_PIN_ULPI_DATA0_PO1,
1008 };
1009 
1010 static const unsigned ulpi_data1_po2_pins[] = {
1011 	TEGRA_PIN_ULPI_DATA1_PO2,
1012 };
1013 
1014 static const unsigned ulpi_data2_po3_pins[] = {
1015 	TEGRA_PIN_ULPI_DATA2_PO3,
1016 };
1017 
1018 static const unsigned ulpi_data3_po4_pins[] = {
1019 	TEGRA_PIN_ULPI_DATA3_PO4,
1020 };
1021 
1022 static const unsigned ulpi_data4_po5_pins[] = {
1023 	TEGRA_PIN_ULPI_DATA4_PO5,
1024 };
1025 
1026 static const unsigned ulpi_data5_po6_pins[] = {
1027 	TEGRA_PIN_ULPI_DATA5_PO6,
1028 };
1029 
1030 static const unsigned ulpi_data6_po7_pins[] = {
1031 	TEGRA_PIN_ULPI_DATA6_PO7,
1032 };
1033 
1034 static const unsigned dap3_fs_pp0_pins[] = {
1035 	TEGRA_PIN_DAP3_FS_PP0,
1036 };
1037 
1038 static const unsigned dap3_din_pp1_pins[] = {
1039 	TEGRA_PIN_DAP3_DIN_PP1,
1040 };
1041 
1042 static const unsigned dap3_dout_pp2_pins[] = {
1043 	TEGRA_PIN_DAP3_DOUT_PP2,
1044 };
1045 
1046 static const unsigned dap3_sclk_pp3_pins[] = {
1047 	TEGRA_PIN_DAP3_SCLK_PP3,
1048 };
1049 
1050 static const unsigned dap4_fs_pp4_pins[] = {
1051 	TEGRA_PIN_DAP4_FS_PP4,
1052 };
1053 
1054 static const unsigned dap4_din_pp5_pins[] = {
1055 	TEGRA_PIN_DAP4_DIN_PP5,
1056 };
1057 
1058 static const unsigned dap4_dout_pp6_pins[] = {
1059 	TEGRA_PIN_DAP4_DOUT_PP6,
1060 };
1061 
1062 static const unsigned dap4_sclk_pp7_pins[] = {
1063 	TEGRA_PIN_DAP4_SCLK_PP7,
1064 };
1065 
1066 static const unsigned kb_col0_pq0_pins[] = {
1067 	TEGRA_PIN_KB_COL0_PQ0,
1068 };
1069 
1070 static const unsigned kb_col1_pq1_pins[] = {
1071 	TEGRA_PIN_KB_COL1_PQ1,
1072 };
1073 
1074 static const unsigned kb_col2_pq2_pins[] = {
1075 	TEGRA_PIN_KB_COL2_PQ2,
1076 };
1077 
1078 static const unsigned kb_col3_pq3_pins[] = {
1079 	TEGRA_PIN_KB_COL3_PQ3,
1080 };
1081 
1082 static const unsigned kb_col4_pq4_pins[] = {
1083 	TEGRA_PIN_KB_COL4_PQ4,
1084 };
1085 
1086 static const unsigned kb_col5_pq5_pins[] = {
1087 	TEGRA_PIN_KB_COL5_PQ5,
1088 };
1089 
1090 static const unsigned kb_col6_pq6_pins[] = {
1091 	TEGRA_PIN_KB_COL6_PQ6,
1092 };
1093 
1094 static const unsigned kb_col7_pq7_pins[] = {
1095 	TEGRA_PIN_KB_COL7_PQ7,
1096 };
1097 
1098 static const unsigned kb_row0_pr0_pins[] = {
1099 	TEGRA_PIN_KB_ROW0_PR0,
1100 };
1101 
1102 static const unsigned kb_row1_pr1_pins[] = {
1103 	TEGRA_PIN_KB_ROW1_PR1,
1104 };
1105 
1106 static const unsigned kb_row2_pr2_pins[] = {
1107 	TEGRA_PIN_KB_ROW2_PR2,
1108 };
1109 
1110 static const unsigned kb_row3_pr3_pins[] = {
1111 	TEGRA_PIN_KB_ROW3_PR3,
1112 };
1113 
1114 static const unsigned kb_row4_pr4_pins[] = {
1115 	TEGRA_PIN_KB_ROW4_PR4,
1116 };
1117 
1118 static const unsigned kb_row5_pr5_pins[] = {
1119 	TEGRA_PIN_KB_ROW5_PR5,
1120 };
1121 
1122 static const unsigned kb_row6_pr6_pins[] = {
1123 	TEGRA_PIN_KB_ROW6_PR6,
1124 };
1125 
1126 static const unsigned kb_row7_pr7_pins[] = {
1127 	TEGRA_PIN_KB_ROW7_PR7,
1128 };
1129 
1130 static const unsigned kb_row8_ps0_pins[] = {
1131 	TEGRA_PIN_KB_ROW8_PS0,
1132 };
1133 
1134 static const unsigned kb_row9_ps1_pins[] = {
1135 	TEGRA_PIN_KB_ROW9_PS1,
1136 };
1137 
1138 static const unsigned kb_row10_ps2_pins[] = {
1139 	TEGRA_PIN_KB_ROW10_PS2,
1140 };
1141 
1142 static const unsigned kb_row11_ps3_pins[] = {
1143 	TEGRA_PIN_KB_ROW11_PS3,
1144 };
1145 
1146 static const unsigned kb_row12_ps4_pins[] = {
1147 	TEGRA_PIN_KB_ROW12_PS4,
1148 };
1149 
1150 static const unsigned kb_row13_ps5_pins[] = {
1151 	TEGRA_PIN_KB_ROW13_PS5,
1152 };
1153 
1154 static const unsigned kb_row14_ps6_pins[] = {
1155 	TEGRA_PIN_KB_ROW14_PS6,
1156 };
1157 
1158 static const unsigned kb_row15_ps7_pins[] = {
1159 	TEGRA_PIN_KB_ROW15_PS7,
1160 };
1161 
1162 static const unsigned vi_pclk_pt0_pins[] = {
1163 	TEGRA_PIN_VI_PCLK_PT0,
1164 };
1165 
1166 static const unsigned vi_mclk_pt1_pins[] = {
1167 	TEGRA_PIN_VI_MCLK_PT1,
1168 };
1169 
1170 static const unsigned vi_d10_pt2_pins[] = {
1171 	TEGRA_PIN_VI_D10_PT2,
1172 };
1173 
1174 static const unsigned vi_d11_pt3_pins[] = {
1175 	TEGRA_PIN_VI_D11_PT3,
1176 };
1177 
1178 static const unsigned vi_d0_pt4_pins[] = {
1179 	TEGRA_PIN_VI_D0_PT4,
1180 };
1181 
1182 static const unsigned gen2_i2c_scl_pt5_pins[] = {
1183 	TEGRA_PIN_GEN2_I2C_SCL_PT5,
1184 };
1185 
1186 static const unsigned gen2_i2c_sda_pt6_pins[] = {
1187 	TEGRA_PIN_GEN2_I2C_SDA_PT6,
1188 };
1189 
1190 static const unsigned sdmmc4_cmd_pt7_pins[] = {
1191 	TEGRA_PIN_SDMMC4_CMD_PT7,
1192 };
1193 
1194 static const unsigned pu0_pins[] = {
1195 	TEGRA_PIN_PU0,
1196 };
1197 
1198 static const unsigned pu1_pins[] = {
1199 	TEGRA_PIN_PU1,
1200 };
1201 
1202 static const unsigned pu2_pins[] = {
1203 	TEGRA_PIN_PU2,
1204 };
1205 
1206 static const unsigned pu3_pins[] = {
1207 	TEGRA_PIN_PU3,
1208 };
1209 
1210 static const unsigned pu4_pins[] = {
1211 	TEGRA_PIN_PU4,
1212 };
1213 
1214 static const unsigned pu5_pins[] = {
1215 	TEGRA_PIN_PU5,
1216 };
1217 
1218 static const unsigned pu6_pins[] = {
1219 	TEGRA_PIN_PU6,
1220 };
1221 
1222 static const unsigned jtag_rtck_pu7_pins[] = {
1223 	TEGRA_PIN_JTAG_RTCK_PU7,
1224 };
1225 
1226 static const unsigned pv0_pins[] = {
1227 	TEGRA_PIN_PV0,
1228 };
1229 
1230 static const unsigned pv1_pins[] = {
1231 	TEGRA_PIN_PV1,
1232 };
1233 
1234 static const unsigned pv2_pins[] = {
1235 	TEGRA_PIN_PV2,
1236 };
1237 
1238 static const unsigned pv3_pins[] = {
1239 	TEGRA_PIN_PV3,
1240 };
1241 
1242 static const unsigned ddc_scl_pv4_pins[] = {
1243 	TEGRA_PIN_DDC_SCL_PV4,
1244 };
1245 
1246 static const unsigned ddc_sda_pv5_pins[] = {
1247 	TEGRA_PIN_DDC_SDA_PV5,
1248 };
1249 
1250 static const unsigned crt_hsync_pv6_pins[] = {
1251 	TEGRA_PIN_CRT_HSYNC_PV6,
1252 };
1253 
1254 static const unsigned crt_vsync_pv7_pins[] = {
1255 	TEGRA_PIN_CRT_VSYNC_PV7,
1256 };
1257 
1258 static const unsigned lcd_cs1_n_pw0_pins[] = {
1259 	TEGRA_PIN_LCD_CS1_N_PW0,
1260 };
1261 
1262 static const unsigned lcd_m1_pw1_pins[] = {
1263 	TEGRA_PIN_LCD_M1_PW1,
1264 };
1265 
1266 static const unsigned spi2_cs1_n_pw2_pins[] = {
1267 	TEGRA_PIN_SPI2_CS1_N_PW2,
1268 };
1269 
1270 static const unsigned spi2_cs2_n_pw3_pins[] = {
1271 	TEGRA_PIN_SPI2_CS2_N_PW3,
1272 };
1273 
1274 static const unsigned clk1_out_pw4_pins[] = {
1275 	TEGRA_PIN_CLK1_OUT_PW4,
1276 };
1277 
1278 static const unsigned clk2_out_pw5_pins[] = {
1279 	TEGRA_PIN_CLK2_OUT_PW5,
1280 };
1281 
1282 static const unsigned uart3_txd_pw6_pins[] = {
1283 	TEGRA_PIN_UART3_TXD_PW6,
1284 };
1285 
1286 static const unsigned uart3_rxd_pw7_pins[] = {
1287 	TEGRA_PIN_UART3_RXD_PW7,
1288 };
1289 
1290 static const unsigned spi2_mosi_px0_pins[] = {
1291 	TEGRA_PIN_SPI2_MOSI_PX0,
1292 };
1293 
1294 static const unsigned spi2_miso_px1_pins[] = {
1295 	TEGRA_PIN_SPI2_MISO_PX1,
1296 };
1297 
1298 static const unsigned spi2_sck_px2_pins[] = {
1299 	TEGRA_PIN_SPI2_SCK_PX2,
1300 };
1301 
1302 static const unsigned spi2_cs0_n_px3_pins[] = {
1303 	TEGRA_PIN_SPI2_CS0_N_PX3,
1304 };
1305 
1306 static const unsigned spi1_mosi_px4_pins[] = {
1307 	TEGRA_PIN_SPI1_MOSI_PX4,
1308 };
1309 
1310 static const unsigned spi1_sck_px5_pins[] = {
1311 	TEGRA_PIN_SPI1_SCK_PX5,
1312 };
1313 
1314 static const unsigned spi1_cs0_n_px6_pins[] = {
1315 	TEGRA_PIN_SPI1_CS0_N_PX6,
1316 };
1317 
1318 static const unsigned spi1_miso_px7_pins[] = {
1319 	TEGRA_PIN_SPI1_MISO_PX7,
1320 };
1321 
1322 static const unsigned ulpi_clk_py0_pins[] = {
1323 	TEGRA_PIN_ULPI_CLK_PY0,
1324 };
1325 
1326 static const unsigned ulpi_dir_py1_pins[] = {
1327 	TEGRA_PIN_ULPI_DIR_PY1,
1328 };
1329 
1330 static const unsigned ulpi_nxt_py2_pins[] = {
1331 	TEGRA_PIN_ULPI_NXT_PY2,
1332 };
1333 
1334 static const unsigned ulpi_stp_py3_pins[] = {
1335 	TEGRA_PIN_ULPI_STP_PY3,
1336 };
1337 
1338 static const unsigned sdmmc1_dat3_py4_pins[] = {
1339 	TEGRA_PIN_SDMMC1_DAT3_PY4,
1340 };
1341 
1342 static const unsigned sdmmc1_dat2_py5_pins[] = {
1343 	TEGRA_PIN_SDMMC1_DAT2_PY5,
1344 };
1345 
1346 static const unsigned sdmmc1_dat1_py6_pins[] = {
1347 	TEGRA_PIN_SDMMC1_DAT1_PY6,
1348 };
1349 
1350 static const unsigned sdmmc1_dat0_py7_pins[] = {
1351 	TEGRA_PIN_SDMMC1_DAT0_PY7,
1352 };
1353 
1354 static const unsigned sdmmc1_clk_pz0_pins[] = {
1355 	TEGRA_PIN_SDMMC1_CLK_PZ0,
1356 };
1357 
1358 static const unsigned sdmmc1_cmd_pz1_pins[] = {
1359 	TEGRA_PIN_SDMMC1_CMD_PZ1,
1360 };
1361 
1362 static const unsigned lcd_sdin_pz2_pins[] = {
1363 	TEGRA_PIN_LCD_SDIN_PZ2,
1364 };
1365 
1366 static const unsigned lcd_wr_n_pz3_pins[] = {
1367 	TEGRA_PIN_LCD_WR_N_PZ3,
1368 };
1369 
1370 static const unsigned lcd_sck_pz4_pins[] = {
1371 	TEGRA_PIN_LCD_SCK_PZ4,
1372 };
1373 
1374 static const unsigned sys_clk_req_pz5_pins[] = {
1375 	TEGRA_PIN_SYS_CLK_REQ_PZ5,
1376 };
1377 
1378 static const unsigned pwr_i2c_scl_pz6_pins[] = {
1379 	TEGRA_PIN_PWR_I2C_SCL_PZ6,
1380 };
1381 
1382 static const unsigned pwr_i2c_sda_pz7_pins[] = {
1383 	TEGRA_PIN_PWR_I2C_SDA_PZ7,
1384 };
1385 
1386 static const unsigned sdmmc4_dat0_paa0_pins[] = {
1387 	TEGRA_PIN_SDMMC4_DAT0_PAA0,
1388 };
1389 
1390 static const unsigned sdmmc4_dat1_paa1_pins[] = {
1391 	TEGRA_PIN_SDMMC4_DAT1_PAA1,
1392 };
1393 
1394 static const unsigned sdmmc4_dat2_paa2_pins[] = {
1395 	TEGRA_PIN_SDMMC4_DAT2_PAA2,
1396 };
1397 
1398 static const unsigned sdmmc4_dat3_paa3_pins[] = {
1399 	TEGRA_PIN_SDMMC4_DAT3_PAA3,
1400 };
1401 
1402 static const unsigned sdmmc4_dat4_paa4_pins[] = {
1403 	TEGRA_PIN_SDMMC4_DAT4_PAA4,
1404 };
1405 
1406 static const unsigned sdmmc4_dat5_paa5_pins[] = {
1407 	TEGRA_PIN_SDMMC4_DAT5_PAA5,
1408 };
1409 
1410 static const unsigned sdmmc4_dat6_paa6_pins[] = {
1411 	TEGRA_PIN_SDMMC4_DAT6_PAA6,
1412 };
1413 
1414 static const unsigned sdmmc4_dat7_paa7_pins[] = {
1415 	TEGRA_PIN_SDMMC4_DAT7_PAA7,
1416 };
1417 
1418 static const unsigned pbb0_pins[] = {
1419 	TEGRA_PIN_PBB0,
1420 };
1421 
1422 static const unsigned cam_i2c_scl_pbb1_pins[] = {
1423 	TEGRA_PIN_CAM_I2C_SCL_PBB1,
1424 };
1425 
1426 static const unsigned cam_i2c_sda_pbb2_pins[] = {
1427 	TEGRA_PIN_CAM_I2C_SDA_PBB2,
1428 };
1429 
1430 static const unsigned pbb3_pins[] = {
1431 	TEGRA_PIN_PBB3,
1432 };
1433 
1434 static const unsigned pbb4_pins[] = {
1435 	TEGRA_PIN_PBB4,
1436 };
1437 
1438 static const unsigned pbb5_pins[] = {
1439 	TEGRA_PIN_PBB5,
1440 };
1441 
1442 static const unsigned pbb6_pins[] = {
1443 	TEGRA_PIN_PBB6,
1444 };
1445 
1446 static const unsigned pbb7_pins[] = {
1447 	TEGRA_PIN_PBB7,
1448 };
1449 
1450 static const unsigned cam_mclk_pcc0_pins[] = {
1451 	TEGRA_PIN_CAM_MCLK_PCC0,
1452 };
1453 
1454 static const unsigned pcc1_pins[] = {
1455 	TEGRA_PIN_PCC1,
1456 };
1457 
1458 static const unsigned pcc2_pins[] = {
1459 	TEGRA_PIN_PCC2,
1460 };
1461 
1462 static const unsigned sdmmc4_rst_n_pcc3_pins[] = {
1463 	TEGRA_PIN_SDMMC4_RST_N_PCC3,
1464 };
1465 
1466 static const unsigned sdmmc4_clk_pcc4_pins[] = {
1467 	TEGRA_PIN_SDMMC4_CLK_PCC4,
1468 };
1469 
1470 static const unsigned clk2_req_pcc5_pins[] = {
1471 	TEGRA_PIN_CLK2_REQ_PCC5,
1472 };
1473 
1474 static const unsigned pex_l2_rst_n_pcc6_pins[] = {
1475 	TEGRA_PIN_PEX_L2_RST_N_PCC6,
1476 };
1477 
1478 static const unsigned pex_l2_clkreq_n_pcc7_pins[] = {
1479 	TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
1480 };
1481 
1482 static const unsigned pex_l0_prsnt_n_pdd0_pins[] = {
1483 	TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
1484 };
1485 
1486 static const unsigned pex_l0_rst_n_pdd1_pins[] = {
1487 	TEGRA_PIN_PEX_L0_RST_N_PDD1,
1488 };
1489 
1490 static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
1491 	TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1492 };
1493 
1494 static const unsigned pex_wake_n_pdd3_pins[] = {
1495 	TEGRA_PIN_PEX_WAKE_N_PDD3,
1496 };
1497 
1498 static const unsigned pex_l1_prsnt_n_pdd4_pins[] = {
1499 	TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
1500 };
1501 
1502 static const unsigned pex_l1_rst_n_pdd5_pins[] = {
1503 	TEGRA_PIN_PEX_L1_RST_N_PDD5,
1504 };
1505 
1506 static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
1507 	TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1508 };
1509 
1510 static const unsigned pex_l2_prsnt_n_pdd7_pins[] = {
1511 	TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
1512 };
1513 
1514 static const unsigned clk3_out_pee0_pins[] = {
1515 	TEGRA_PIN_CLK3_OUT_PEE0,
1516 };
1517 
1518 static const unsigned clk3_req_pee1_pins[] = {
1519 	TEGRA_PIN_CLK3_REQ_PEE1,
1520 };
1521 
1522 static const unsigned clk1_req_pee2_pins[] = {
1523 	TEGRA_PIN_CLK1_REQ_PEE2,
1524 };
1525 
1526 static const unsigned hdmi_cec_pee3_pins[] = {
1527 	TEGRA_PIN_HDMI_CEC_PEE3,
1528 };
1529 
1530 static const unsigned clk_32k_in_pins[] = {
1531 	TEGRA_PIN_CLK_32K_IN,
1532 };
1533 
1534 static const unsigned core_pwr_req_pins[] = {
1535 	TEGRA_PIN_CORE_PWR_REQ,
1536 };
1537 
1538 static const unsigned cpu_pwr_req_pins[] = {
1539 	TEGRA_PIN_CPU_PWR_REQ,
1540 };
1541 
1542 static const unsigned owr_pins[] = {
1543 	TEGRA_PIN_OWR,
1544 };
1545 
1546 static const unsigned pwr_int_n_pins[] = {
1547 	TEGRA_PIN_PWR_INT_N,
1548 };
1549 
1550 static const unsigned drive_ao1_pins[] = {
1551 	TEGRA_PIN_KB_ROW0_PR0,
1552 	TEGRA_PIN_KB_ROW1_PR1,
1553 	TEGRA_PIN_KB_ROW2_PR2,
1554 	TEGRA_PIN_KB_ROW3_PR3,
1555 	TEGRA_PIN_KB_ROW4_PR4,
1556 	TEGRA_PIN_KB_ROW5_PR5,
1557 	TEGRA_PIN_KB_ROW6_PR6,
1558 	TEGRA_PIN_KB_ROW7_PR7,
1559 	TEGRA_PIN_PWR_I2C_SCL_PZ6,
1560 	TEGRA_PIN_PWR_I2C_SDA_PZ7,
1561 	TEGRA_PIN_SYS_RESET_N,
1562 };
1563 
1564 static const unsigned drive_ao2_pins[] = {
1565 	TEGRA_PIN_CLK_32K_OUT_PA0,
1566 	TEGRA_PIN_KB_COL0_PQ0,
1567 	TEGRA_PIN_KB_COL1_PQ1,
1568 	TEGRA_PIN_KB_COL2_PQ2,
1569 	TEGRA_PIN_KB_COL3_PQ3,
1570 	TEGRA_PIN_KB_COL4_PQ4,
1571 	TEGRA_PIN_KB_COL5_PQ5,
1572 	TEGRA_PIN_KB_COL6_PQ6,
1573 	TEGRA_PIN_KB_COL7_PQ7,
1574 	TEGRA_PIN_KB_ROW8_PS0,
1575 	TEGRA_PIN_KB_ROW9_PS1,
1576 	TEGRA_PIN_KB_ROW10_PS2,
1577 	TEGRA_PIN_KB_ROW11_PS3,
1578 	TEGRA_PIN_KB_ROW12_PS4,
1579 	TEGRA_PIN_KB_ROW13_PS5,
1580 	TEGRA_PIN_KB_ROW14_PS6,
1581 	TEGRA_PIN_KB_ROW15_PS7,
1582 	TEGRA_PIN_SYS_CLK_REQ_PZ5,
1583 	TEGRA_PIN_CLK_32K_IN,
1584 	TEGRA_PIN_CORE_PWR_REQ,
1585 	TEGRA_PIN_CPU_PWR_REQ,
1586 	TEGRA_PIN_PWR_INT_N,
1587 };
1588 
1589 static const unsigned drive_at1_pins[] = {
1590 	TEGRA_PIN_GMI_AD8_PH0,
1591 	TEGRA_PIN_GMI_AD9_PH1,
1592 	TEGRA_PIN_GMI_AD10_PH2,
1593 	TEGRA_PIN_GMI_AD11_PH3,
1594 	TEGRA_PIN_GMI_AD12_PH4,
1595 	TEGRA_PIN_GMI_AD13_PH5,
1596 	TEGRA_PIN_GMI_AD14_PH6,
1597 	TEGRA_PIN_GMI_AD15_PH7,
1598 	TEGRA_PIN_GMI_IORDY_PI5,
1599 	TEGRA_PIN_GMI_CS7_N_PI6,
1600 };
1601 
1602 static const unsigned drive_at2_pins[] = {
1603 	TEGRA_PIN_GMI_AD0_PG0,
1604 	TEGRA_PIN_GMI_AD1_PG1,
1605 	TEGRA_PIN_GMI_AD2_PG2,
1606 	TEGRA_PIN_GMI_AD3_PG3,
1607 	TEGRA_PIN_GMI_AD4_PG4,
1608 	TEGRA_PIN_GMI_AD5_PG5,
1609 	TEGRA_PIN_GMI_AD6_PG6,
1610 	TEGRA_PIN_GMI_AD7_PG7,
1611 	TEGRA_PIN_GMI_WR_N_PI0,
1612 	TEGRA_PIN_GMI_OE_N_PI1,
1613 	TEGRA_PIN_GMI_DQS_PI2,
1614 	TEGRA_PIN_GMI_CS6_N_PI3,
1615 	TEGRA_PIN_GMI_RST_N_PI4,
1616 	TEGRA_PIN_GMI_WAIT_PI7,
1617 	TEGRA_PIN_GMI_ADV_N_PK0,
1618 	TEGRA_PIN_GMI_CLK_PK1,
1619 	TEGRA_PIN_GMI_CS4_N_PK2,
1620 	TEGRA_PIN_GMI_CS2_N_PK3,
1621 	TEGRA_PIN_GMI_CS3_N_PK4,
1622 };
1623 
1624 static const unsigned drive_at3_pins[] = {
1625 	TEGRA_PIN_GMI_WP_N_PC7,
1626 	TEGRA_PIN_GMI_CS0_N_PJ0,
1627 };
1628 
1629 static const unsigned drive_at4_pins[] = {
1630 	TEGRA_PIN_GMI_A17_PB0,
1631 	TEGRA_PIN_GMI_A18_PB1,
1632 	TEGRA_PIN_GMI_CS1_N_PJ2,
1633 	TEGRA_PIN_GMI_A16_PJ7,
1634 	TEGRA_PIN_GMI_A19_PK7,
1635 };
1636 
1637 static const unsigned drive_at5_pins[] = {
1638 	TEGRA_PIN_GEN2_I2C_SCL_PT5,
1639 	TEGRA_PIN_GEN2_I2C_SDA_PT6,
1640 };
1641 
1642 static const unsigned drive_cdev1_pins[] = {
1643 	TEGRA_PIN_CLK1_OUT_PW4,
1644 	TEGRA_PIN_CLK1_REQ_PEE2,
1645 };
1646 
1647 static const unsigned drive_cdev2_pins[] = {
1648 	TEGRA_PIN_CLK2_OUT_PW5,
1649 	TEGRA_PIN_CLK2_REQ_PCC5,
1650 };
1651 
1652 static const unsigned drive_cec_pins[] = {
1653 	TEGRA_PIN_HDMI_CEC_PEE3,
1654 };
1655 
1656 static const unsigned drive_crt_pins[] = {
1657 	TEGRA_PIN_CRT_HSYNC_PV6,
1658 	TEGRA_PIN_CRT_VSYNC_PV7,
1659 };
1660 
1661 static const unsigned drive_csus_pins[] = {
1662 	TEGRA_PIN_VI_MCLK_PT1,
1663 };
1664 
1665 static const unsigned drive_dap1_pins[] = {
1666 	TEGRA_PIN_SPDIF_OUT_PK5,
1667 	TEGRA_PIN_SPDIF_IN_PK6,
1668 	TEGRA_PIN_DAP1_FS_PN0,
1669 	TEGRA_PIN_DAP1_DIN_PN1,
1670 	TEGRA_PIN_DAP1_DOUT_PN2,
1671 	TEGRA_PIN_DAP1_SCLK_PN3,
1672 };
1673 
1674 static const unsigned drive_dap2_pins[] = {
1675 	TEGRA_PIN_DAP2_FS_PA2,
1676 	TEGRA_PIN_DAP2_SCLK_PA3,
1677 	TEGRA_PIN_DAP2_DIN_PA4,
1678 	TEGRA_PIN_DAP2_DOUT_PA5,
1679 };
1680 
1681 static const unsigned drive_dap3_pins[] = {
1682 	TEGRA_PIN_DAP3_FS_PP0,
1683 	TEGRA_PIN_DAP3_DIN_PP1,
1684 	TEGRA_PIN_DAP3_DOUT_PP2,
1685 	TEGRA_PIN_DAP3_SCLK_PP3,
1686 };
1687 
1688 static const unsigned drive_dap4_pins[] = {
1689 	TEGRA_PIN_DAP4_FS_PP4,
1690 	TEGRA_PIN_DAP4_DIN_PP5,
1691 	TEGRA_PIN_DAP4_DOUT_PP6,
1692 	TEGRA_PIN_DAP4_SCLK_PP7,
1693 };
1694 
1695 static const unsigned drive_dbg_pins[] = {
1696 	TEGRA_PIN_GEN1_I2C_SCL_PC4,
1697 	TEGRA_PIN_GEN1_I2C_SDA_PC5,
1698 	TEGRA_PIN_PU0,
1699 	TEGRA_PIN_PU1,
1700 	TEGRA_PIN_PU2,
1701 	TEGRA_PIN_PU3,
1702 	TEGRA_PIN_PU4,
1703 	TEGRA_PIN_PU5,
1704 	TEGRA_PIN_PU6,
1705 	TEGRA_PIN_JTAG_RTCK_PU7,
1706 	TEGRA_PIN_JTAG_TCK,
1707 	TEGRA_PIN_JTAG_TDI,
1708 	TEGRA_PIN_JTAG_TDO,
1709 	TEGRA_PIN_JTAG_TMS,
1710 	TEGRA_PIN_JTAG_TRST_N,
1711 	TEGRA_PIN_TEST_MODE_EN,
1712 };
1713 
1714 static const unsigned drive_ddc_pins[] = {
1715 	TEGRA_PIN_DDC_SCL_PV4,
1716 	TEGRA_PIN_DDC_SDA_PV5,
1717 };
1718 
1719 static const unsigned drive_dev3_pins[] = {
1720 	TEGRA_PIN_CLK3_OUT_PEE0,
1721 	TEGRA_PIN_CLK3_REQ_PEE1,
1722 };
1723 
1724 static const unsigned drive_gma_pins[] = {
1725 	TEGRA_PIN_SDMMC4_DAT0_PAA0,
1726 	TEGRA_PIN_SDMMC4_DAT1_PAA1,
1727 	TEGRA_PIN_SDMMC4_DAT2_PAA2,
1728 	TEGRA_PIN_SDMMC4_DAT3_PAA3,
1729 	TEGRA_PIN_SDMMC4_RST_N_PCC3,
1730 };
1731 
1732 static const unsigned drive_gmb_pins[] = {
1733 	TEGRA_PIN_SDMMC4_DAT4_PAA4,
1734 	TEGRA_PIN_SDMMC4_DAT5_PAA5,
1735 	TEGRA_PIN_SDMMC4_DAT6_PAA6,
1736 	TEGRA_PIN_SDMMC4_DAT7_PAA7,
1737 };
1738 
1739 static const unsigned drive_gmc_pins[] = {
1740 	TEGRA_PIN_SDMMC4_CLK_PCC4,
1741 };
1742 
1743 static const unsigned drive_gmd_pins[] = {
1744 	TEGRA_PIN_SDMMC4_CMD_PT7,
1745 };
1746 
1747 static const unsigned drive_gme_pins[] = {
1748 	TEGRA_PIN_PBB0,
1749 	TEGRA_PIN_CAM_I2C_SCL_PBB1,
1750 	TEGRA_PIN_CAM_I2C_SDA_PBB2,
1751 	TEGRA_PIN_PBB3,
1752 	TEGRA_PIN_PCC2,
1753 };
1754 
1755 static const unsigned drive_gmf_pins[] = {
1756 	TEGRA_PIN_PBB4,
1757 	TEGRA_PIN_PBB5,
1758 	TEGRA_PIN_PBB6,
1759 	TEGRA_PIN_PBB7,
1760 };
1761 
1762 static const unsigned drive_gmg_pins[] = {
1763 	TEGRA_PIN_CAM_MCLK_PCC0,
1764 };
1765 
1766 static const unsigned drive_gmh_pins[] = {
1767 	TEGRA_PIN_PCC1,
1768 };
1769 
1770 static const unsigned drive_gpv_pins[] = {
1771 	TEGRA_PIN_PEX_L2_RST_N_PCC6,
1772 	TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
1773 	TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
1774 	TEGRA_PIN_PEX_L0_RST_N_PDD1,
1775 	TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1776 	TEGRA_PIN_PEX_WAKE_N_PDD3,
1777 	TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
1778 	TEGRA_PIN_PEX_L1_RST_N_PDD5,
1779 	TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1780 	TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
1781 };
1782 
1783 static const unsigned drive_lcd1_pins[] = {
1784 	TEGRA_PIN_LCD_PWR1_PC1,
1785 	TEGRA_PIN_LCD_PWR2_PC6,
1786 	TEGRA_PIN_LCD_CS0_N_PN4,
1787 	TEGRA_PIN_LCD_SDOUT_PN5,
1788 	TEGRA_PIN_LCD_DC0_PN6,
1789 	TEGRA_PIN_LCD_SDIN_PZ2,
1790 	TEGRA_PIN_LCD_WR_N_PZ3,
1791 	TEGRA_PIN_LCD_SCK_PZ4,
1792 };
1793 
1794 static const unsigned drive_lcd2_pins[] = {
1795 	TEGRA_PIN_LCD_PWR0_PB2,
1796 	TEGRA_PIN_LCD_PCLK_PB3,
1797 	TEGRA_PIN_LCD_DC1_PD2,
1798 	TEGRA_PIN_LCD_D0_PE0,
1799 	TEGRA_PIN_LCD_D1_PE1,
1800 	TEGRA_PIN_LCD_D2_PE2,
1801 	TEGRA_PIN_LCD_D3_PE3,
1802 	TEGRA_PIN_LCD_D4_PE4,
1803 	TEGRA_PIN_LCD_D5_PE5,
1804 	TEGRA_PIN_LCD_D6_PE6,
1805 	TEGRA_PIN_LCD_D7_PE7,
1806 	TEGRA_PIN_LCD_D8_PF0,
1807 	TEGRA_PIN_LCD_D9_PF1,
1808 	TEGRA_PIN_LCD_D10_PF2,
1809 	TEGRA_PIN_LCD_D11_PF3,
1810 	TEGRA_PIN_LCD_D12_PF4,
1811 	TEGRA_PIN_LCD_D13_PF5,
1812 	TEGRA_PIN_LCD_D14_PF6,
1813 	TEGRA_PIN_LCD_D15_PF7,
1814 	TEGRA_PIN_LCD_DE_PJ1,
1815 	TEGRA_PIN_LCD_HSYNC_PJ3,
1816 	TEGRA_PIN_LCD_VSYNC_PJ4,
1817 	TEGRA_PIN_LCD_D16_PM0,
1818 	TEGRA_PIN_LCD_D17_PM1,
1819 	TEGRA_PIN_LCD_D18_PM2,
1820 	TEGRA_PIN_LCD_D19_PM3,
1821 	TEGRA_PIN_LCD_D20_PM4,
1822 	TEGRA_PIN_LCD_D21_PM5,
1823 	TEGRA_PIN_LCD_D22_PM6,
1824 	TEGRA_PIN_LCD_D23_PM7,
1825 	TEGRA_PIN_HDMI_INT_PN7,
1826 	TEGRA_PIN_LCD_CS1_N_PW0,
1827 	TEGRA_PIN_LCD_M1_PW1,
1828 };
1829 
1830 static const unsigned drive_owr_pins[] = {
1831 	TEGRA_PIN_OWR,
1832 };
1833 
1834 static const unsigned drive_sdio1_pins[] = {
1835 	TEGRA_PIN_SDMMC1_DAT3_PY4,
1836 	TEGRA_PIN_SDMMC1_DAT2_PY5,
1837 	TEGRA_PIN_SDMMC1_DAT1_PY6,
1838 	TEGRA_PIN_SDMMC1_DAT0_PY7,
1839 	TEGRA_PIN_SDMMC1_CLK_PZ0,
1840 	TEGRA_PIN_SDMMC1_CMD_PZ1,
1841 };
1842 
1843 static const unsigned drive_sdio2_pins[] = {
1844 	TEGRA_PIN_SDMMC3_DAT5_PD0,
1845 	TEGRA_PIN_SDMMC3_DAT4_PD1,
1846 	TEGRA_PIN_SDMMC3_DAT6_PD3,
1847 	TEGRA_PIN_SDMMC3_DAT7_PD4,
1848 };
1849 
1850 static const unsigned drive_sdio3_pins[] = {
1851 	TEGRA_PIN_SDMMC3_CLK_PA6,
1852 	TEGRA_PIN_SDMMC3_CMD_PA7,
1853 	TEGRA_PIN_SDMMC3_DAT3_PB4,
1854 	TEGRA_PIN_SDMMC3_DAT2_PB5,
1855 	TEGRA_PIN_SDMMC3_DAT1_PB6,
1856 	TEGRA_PIN_SDMMC3_DAT0_PB7,
1857 };
1858 
1859 static const unsigned drive_spi_pins[] = {
1860 	TEGRA_PIN_SPI2_CS1_N_PW2,
1861 	TEGRA_PIN_SPI2_CS2_N_PW3,
1862 	TEGRA_PIN_SPI2_MOSI_PX0,
1863 	TEGRA_PIN_SPI2_MISO_PX1,
1864 	TEGRA_PIN_SPI2_SCK_PX2,
1865 	TEGRA_PIN_SPI2_CS0_N_PX3,
1866 	TEGRA_PIN_SPI1_MOSI_PX4,
1867 	TEGRA_PIN_SPI1_SCK_PX5,
1868 	TEGRA_PIN_SPI1_CS0_N_PX6,
1869 	TEGRA_PIN_SPI1_MISO_PX7,
1870 };
1871 
1872 static const unsigned drive_uaa_pins[] = {
1873 	TEGRA_PIN_ULPI_DATA0_PO1,
1874 	TEGRA_PIN_ULPI_DATA1_PO2,
1875 	TEGRA_PIN_ULPI_DATA2_PO3,
1876 	TEGRA_PIN_ULPI_DATA3_PO4,
1877 };
1878 
1879 static const unsigned drive_uab_pins[] = {
1880 	TEGRA_PIN_ULPI_DATA7_PO0,
1881 	TEGRA_PIN_ULPI_DATA4_PO5,
1882 	TEGRA_PIN_ULPI_DATA5_PO6,
1883 	TEGRA_PIN_ULPI_DATA6_PO7,
1884 	TEGRA_PIN_PV0,
1885 	TEGRA_PIN_PV1,
1886 	TEGRA_PIN_PV2,
1887 	TEGRA_PIN_PV3,
1888 };
1889 
1890 static const unsigned drive_uart2_pins[] = {
1891 	TEGRA_PIN_UART2_TXD_PC2,
1892 	TEGRA_PIN_UART2_RXD_PC3,
1893 	TEGRA_PIN_UART2_CTS_N_PJ5,
1894 	TEGRA_PIN_UART2_RTS_N_PJ6,
1895 };
1896 
1897 static const unsigned drive_uart3_pins[] = {
1898 	TEGRA_PIN_UART3_CTS_N_PA1,
1899 	TEGRA_PIN_UART3_RTS_N_PC0,
1900 	TEGRA_PIN_UART3_TXD_PW6,
1901 	TEGRA_PIN_UART3_RXD_PW7,
1902 };
1903 
1904 static const unsigned drive_uda_pins[] = {
1905 	TEGRA_PIN_ULPI_CLK_PY0,
1906 	TEGRA_PIN_ULPI_DIR_PY1,
1907 	TEGRA_PIN_ULPI_NXT_PY2,
1908 	TEGRA_PIN_ULPI_STP_PY3,
1909 };
1910 
1911 static const unsigned drive_vi1_pins[] = {
1912 	TEGRA_PIN_VI_D1_PD5,
1913 	TEGRA_PIN_VI_VSYNC_PD6,
1914 	TEGRA_PIN_VI_HSYNC_PD7,
1915 	TEGRA_PIN_VI_D2_PL0,
1916 	TEGRA_PIN_VI_D3_PL1,
1917 	TEGRA_PIN_VI_D4_PL2,
1918 	TEGRA_PIN_VI_D5_PL3,
1919 	TEGRA_PIN_VI_D6_PL4,
1920 	TEGRA_PIN_VI_D7_PL5,
1921 	TEGRA_PIN_VI_D8_PL6,
1922 	TEGRA_PIN_VI_D9_PL7,
1923 	TEGRA_PIN_VI_PCLK_PT0,
1924 	TEGRA_PIN_VI_D10_PT2,
1925 	TEGRA_PIN_VI_D11_PT3,
1926 	TEGRA_PIN_VI_D0_PT4,
1927 };
1928 
1929 enum tegra_mux {
1930 	TEGRA_MUX_BLINK,
1931 	TEGRA_MUX_CEC,
1932 	TEGRA_MUX_CLK_12M_OUT,
1933 	TEGRA_MUX_CLK_32K_IN,
1934 	TEGRA_MUX_CORE_PWR_REQ,
1935 	TEGRA_MUX_CPU_PWR_REQ,
1936 	TEGRA_MUX_CRT,
1937 	TEGRA_MUX_DAP,
1938 	TEGRA_MUX_DDR,
1939 	TEGRA_MUX_DEV3,
1940 	TEGRA_MUX_DISPLAYA,
1941 	TEGRA_MUX_DISPLAYB,
1942 	TEGRA_MUX_DTV,
1943 	TEGRA_MUX_EXTPERIPH1,
1944 	TEGRA_MUX_EXTPERIPH2,
1945 	TEGRA_MUX_EXTPERIPH3,
1946 	TEGRA_MUX_GMI,
1947 	TEGRA_MUX_GMI_ALT,
1948 	TEGRA_MUX_HDA,
1949 	TEGRA_MUX_HDCP,
1950 	TEGRA_MUX_HDMI,
1951 	TEGRA_MUX_HSI,
1952 	TEGRA_MUX_I2C1,
1953 	TEGRA_MUX_I2C2,
1954 	TEGRA_MUX_I2C3,
1955 	TEGRA_MUX_I2C4,
1956 	TEGRA_MUX_I2CPWR,
1957 	TEGRA_MUX_I2S0,
1958 	TEGRA_MUX_I2S1,
1959 	TEGRA_MUX_I2S2,
1960 	TEGRA_MUX_I2S3,
1961 	TEGRA_MUX_I2S4,
1962 	TEGRA_MUX_INVALID,
1963 	TEGRA_MUX_KBC,
1964 	TEGRA_MUX_MIO,
1965 	TEGRA_MUX_NAND,
1966 	TEGRA_MUX_NAND_ALT,
1967 	TEGRA_MUX_OWR,
1968 	TEGRA_MUX_PCIE,
1969 	TEGRA_MUX_PWM0,
1970 	TEGRA_MUX_PWM1,
1971 	TEGRA_MUX_PWM2,
1972 	TEGRA_MUX_PWM3,
1973 	TEGRA_MUX_PWR_INT_N,
1974 	TEGRA_MUX_RSVD1,
1975 	TEGRA_MUX_RSVD2,
1976 	TEGRA_MUX_RSVD3,
1977 	TEGRA_MUX_RSVD4,
1978 	TEGRA_MUX_RTCK,
1979 	TEGRA_MUX_SATA,
1980 	TEGRA_MUX_SDMMC1,
1981 	TEGRA_MUX_SDMMC2,
1982 	TEGRA_MUX_SDMMC3,
1983 	TEGRA_MUX_SDMMC4,
1984 	TEGRA_MUX_SPDIF,
1985 	TEGRA_MUX_SPI1,
1986 	TEGRA_MUX_SPI2,
1987 	TEGRA_MUX_SPI2_ALT,
1988 	TEGRA_MUX_SPI3,
1989 	TEGRA_MUX_SPI4,
1990 	TEGRA_MUX_SPI5,
1991 	TEGRA_MUX_SPI6,
1992 	TEGRA_MUX_SYSCLK,
1993 	TEGRA_MUX_TEST,
1994 	TEGRA_MUX_TRACE,
1995 	TEGRA_MUX_UARTA,
1996 	TEGRA_MUX_UARTB,
1997 	TEGRA_MUX_UARTC,
1998 	TEGRA_MUX_UARTD,
1999 	TEGRA_MUX_UARTE,
2000 	TEGRA_MUX_ULPI,
2001 	TEGRA_MUX_VGP1,
2002 	TEGRA_MUX_VGP2,
2003 	TEGRA_MUX_VGP3,
2004 	TEGRA_MUX_VGP4,
2005 	TEGRA_MUX_VGP5,
2006 	TEGRA_MUX_VGP6,
2007 	TEGRA_MUX_VI,
2008 	TEGRA_MUX_VI_ALT1,
2009 	TEGRA_MUX_VI_ALT2,
2010 	TEGRA_MUX_VI_ALT3,
2011 };
2012 
2013 #define FUNCTION(fname)					\
2014 	{						\
2015 		.name = #fname,				\
2016 	}
2017 
2018 static struct tegra_function tegra30_functions[] = {
2019 	FUNCTION(blink),
2020 	FUNCTION(cec),
2021 	FUNCTION(clk_12m_out),
2022 	FUNCTION(clk_32k_in),
2023 	FUNCTION(core_pwr_req),
2024 	FUNCTION(cpu_pwr_req),
2025 	FUNCTION(crt),
2026 	FUNCTION(dap),
2027 	FUNCTION(ddr),
2028 	FUNCTION(dev3),
2029 	FUNCTION(displaya),
2030 	FUNCTION(displayb),
2031 	FUNCTION(dtv),
2032 	FUNCTION(extperiph1),
2033 	FUNCTION(extperiph2),
2034 	FUNCTION(extperiph3),
2035 	FUNCTION(gmi),
2036 	FUNCTION(gmi_alt),
2037 	FUNCTION(hda),
2038 	FUNCTION(hdcp),
2039 	FUNCTION(hdmi),
2040 	FUNCTION(hsi),
2041 	FUNCTION(i2c1),
2042 	FUNCTION(i2c2),
2043 	FUNCTION(i2c3),
2044 	FUNCTION(i2c4),
2045 	FUNCTION(i2cpwr),
2046 	FUNCTION(i2s0),
2047 	FUNCTION(i2s1),
2048 	FUNCTION(i2s2),
2049 	FUNCTION(i2s3),
2050 	FUNCTION(i2s4),
2051 	FUNCTION(invalid),
2052 	FUNCTION(kbc),
2053 	FUNCTION(mio),
2054 	FUNCTION(nand),
2055 	FUNCTION(nand_alt),
2056 	FUNCTION(owr),
2057 	FUNCTION(pcie),
2058 	FUNCTION(pwm0),
2059 	FUNCTION(pwm1),
2060 	FUNCTION(pwm2),
2061 	FUNCTION(pwm3),
2062 	FUNCTION(pwr_int_n),
2063 	FUNCTION(rsvd1),
2064 	FUNCTION(rsvd2),
2065 	FUNCTION(rsvd3),
2066 	FUNCTION(rsvd4),
2067 	FUNCTION(rtck),
2068 	FUNCTION(sata),
2069 	FUNCTION(sdmmc1),
2070 	FUNCTION(sdmmc2),
2071 	FUNCTION(sdmmc3),
2072 	FUNCTION(sdmmc4),
2073 	FUNCTION(spdif),
2074 	FUNCTION(spi1),
2075 	FUNCTION(spi2),
2076 	FUNCTION(spi2_alt),
2077 	FUNCTION(spi3),
2078 	FUNCTION(spi4),
2079 	FUNCTION(spi5),
2080 	FUNCTION(spi6),
2081 	FUNCTION(sysclk),
2082 	FUNCTION(test),
2083 	FUNCTION(trace),
2084 	FUNCTION(uarta),
2085 	FUNCTION(uartb),
2086 	FUNCTION(uartc),
2087 	FUNCTION(uartd),
2088 	FUNCTION(uarte),
2089 	FUNCTION(ulpi),
2090 	FUNCTION(vgp1),
2091 	FUNCTION(vgp2),
2092 	FUNCTION(vgp3),
2093 	FUNCTION(vgp4),
2094 	FUNCTION(vgp5),
2095 	FUNCTION(vgp6),
2096 	FUNCTION(vi),
2097 	FUNCTION(vi_alt1),
2098 	FUNCTION(vi_alt2),
2099 	FUNCTION(vi_alt3),
2100 };
2101 
2102 #define DRV_PINGROUP_REG_A		0x868	/* bank 0 */
2103 #define PINGROUP_REG_A			0x3000	/* bank 1 */
2104 
2105 #define DRV_PINGROUP_REG(r)		((r) - DRV_PINGROUP_REG_A)
2106 #define PINGROUP_REG(r)			((r) - PINGROUP_REG_A)
2107 
2108 #define PINGROUP_BIT_Y(b)		(b)
2109 #define PINGROUP_BIT_N(b)		(-1)
2110 
2111 #define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior)			\
2112 	{								\
2113 		.name = #pg_name,					\
2114 		.pins = pg_name##_pins,					\
2115 		.npins = ARRAY_SIZE(pg_name##_pins),			\
2116 		.funcs = {						\
2117 			TEGRA_MUX_##f0,					\
2118 			TEGRA_MUX_##f1,					\
2119 			TEGRA_MUX_##f2,					\
2120 			TEGRA_MUX_##f3,					\
2121 		},							\
2122 		.mux_reg = PINGROUP_REG(r),				\
2123 		.mux_bank = 1,						\
2124 		.mux_bit = 0,						\
2125 		.pupd_reg = PINGROUP_REG(r),				\
2126 		.pupd_bank = 1,						\
2127 		.pupd_bit = 2,						\
2128 		.tri_reg = PINGROUP_REG(r),				\
2129 		.tri_bank = 1,						\
2130 		.tri_bit = 4,						\
2131 		.einput_bit = 5,					\
2132 		.odrain_bit = PINGROUP_BIT_##od(6),			\
2133 		.lock_bit = 7,						\
2134 		.ioreset_bit = PINGROUP_BIT_##ior(8),			\
2135 		.rcv_sel_bit = -1,					\
2136 		.drv_reg = -1,						\
2137 		.parked_bitmask = 0,					\
2138 	}
2139 
2140 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b,	\
2141 		     drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w,		\
2142 		     slwf_b, slwf_w)					\
2143 	{								\
2144 		.name = "drive_" #pg_name,				\
2145 		.pins = drive_##pg_name##_pins,				\
2146 		.npins = ARRAY_SIZE(drive_##pg_name##_pins),		\
2147 		.mux_reg = -1,						\
2148 		.pupd_reg = -1,						\
2149 		.tri_reg = -1,						\
2150 		.einput_bit = -1,					\
2151 		.odrain_bit = -1,					\
2152 		.lock_bit = -1,						\
2153 		.ioreset_bit = -1,					\
2154 		.rcv_sel_bit = -1,					\
2155 		.drv_reg = DRV_PINGROUP_REG(r),				\
2156 		.drv_bank = 0,						\
2157 		.hsm_bit = hsm_b,					\
2158 		.schmitt_bit = schmitt_b,				\
2159 		.lpmd_bit = lpmd_b,					\
2160 		.drvdn_bit = drvdn_b,					\
2161 		.drvdn_width = drvdn_w,					\
2162 		.drvup_bit = drvup_b,					\
2163 		.drvup_width = drvup_w,					\
2164 		.slwr_bit = slwr_b,					\
2165 		.slwr_width = slwr_w,					\
2166 		.slwf_bit = slwf_b,					\
2167 		.slwf_width = slwf_w,					\
2168 		.drvtype_bit = -1,					\
2169 		.parked_bitmask = 0,					\
2170 	}
2171 
2172 static const struct tegra_pingroup tegra30_groups[] = {
2173 	/*       pg_name,              f0,           f1,           f2,           f3,           r,      od, ior */
2174 	PINGROUP(clk_32k_out_pa0,      BLINK,        RSVD2,        RSVD3,        RSVD4,        0x331c, N, N),
2175 	PINGROUP(uart3_cts_n_pa1,      UARTC,        RSVD2,        GMI,          RSVD4,        0x317c, N, N),
2176 	PINGROUP(dap2_fs_pa2,          I2S1,         HDA,          RSVD3,        GMI,          0x3358, N, N),
2177 	PINGROUP(dap2_sclk_pa3,        I2S1,         HDA,          RSVD3,        GMI,          0x3364, N, N),
2178 	PINGROUP(dap2_din_pa4,         I2S1,         HDA,          RSVD3,        GMI,          0x335c, N, N),
2179 	PINGROUP(dap2_dout_pa5,        I2S1,         HDA,          RSVD3,        GMI,          0x3360, N, N),
2180 	PINGROUP(sdmmc3_clk_pa6,       UARTA,        PWM2,         SDMMC3,       SPI3,         0x3390, N, N),
2181 	PINGROUP(sdmmc3_cmd_pa7,       UARTA,        PWM3,         SDMMC3,       SPI2,         0x3394, N, N),
2182 	PINGROUP(gmi_a17_pb0,          UARTD,        SPI4,         GMI,          DTV,          0x3234, N, N),
2183 	PINGROUP(gmi_a18_pb1,          UARTD,        SPI4,         GMI,          DTV,          0x3238, N, N),
2184 	PINGROUP(lcd_pwr0_pb2,         DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         0x3090, N, N),
2185 	PINGROUP(lcd_pclk_pb3,         DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x3094, N, N),
2186 	PINGROUP(sdmmc3_dat3_pb4,      RSVD1,        PWM0,         SDMMC3,       SPI3,         0x33a4, N, N),
2187 	PINGROUP(sdmmc3_dat2_pb5,      RSVD1,        PWM1,         SDMMC3,       SPI3,         0x33a0, N, N),
2188 	PINGROUP(sdmmc3_dat1_pb6,      RSVD1,        RSVD2,        SDMMC3,       SPI3,         0x339c, N, N),
2189 	PINGROUP(sdmmc3_dat0_pb7,      RSVD1,        RSVD2,        SDMMC3,       SPI3,         0x3398, N, N),
2190 	PINGROUP(uart3_rts_n_pc0,      UARTC,        PWM0,         GMI,          RSVD4,        0x3180, N, N),
2191 	PINGROUP(lcd_pwr1_pc1,         DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x3070, N, N),
2192 	PINGROUP(uart2_txd_pc2,        UARTB,        SPDIF,        UARTA,        SPI4,         0x3168, N, N),
2193 	PINGROUP(uart2_rxd_pc3,        UARTB,        SPDIF,        UARTA,        SPI4,         0x3164, N, N),
2194 	PINGROUP(gen1_i2c_scl_pc4,     I2C1,         RSVD2,        RSVD3,        RSVD4,        0x31a4, Y, N),
2195 	PINGROUP(gen1_i2c_sda_pc5,     I2C1,         RSVD2,        RSVD3,        RSVD4,        0x31a0, Y, N),
2196 	PINGROUP(lcd_pwr2_pc6,         DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         0x3074, N, N),
2197 	PINGROUP(gmi_wp_n_pc7,         RSVD1,        NAND,         GMI,          GMI_ALT,      0x31c0, N, N),
2198 	PINGROUP(sdmmc3_dat5_pd0,      PWM0,         SPI4,         SDMMC3,       SPI2,         0x33ac, N, N),
2199 	PINGROUP(sdmmc3_dat4_pd1,      PWM1,         SPI4,         SDMMC3,       SPI2,         0x33a8, N, N),
2200 	PINGROUP(lcd_dc1_pd2,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x310c, N, N),
2201 	PINGROUP(sdmmc3_dat6_pd3,      SPDIF,        SPI4,         SDMMC3,       SPI2,         0x33b0, N, N),
2202 	PINGROUP(sdmmc3_dat7_pd4,      SPDIF,        SPI4,         SDMMC3,       SPI2,         0x33b4, N, N),
2203 	PINGROUP(vi_d1_pd5,            DDR,          SDMMC2,       VI,           RSVD4,        0x3128, N, Y),
2204 	PINGROUP(vi_vsync_pd6,         DDR,          RSVD2,        VI,           RSVD4,        0x315c, N, Y),
2205 	PINGROUP(vi_hsync_pd7,         DDR,          RSVD2,        VI,           RSVD4,        0x3160, N, Y),
2206 	PINGROUP(lcd_d0_pe0,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30a4, N, N),
2207 	PINGROUP(lcd_d1_pe1,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30a8, N, N),
2208 	PINGROUP(lcd_d2_pe2,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30ac, N, N),
2209 	PINGROUP(lcd_d3_pe3,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30b0, N, N),
2210 	PINGROUP(lcd_d4_pe4,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30b4, N, N),
2211 	PINGROUP(lcd_d5_pe5,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30b8, N, N),
2212 	PINGROUP(lcd_d6_pe6,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30bc, N, N),
2213 	PINGROUP(lcd_d7_pe7,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30c0, N, N),
2214 	PINGROUP(lcd_d8_pf0,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30c4, N, N),
2215 	PINGROUP(lcd_d9_pf1,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30c8, N, N),
2216 	PINGROUP(lcd_d10_pf2,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30cc, N, N),
2217 	PINGROUP(lcd_d11_pf3,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30d0, N, N),
2218 	PINGROUP(lcd_d12_pf4,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30d4, N, N),
2219 	PINGROUP(lcd_d13_pf5,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30d8, N, N),
2220 	PINGROUP(lcd_d14_pf6,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30dc, N, N),
2221 	PINGROUP(lcd_d15_pf7,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30e0, N, N),
2222 	PINGROUP(gmi_ad0_pg0,          RSVD1,        NAND,         GMI,          RSVD4,        0x31f0, N, N),
2223 	PINGROUP(gmi_ad1_pg1,          RSVD1,        NAND,         GMI,          RSVD4,        0x31f4, N, N),
2224 	PINGROUP(gmi_ad2_pg2,          RSVD1,        NAND,         GMI,          RSVD4,        0x31f8, N, N),
2225 	PINGROUP(gmi_ad3_pg3,          RSVD1,        NAND,         GMI,          RSVD4,        0x31fc, N, N),
2226 	PINGROUP(gmi_ad4_pg4,          RSVD1,        NAND,         GMI,          RSVD4,        0x3200, N, N),
2227 	PINGROUP(gmi_ad5_pg5,          RSVD1,        NAND,         GMI,          RSVD4,        0x3204, N, N),
2228 	PINGROUP(gmi_ad6_pg6,          RSVD1,        NAND,         GMI,          RSVD4,        0x3208, N, N),
2229 	PINGROUP(gmi_ad7_pg7,          RSVD1,        NAND,         GMI,          RSVD4,        0x320c, N, N),
2230 	PINGROUP(gmi_ad8_ph0,          PWM0,         NAND,         GMI,          RSVD4,        0x3210, N, N),
2231 	PINGROUP(gmi_ad9_ph1,          PWM1,         NAND,         GMI,          RSVD4,        0x3214, N, N),
2232 	PINGROUP(gmi_ad10_ph2,         PWM2,         NAND,         GMI,          RSVD4,        0x3218, N, N),
2233 	PINGROUP(gmi_ad11_ph3,         PWM3,         NAND,         GMI,          RSVD4,        0x321c, N, N),
2234 	PINGROUP(gmi_ad12_ph4,         RSVD1,        NAND,         GMI,          RSVD4,        0x3220, N, N),
2235 	PINGROUP(gmi_ad13_ph5,         RSVD1,        NAND,         GMI,          RSVD4,        0x3224, N, N),
2236 	PINGROUP(gmi_ad14_ph6,         RSVD1,        NAND,         GMI,          RSVD4,        0x3228, N, N),
2237 	PINGROUP(gmi_ad15_ph7,         RSVD1,        NAND,         GMI,          RSVD4,        0x322c, N, N),
2238 	PINGROUP(gmi_wr_n_pi0,         RSVD1,        NAND,         GMI,          RSVD4,        0x3240, N, N),
2239 	PINGROUP(gmi_oe_n_pi1,         RSVD1,        NAND,         GMI,          RSVD4,        0x3244, N, N),
2240 	PINGROUP(gmi_dqs_pi2,          RSVD1,        NAND,         GMI,          RSVD4,        0x3248, N, N),
2241 	PINGROUP(gmi_cs6_n_pi3,        NAND,         NAND_ALT,     GMI,          SATA,         0x31e8, N, N),
2242 	PINGROUP(gmi_rst_n_pi4,        NAND,         NAND_ALT,     GMI,          RSVD4,        0x324c, N, N),
2243 	PINGROUP(gmi_iordy_pi5,        RSVD1,        NAND,         GMI,          RSVD4,        0x31c4, N, N),
2244 	PINGROUP(gmi_cs7_n_pi6,        NAND,         NAND_ALT,     GMI,          GMI_ALT,      0x31ec, N, N),
2245 	PINGROUP(gmi_wait_pi7,         RSVD1,        NAND,         GMI,          RSVD4,        0x31c8, N, N),
2246 	PINGROUP(gmi_cs0_n_pj0,        RSVD1,        NAND,         GMI,          DTV,          0x31d4, N, N),
2247 	PINGROUP(lcd_de_pj1,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x3098, N, N),
2248 	PINGROUP(gmi_cs1_n_pj2,        RSVD1,        NAND,         GMI,          DTV,          0x31d8, N, N),
2249 	PINGROUP(lcd_hsync_pj3,        DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x309c, N, N),
2250 	PINGROUP(lcd_vsync_pj4,        DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30a0, N, N),
2251 	PINGROUP(uart2_cts_n_pj5,      UARTA,        UARTB,        GMI,          SPI4,         0x3170, N, N),
2252 	PINGROUP(uart2_rts_n_pj6,      UARTA,        UARTB,        GMI,          SPI4,         0x316c, N, N),
2253 	PINGROUP(gmi_a16_pj7,          UARTD,        SPI4,         GMI,          GMI_ALT,      0x3230, N, N),
2254 	PINGROUP(gmi_adv_n_pk0,        RSVD1,        NAND,         GMI,          RSVD4,        0x31cc, N, N),
2255 	PINGROUP(gmi_clk_pk1,          RSVD1,        NAND,         GMI,          RSVD4,        0x31d0, N, N),
2256 	PINGROUP(gmi_cs4_n_pk2,        RSVD1,        NAND,         GMI,          RSVD4,        0x31e4, N, N),
2257 	PINGROUP(gmi_cs2_n_pk3,        RSVD1,        NAND,         GMI,          RSVD4,        0x31dc, N, N),
2258 	PINGROUP(gmi_cs3_n_pk4,        RSVD1,        NAND,         GMI,          GMI_ALT,      0x31e0, N, N),
2259 	PINGROUP(spdif_out_pk5,        SPDIF,        RSVD2,        I2C1,         SDMMC2,       0x3354, N, N),
2260 	PINGROUP(spdif_in_pk6,         SPDIF,        HDA,          I2C1,         SDMMC2,       0x3350, N, N),
2261 	PINGROUP(gmi_a19_pk7,          UARTD,        SPI4,         GMI,          RSVD4,        0x323c, N, N),
2262 	PINGROUP(vi_d2_pl0,            DDR,          SDMMC2,       VI,           RSVD4,        0x312c, N, Y),
2263 	PINGROUP(vi_d3_pl1,            DDR,          SDMMC2,       VI,           RSVD4,        0x3130, N, Y),
2264 	PINGROUP(vi_d4_pl2,            DDR,          SDMMC2,       VI,           RSVD4,        0x3134, N, Y),
2265 	PINGROUP(vi_d5_pl3,            DDR,          SDMMC2,       VI,           RSVD4,        0x3138, N, Y),
2266 	PINGROUP(vi_d6_pl4,            DDR,          SDMMC2,       VI,           RSVD4,        0x313c, N, Y),
2267 	PINGROUP(vi_d7_pl5,            DDR,          SDMMC2,       VI,           RSVD4,        0x3140, N, Y),
2268 	PINGROUP(vi_d8_pl6,            DDR,          SDMMC2,       VI,           RSVD4,        0x3144, N, Y),
2269 	PINGROUP(vi_d9_pl7,            DDR,          SDMMC2,       VI,           RSVD4,        0x3148, N, Y),
2270 	PINGROUP(lcd_d16_pm0,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30e4, N, N),
2271 	PINGROUP(lcd_d17_pm1,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30e8, N, N),
2272 	PINGROUP(lcd_d18_pm2,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30ec, N, N),
2273 	PINGROUP(lcd_d19_pm3,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30f0, N, N),
2274 	PINGROUP(lcd_d20_pm4,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30f4, N, N),
2275 	PINGROUP(lcd_d21_pm5,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30f8, N, N),
2276 	PINGROUP(lcd_d22_pm6,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x30fc, N, N),
2277 	PINGROUP(lcd_d23_pm7,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x3100, N, N),
2278 	PINGROUP(dap1_fs_pn0,          I2S0,         HDA,          GMI,          SDMMC2,       0x3338, N, N),
2279 	PINGROUP(dap1_din_pn1,         I2S0,         HDA,          GMI,          SDMMC2,       0x333c, N, N),
2280 	PINGROUP(dap1_dout_pn2,        I2S0,         HDA,          GMI,          SDMMC2,       0x3340, N, N),
2281 	PINGROUP(dap1_sclk_pn3,        I2S0,         HDA,          GMI,          SDMMC2,       0x3344, N, N),
2282 	PINGROUP(lcd_cs0_n_pn4,        DISPLAYA,     DISPLAYB,     SPI5,         RSVD4,        0x3084, N, N),
2283 	PINGROUP(lcd_sdout_pn5,        DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         0x307c, N, N),
2284 	PINGROUP(lcd_dc0_pn6,          DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x3088, N, N),
2285 	PINGROUP(hdmi_int_pn7,         HDMI,         RSVD2,        RSVD3,        RSVD4,        0x3110, N, N),
2286 	PINGROUP(ulpi_data7_po0,       SPI2,         HSI,          UARTA,        ULPI,         0x301c, N, N),
2287 	PINGROUP(ulpi_data0_po1,       SPI3,         HSI,          UARTA,        ULPI,         0x3000, N, N),
2288 	PINGROUP(ulpi_data1_po2,       SPI3,         HSI,          UARTA,        ULPI,         0x3004, N, N),
2289 	PINGROUP(ulpi_data2_po3,       SPI3,         HSI,          UARTA,        ULPI,         0x3008, N, N),
2290 	PINGROUP(ulpi_data3_po4,       SPI3,         HSI,          UARTA,        ULPI,         0x300c, N, N),
2291 	PINGROUP(ulpi_data4_po5,       SPI2,         HSI,          UARTA,        ULPI,         0x3010, N, N),
2292 	PINGROUP(ulpi_data5_po6,       SPI2,         HSI,          UARTA,        ULPI,         0x3014, N, N),
2293 	PINGROUP(ulpi_data6_po7,       SPI2,         HSI,          UARTA,        ULPI,         0x3018, N, N),
2294 	PINGROUP(dap3_fs_pp0,          I2S2,         RSVD2,        DISPLAYA,     DISPLAYB,     0x3030, N, N),
2295 	PINGROUP(dap3_din_pp1,         I2S2,         RSVD2,        DISPLAYA,     DISPLAYB,     0x3034, N, N),
2296 	PINGROUP(dap3_dout_pp2,        I2S2,         RSVD2,        DISPLAYA,     DISPLAYB,     0x3038, N, N),
2297 	PINGROUP(dap3_sclk_pp3,        I2S2,         RSVD2,        DISPLAYA,     DISPLAYB,     0x303c, N, N),
2298 	PINGROUP(dap4_fs_pp4,          I2S3,         RSVD2,        GMI,          RSVD4,        0x31a8, N, N),
2299 	PINGROUP(dap4_din_pp5,         I2S3,         RSVD2,        GMI,          RSVD4,        0x31ac, N, N),
2300 	PINGROUP(dap4_dout_pp6,        I2S3,         RSVD2,        GMI,          RSVD4,        0x31b0, N, N),
2301 	PINGROUP(dap4_sclk_pp7,        I2S3,         RSVD2,        GMI,          RSVD4,        0x31b4, N, N),
2302 	PINGROUP(kb_col0_pq0,          KBC,          NAND,         TRACE,        TEST,         0x32fc, N, N),
2303 	PINGROUP(kb_col1_pq1,          KBC,          NAND,         TRACE,        TEST,         0x3300, N, N),
2304 	PINGROUP(kb_col2_pq2,          KBC,          NAND,         TRACE,        RSVD4,        0x3304, N, N),
2305 	PINGROUP(kb_col3_pq3,          KBC,          NAND,         TRACE,        RSVD4,        0x3308, N, N),
2306 	PINGROUP(kb_col4_pq4,          KBC,          NAND,         TRACE,        RSVD4,        0x330c, N, N),
2307 	PINGROUP(kb_col5_pq5,          KBC,          NAND,         TRACE,        RSVD4,        0x3310, N, N),
2308 	PINGROUP(kb_col6_pq6,          KBC,          NAND,         TRACE,        MIO,          0x3314, N, N),
2309 	PINGROUP(kb_col7_pq7,          KBC,          NAND,         TRACE,        MIO,          0x3318, N, N),
2310 	PINGROUP(kb_row0_pr0,          KBC,          NAND,         RSVD3,        RSVD4,        0x32bc, N, N),
2311 	PINGROUP(kb_row1_pr1,          KBC,          NAND,         RSVD3,        RSVD4,        0x32c0, N, N),
2312 	PINGROUP(kb_row2_pr2,          KBC,          NAND,         RSVD3,        RSVD4,        0x32c4, N, N),
2313 	PINGROUP(kb_row3_pr3,          KBC,          NAND,         RSVD3,        INVALID,      0x32c8, N, N),
2314 	PINGROUP(kb_row4_pr4,          KBC,          NAND,         TRACE,        RSVD4,        0x32cc, N, N),
2315 	PINGROUP(kb_row5_pr5,          KBC,          NAND,         TRACE,        OWR,          0x32d0, N, N),
2316 	PINGROUP(kb_row6_pr6,          KBC,          NAND,         SDMMC2,       MIO,          0x32d4, N, N),
2317 	PINGROUP(kb_row7_pr7,          KBC,          NAND,         SDMMC2,       MIO,          0x32d8, N, N),
2318 	PINGROUP(kb_row8_ps0,          KBC,          NAND,         SDMMC2,       MIO,          0x32dc, N, N),
2319 	PINGROUP(kb_row9_ps1,          KBC,          NAND,         SDMMC2,       MIO,          0x32e0, N, N),
2320 	PINGROUP(kb_row10_ps2,         KBC,          NAND,         SDMMC2,       MIO,          0x32e4, N, N),
2321 	PINGROUP(kb_row11_ps3,         KBC,          NAND,         SDMMC2,       MIO,          0x32e8, N, N),
2322 	PINGROUP(kb_row12_ps4,         KBC,          NAND,         SDMMC2,       MIO,          0x32ec, N, N),
2323 	PINGROUP(kb_row13_ps5,         KBC,          NAND,         SDMMC2,       MIO,          0x32f0, N, N),
2324 	PINGROUP(kb_row14_ps6,         KBC,          NAND,         SDMMC2,       MIO,          0x32f4, N, N),
2325 	PINGROUP(kb_row15_ps7,         KBC,          NAND,         SDMMC2,       MIO,          0x32f8, N, N),
2326 	PINGROUP(vi_pclk_pt0,          RSVD1,        SDMMC2,       VI,           RSVD4,        0x3154, N, Y),
2327 	PINGROUP(vi_mclk_pt1,          VI,           VI_ALT1,      VI_ALT2,      VI_ALT3,      0x3158, N, Y),
2328 	PINGROUP(vi_d10_pt2,           DDR,          RSVD2,        VI,           RSVD4,        0x314c, N, Y),
2329 	PINGROUP(vi_d11_pt3,           DDR,          RSVD2,        VI,           RSVD4,        0x3150, N, Y),
2330 	PINGROUP(vi_d0_pt4,            DDR,          RSVD2,        VI,           RSVD4,        0x3124, N, Y),
2331 	PINGROUP(gen2_i2c_scl_pt5,     I2C2,         HDCP,         GMI,          RSVD4,        0x3250, Y, N),
2332 	PINGROUP(gen2_i2c_sda_pt6,     I2C2,         HDCP,         GMI,          RSVD4,        0x3254, Y, N),
2333 	PINGROUP(sdmmc4_cmd_pt7,       I2C3,         NAND,         GMI,          SDMMC4,       0x325c, N, Y),
2334 	PINGROUP(pu0,                  OWR,          UARTA,        GMI,          RSVD4,        0x3184, N, N),
2335 	PINGROUP(pu1,                  RSVD1,        UARTA,        GMI,          RSVD4,        0x3188, N, N),
2336 	PINGROUP(pu2,                  RSVD1,        UARTA,        GMI,          RSVD4,        0x318c, N, N),
2337 	PINGROUP(pu3,                  PWM0,         UARTA,        GMI,          RSVD4,        0x3190, N, N),
2338 	PINGROUP(pu4,                  PWM1,         UARTA,        GMI,          RSVD4,        0x3194, N, N),
2339 	PINGROUP(pu5,                  PWM2,         UARTA,        GMI,          RSVD4,        0x3198, N, N),
2340 	PINGROUP(pu6,                  PWM3,         UARTA,        GMI,          RSVD4,        0x319c, N, N),
2341 	PINGROUP(jtag_rtck_pu7,        RTCK,         RSVD2,        RSVD3,        RSVD4,        0x32b0, N, N),
2342 	PINGROUP(pv0,                  RSVD1,        RSVD2,        RSVD3,        RSVD4,        0x3040, N, N),
2343 	PINGROUP(pv1,                  RSVD1,        RSVD2,        RSVD3,        RSVD4,        0x3044, N, N),
2344 	PINGROUP(pv2,                  OWR,          RSVD2,        RSVD3,        RSVD4,        0x3060, N, N),
2345 	PINGROUP(pv3,                  CLK_12M_OUT,  RSVD2,        RSVD3,        RSVD4,        0x3064, N, N),
2346 	PINGROUP(ddc_scl_pv4,          I2C4,         RSVD2,        RSVD3,        RSVD4,        0x3114, N, N),
2347 	PINGROUP(ddc_sda_pv5,          I2C4,         RSVD2,        RSVD3,        RSVD4,        0x3118, N, N),
2348 	PINGROUP(crt_hsync_pv6,        CRT,          RSVD2,        RSVD3,        RSVD4,        0x311c, N, N),
2349 	PINGROUP(crt_vsync_pv7,        CRT,          RSVD2,        RSVD3,        RSVD4,        0x3120, N, N),
2350 	PINGROUP(lcd_cs1_n_pw0,        DISPLAYA,     DISPLAYB,     SPI5,         RSVD4,        0x3104, N, N),
2351 	PINGROUP(lcd_m1_pw1,           DISPLAYA,     DISPLAYB,     RSVD3,        RSVD4,        0x3108, N, N),
2352 	PINGROUP(spi2_cs1_n_pw2,       SPI3,         SPI2,         SPI2_ALT,     I2C1,         0x3388, N, N),
2353 	PINGROUP(spi2_cs2_n_pw3,       SPI3,         SPI2,         SPI2_ALT,     I2C1,         0x338c, N, N),
2354 	PINGROUP(clk1_out_pw4,         EXTPERIPH1,   RSVD2,        RSVD3,        RSVD4,        0x334c, N, N),
2355 	PINGROUP(clk2_out_pw5,         EXTPERIPH2,   RSVD2,        RSVD3,        RSVD4,        0x3068, N, N),
2356 	PINGROUP(uart3_txd_pw6,        UARTC,        RSVD2,        GMI,          RSVD4,        0x3174, N, N),
2357 	PINGROUP(uart3_rxd_pw7,        UARTC,        RSVD2,        GMI,          RSVD4,        0x3178, N, N),
2358 	PINGROUP(spi2_mosi_px0,        SPI6,         SPI2,         SPI3,         GMI,          0x3368, N, N),
2359 	PINGROUP(spi2_miso_px1,        SPI6,         SPI2,         SPI3,         GMI,          0x336c, N, N),
2360 	PINGROUP(spi2_sck_px2,         SPI6,         SPI2,         SPI3,         GMI,          0x3374, N, N),
2361 	PINGROUP(spi2_cs0_n_px3,       SPI6,         SPI2,         SPI3,         GMI,          0x3370, N, N),
2362 	PINGROUP(spi1_mosi_px4,        SPI2,         SPI1,         SPI2_ALT,     GMI,          0x3378, N, N),
2363 	PINGROUP(spi1_sck_px5,         SPI2,         SPI1,         SPI2_ALT,     GMI,          0x337c, N, N),
2364 	PINGROUP(spi1_cs0_n_px6,       SPI2,         SPI1,         SPI2_ALT,     GMI,          0x3380, N, N),
2365 	PINGROUP(spi1_miso_px7,        SPI3,         SPI1,         SPI2_ALT,     RSVD4,        0x3384, N, N),
2366 	PINGROUP(ulpi_clk_py0,         SPI1,         RSVD2,        UARTD,        ULPI,         0x3020, N, N),
2367 	PINGROUP(ulpi_dir_py1,         SPI1,         RSVD2,        UARTD,        ULPI,         0x3024, N, N),
2368 	PINGROUP(ulpi_nxt_py2,         SPI1,         RSVD2,        UARTD,        ULPI,         0x3028, N, N),
2369 	PINGROUP(ulpi_stp_py3,         SPI1,         RSVD2,        UARTD,        ULPI,         0x302c, N, N),
2370 	PINGROUP(sdmmc1_dat3_py4,      SDMMC1,       RSVD2,        UARTE,        UARTA,        0x3050, N, N),
2371 	PINGROUP(sdmmc1_dat2_py5,      SDMMC1,       RSVD2,        UARTE,        UARTA,        0x3054, N, N),
2372 	PINGROUP(sdmmc1_dat1_py6,      SDMMC1,       RSVD2,        UARTE,        UARTA,        0x3058, N, N),
2373 	PINGROUP(sdmmc1_dat0_py7,      SDMMC1,       RSVD2,        UARTE,        UARTA,        0x305c, N, N),
2374 	PINGROUP(sdmmc1_clk_pz0,       SDMMC1,       RSVD2,        RSVD3,        UARTA,        0x3048, N, N),
2375 	PINGROUP(sdmmc1_cmd_pz1,       SDMMC1,       RSVD2,        RSVD3,        UARTA,        0x304c, N, N),
2376 	PINGROUP(lcd_sdin_pz2,         DISPLAYA,     DISPLAYB,     SPI5,         RSVD4,        0x3078, N, N),
2377 	PINGROUP(lcd_wr_n_pz3,         DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         0x3080, N, N),
2378 	PINGROUP(lcd_sck_pz4,          DISPLAYA,     DISPLAYB,     SPI5,         HDCP,         0x308c, N, N),
2379 	PINGROUP(sys_clk_req_pz5,      SYSCLK,       RSVD2,        RSVD3,        RSVD4,        0x3320, N, N),
2380 	PINGROUP(pwr_i2c_scl_pz6,      I2CPWR,       RSVD2,        RSVD3,        RSVD4,        0x32b4, Y, N),
2381 	PINGROUP(pwr_i2c_sda_pz7,      I2CPWR,       RSVD2,        RSVD3,        RSVD4,        0x32b8, Y, N),
2382 	PINGROUP(sdmmc4_dat0_paa0,     UARTE,        SPI3,         GMI,          SDMMC4,       0x3260, N, Y),
2383 	PINGROUP(sdmmc4_dat1_paa1,     UARTE,        SPI3,         GMI,          SDMMC4,       0x3264, N, Y),
2384 	PINGROUP(sdmmc4_dat2_paa2,     UARTE,        SPI3,         GMI,          SDMMC4,       0x3268, N, Y),
2385 	PINGROUP(sdmmc4_dat3_paa3,     UARTE,        SPI3,         GMI,          SDMMC4,       0x326c, N, Y),
2386 	PINGROUP(sdmmc4_dat4_paa4,     I2C3,         I2S4,         GMI,          SDMMC4,       0x3270, N, Y),
2387 	PINGROUP(sdmmc4_dat5_paa5,     VGP3,         I2S4,         GMI,          SDMMC4,       0x3274, N, Y),
2388 	PINGROUP(sdmmc4_dat6_paa6,     VGP4,         I2S4,         GMI,          SDMMC4,       0x3278, N, Y),
2389 	PINGROUP(sdmmc4_dat7_paa7,     VGP5,         I2S4,         GMI,          SDMMC4,       0x327c, N, Y),
2390 	PINGROUP(pbb0,                 I2S4,         RSVD2,        RSVD3,        SDMMC4,       0x328c, N, N),
2391 	PINGROUP(cam_i2c_scl_pbb1,     VGP1,         I2C3,         RSVD3,        SDMMC4,       0x3290, Y, N),
2392 	PINGROUP(cam_i2c_sda_pbb2,     VGP2,         I2C3,         RSVD3,        SDMMC4,       0x3294, Y, N),
2393 	PINGROUP(pbb3,                 VGP3,         DISPLAYA,     DISPLAYB,     SDMMC4,       0x3298, N, N),
2394 	PINGROUP(pbb4,                 VGP4,         DISPLAYA,     DISPLAYB,     SDMMC4,       0x329c, N, N),
2395 	PINGROUP(pbb5,                 VGP5,         DISPLAYA,     DISPLAYB,     SDMMC4,       0x32a0, N, N),
2396 	PINGROUP(pbb6,                 VGP6,         DISPLAYA,     DISPLAYB,     SDMMC4,       0x32a4, N, N),
2397 	PINGROUP(pbb7,                 I2S4,         RSVD2,        RSVD3,        SDMMC4,       0x32a8, N, N),
2398 	PINGROUP(cam_mclk_pcc0,        VI,           VI_ALT1,      VI_ALT3,      SDMMC4,       0x3284, N, N),
2399 	PINGROUP(pcc1,                 I2S4,         RSVD2,        RSVD3,        SDMMC4,       0x3288, N, N),
2400 	PINGROUP(pcc2,                 I2S4,         RSVD2,        RSVD3,        RSVD4,        0x32ac, N, N),
2401 	PINGROUP(sdmmc4_rst_n_pcc3,    VGP6,         RSVD2,        RSVD3,        SDMMC4,       0x3280, N, Y),
2402 	PINGROUP(sdmmc4_clk_pcc4,      INVALID,      NAND,         GMI,          SDMMC4,       0x3258, N, Y),
2403 	PINGROUP(clk2_req_pcc5,        DAP,          RSVD2,        RSVD3,        RSVD4,        0x306c, N, N),
2404 	PINGROUP(pex_l2_rst_n_pcc6,    PCIE,         HDA,          RSVD3,        RSVD4,        0x33d8, N, N),
2405 	PINGROUP(pex_l2_clkreq_n_pcc7, PCIE,         HDA,          RSVD3,        RSVD4,        0x33dc, N, N),
2406 	PINGROUP(pex_l0_prsnt_n_pdd0,  PCIE,         HDA,          RSVD3,        RSVD4,        0x33b8, N, N),
2407 	PINGROUP(pex_l0_rst_n_pdd1,    PCIE,         HDA,          RSVD3,        RSVD4,        0x33bc, N, N),
2408 	PINGROUP(pex_l0_clkreq_n_pdd2, PCIE,         HDA,          RSVD3,        RSVD4,        0x33c0, N, N),
2409 	PINGROUP(pex_wake_n_pdd3,      PCIE,         HDA,          RSVD3,        RSVD4,        0x33c4, N, N),
2410 	PINGROUP(pex_l1_prsnt_n_pdd4,  PCIE,         HDA,          RSVD3,        RSVD4,        0x33c8, N, N),
2411 	PINGROUP(pex_l1_rst_n_pdd5,    PCIE,         HDA,          RSVD3,        RSVD4,        0x33cc, N, N),
2412 	PINGROUP(pex_l1_clkreq_n_pdd6, PCIE,         HDA,          RSVD3,        RSVD4,        0x33d0, N, N),
2413 	PINGROUP(pex_l2_prsnt_n_pdd7,  PCIE,         HDA,          RSVD3,        RSVD4,        0x33d4, N, N),
2414 	PINGROUP(clk3_out_pee0,        EXTPERIPH3,   RSVD2,        RSVD3,        RSVD4,        0x31b8, N, N),
2415 	PINGROUP(clk3_req_pee1,        DEV3,         RSVD2,        RSVD3,        RSVD4,        0x31bc, N, N),
2416 	PINGROUP(clk1_req_pee2,        DAP,          HDA,          RSVD3,        RSVD4,        0x3348, N, N),
2417 	PINGROUP(hdmi_cec_pee3,        CEC,          RSVD2,        RSVD3,        RSVD4,        0x33e0, Y, N),
2418 	PINGROUP(clk_32k_in,           CLK_32K_IN,   RSVD2,        RSVD3,        RSVD4,        0x3330, N, N),
2419 	PINGROUP(core_pwr_req,         CORE_PWR_REQ, RSVD2,        RSVD3,        RSVD4,        0x3324, N, N),
2420 	PINGROUP(cpu_pwr_req,          CPU_PWR_REQ,  RSVD2,        RSVD3,        RSVD4,        0x3328, N, N),
2421 	PINGROUP(owr,                  OWR,          CEC,          RSVD3,        RSVD4,        0x3334, N, N),
2422 	PINGROUP(pwr_int_n,            PWR_INT_N,    RSVD2,        RSVD3,        RSVD4,        0x332c, N, N),
2423 	/* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
2424 	DRV_PINGROUP(ao1,   0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2425 	DRV_PINGROUP(ao2,   0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2426 	DRV_PINGROUP(at1,   0x870,  2,  3,  4,  14,  5,  19,  5,  24,  2,  28,  2),
2427 	DRV_PINGROUP(at2,   0x874,  2,  3,  4,  14,  5,  19,  5,  24,  2,  28,  2),
2428 	DRV_PINGROUP(at3,   0x878,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
2429 	DRV_PINGROUP(at4,   0x87c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
2430 	DRV_PINGROUP(at5,   0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
2431 	DRV_PINGROUP(cdev1, 0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2432 	DRV_PINGROUP(cdev2, 0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2433 	DRV_PINGROUP(cec,   0x938,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2434 	DRV_PINGROUP(crt,   0x8f8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2435 	DRV_PINGROUP(csus,  0x88c, -1, -1, -1,  12,  5,  19,  5,  24,  4,  28,  4),
2436 	DRV_PINGROUP(dap1,  0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2437 	DRV_PINGROUP(dap2,  0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2438 	DRV_PINGROUP(dap3,  0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2439 	DRV_PINGROUP(dap4,  0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2440 	DRV_PINGROUP(dbg,   0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2441 	DRV_PINGROUP(ddc,   0x8fc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2442 	DRV_PINGROUP(dev3,  0x92c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2443 	DRV_PINGROUP(gma,   0x900, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
2444 	DRV_PINGROUP(gmb,   0x904, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
2445 	DRV_PINGROUP(gmc,   0x908, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
2446 	DRV_PINGROUP(gmd,   0x90c, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
2447 	DRV_PINGROUP(gme,   0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
2448 	DRV_PINGROUP(gmf,   0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
2449 	DRV_PINGROUP(gmg,   0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
2450 	DRV_PINGROUP(gmh,   0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
2451 	DRV_PINGROUP(gpv,   0x928,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2452 	DRV_PINGROUP(lcd1,  0x8a4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2453 	DRV_PINGROUP(lcd2,  0x8a8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2454 	DRV_PINGROUP(owr,   0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2455 	DRV_PINGROUP(sdio1, 0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
2456 	DRV_PINGROUP(sdio2, 0x8ac,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
2457 	DRV_PINGROUP(sdio3, 0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
2458 	DRV_PINGROUP(spi,   0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2459 	DRV_PINGROUP(uaa,   0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2460 	DRV_PINGROUP(uab,   0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2461 	DRV_PINGROUP(uart2, 0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2462 	DRV_PINGROUP(uart3, 0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2463 	DRV_PINGROUP(uda,   0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
2464 	DRV_PINGROUP(vi1,   0x8c8, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
2465 };
2466 
2467 static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
2468 	.ngpios = NUM_GPIOS,
2469 	.gpio_compatible = "nvidia,tegra30-gpio",
2470 	.pins = tegra30_pins,
2471 	.npins = ARRAY_SIZE(tegra30_pins),
2472 	.functions = tegra30_functions,
2473 	.nfunctions = ARRAY_SIZE(tegra30_functions),
2474 	.groups = tegra30_groups,
2475 	.ngroups = ARRAY_SIZE(tegra30_groups),
2476 	.hsm_in_mux = false,
2477 	.schmitt_in_mux = false,
2478 	.drvtype_in_mux = false,
2479 };
2480 
2481 static int tegra30_pinctrl_probe(struct platform_device *pdev)
2482 {
2483 	return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
2484 }
2485 
2486 static const struct of_device_id tegra30_pinctrl_of_match[] = {
2487 	{ .compatible = "nvidia,tegra30-pinmux", },
2488 	{ },
2489 };
2490 
2491 static struct platform_driver tegra30_pinctrl_driver = {
2492 	.driver = {
2493 		.name = "tegra30-pinctrl",
2494 		.of_match_table = tegra30_pinctrl_of_match,
2495 	},
2496 	.probe = tegra30_pinctrl_probe,
2497 };
2498 
2499 static int __init tegra30_pinctrl_init(void)
2500 {
2501 	return platform_driver_register(&tegra30_pinctrl_driver);
2502 }
2503 arch_initcall(tegra30_pinctrl_init);
2504