1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Pinctrl data for the NVIDIA Tegra194 pinmux
4  *
5  * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  */
16 
17 #include <linux/init.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 
24 #include "pinctrl-tegra.h"
25 
26 /* Define unique ID for each pins */
27 enum {
28 	TEGRA_PIN_DAP6_SCLK_PA0,
29 	TEGRA_PIN_DAP6_DOUT_PA1,
30 	TEGRA_PIN_DAP6_DIN_PA2,
31 	TEGRA_PIN_DAP6_FS_PA3,
32 	TEGRA_PIN_DAP4_SCLK_PA4,
33 	TEGRA_PIN_DAP4_DOUT_PA5,
34 	TEGRA_PIN_DAP4_DIN_PA6,
35 	TEGRA_PIN_DAP4_FS_PA7,
36 	TEGRA_PIN_CPU_PWR_REQ_0_PB0,
37 	TEGRA_PIN_CPU_PWR_REQ_1_PB1,
38 	TEGRA_PIN_QSPI0_SCK_PC0,
39 	TEGRA_PIN_QSPI0_CS_N_PC1,
40 	TEGRA_PIN_QSPI0_IO0_PC2,
41 	TEGRA_PIN_QSPI0_IO1_PC3,
42 	TEGRA_PIN_QSPI0_IO2_PC4,
43 	TEGRA_PIN_QSPI0_IO3_PC5,
44 	TEGRA_PIN_QSPI1_SCK_PC6,
45 	TEGRA_PIN_QSPI1_CS_N_PC7,
46 	TEGRA_PIN_QSPI1_IO0_PD0,
47 	TEGRA_PIN_QSPI1_IO1_PD1,
48 	TEGRA_PIN_QSPI1_IO2_PD2,
49 	TEGRA_PIN_QSPI1_IO3_PD3,
50 	TEGRA_PIN_EQOS_TXC_PE0,
51 	TEGRA_PIN_EQOS_TD0_PE1,
52 	TEGRA_PIN_EQOS_TD1_PE2,
53 	TEGRA_PIN_EQOS_TD2_PE3,
54 	TEGRA_PIN_EQOS_TD3_PE4,
55 	TEGRA_PIN_EQOS_TX_CTL_PE5,
56 	TEGRA_PIN_EQOS_RD0_PE6,
57 	TEGRA_PIN_EQOS_RD1_PE7,
58 	TEGRA_PIN_EQOS_RD2_PF0,
59 	TEGRA_PIN_EQOS_RD3_PF1,
60 	TEGRA_PIN_EQOS_RX_CTL_PF2,
61 	TEGRA_PIN_EQOS_RXC_PF3,
62 	TEGRA_PIN_EQOS_SMA_MDIO_PF4,
63 	TEGRA_PIN_EQOS_SMA_MDC_PF5,
64 	TEGRA_PIN_SOC_GPIO00_PG0,
65 	TEGRA_PIN_SOC_GPIO01_PG1,
66 	TEGRA_PIN_SOC_GPIO02_PG2,
67 	TEGRA_PIN_SOC_GPIO03_PG3,
68 	TEGRA_PIN_SOC_GPIO08_PG4,
69 	TEGRA_PIN_SOC_GPIO09_PG5,
70 	TEGRA_PIN_SOC_GPIO10_PG6,
71 	TEGRA_PIN_SOC_GPIO11_PG7,
72 	TEGRA_PIN_SOC_GPIO12_PH0,
73 	TEGRA_PIN_SOC_GPIO13_PH1,
74 	TEGRA_PIN_SOC_GPIO14_PH2,
75 	TEGRA_PIN_UART4_TX_PH3,
76 	TEGRA_PIN_UART4_RX_PH4,
77 	TEGRA_PIN_UART4_RTS_PH5,
78 	TEGRA_PIN_UART4_CTS_PH6,
79 	TEGRA_PIN_DAP2_SCLK_PH7,
80 	TEGRA_PIN_DAP2_DOUT_PI0,
81 	TEGRA_PIN_DAP2_DIN_PI1,
82 	TEGRA_PIN_DAP2_FS_PI2,
83 	TEGRA_PIN_GEN1_I2C_SCL_PI3,
84 	TEGRA_PIN_GEN1_I2C_SDA_PI4,
85 	TEGRA_PIN_SDMMC1_CLK_PJ0,
86 	TEGRA_PIN_SDMMC1_CMD_PJ1,
87 	TEGRA_PIN_SDMMC1_DAT0_PJ2,
88 	TEGRA_PIN_SDMMC1_DAT1_PJ3,
89 	TEGRA_PIN_SDMMC1_DAT2_PJ4,
90 	TEGRA_PIN_SDMMC1_DAT3_PJ5,
91 	TEGRA_PIN_PEX_L0_CLKREQ_N_PK0,
92 	TEGRA_PIN_PEX_L0_RST_N_PK1,
93 	TEGRA_PIN_PEX_L1_CLKREQ_N_PK2,
94 	TEGRA_PIN_PEX_L1_RST_N_PK3,
95 	TEGRA_PIN_PEX_L2_CLKREQ_N_PK4,
96 	TEGRA_PIN_PEX_L2_RST_N_PK5,
97 	TEGRA_PIN_PEX_L3_CLKREQ_N_PK6,
98 	TEGRA_PIN_PEX_L3_RST_N_PK7,
99 	TEGRA_PIN_PEX_L4_CLKREQ_N_PL0,
100 	TEGRA_PIN_PEX_L4_RST_N_PL1,
101 	TEGRA_PIN_PEX_WAKE_N_PL2,
102 	TEGRA_PIN_SATA_DEV_SLP_PL3,
103 	TEGRA_PIN_DP_AUX_CH0_HPD_PM0,
104 	TEGRA_PIN_DP_AUX_CH1_HPD_PM1,
105 	TEGRA_PIN_DP_AUX_CH2_HPD_PM2,
106 	TEGRA_PIN_DP_AUX_CH3_HPD_PM3,
107 	TEGRA_PIN_HDMI_CEC_PM4,
108 	TEGRA_PIN_SOC_GPIO50_PM5,
109 	TEGRA_PIN_SOC_GPIO51_PM6,
110 	TEGRA_PIN_SOC_GPIO52_PM7,
111 	TEGRA_PIN_SOC_GPIO53_PN0,
112 	TEGRA_PIN_SOC_GPIO54_PN1,
113 	TEGRA_PIN_SOC_GPIO55_PN2,
114 	TEGRA_PIN_SDMMC3_CLK_PO0,
115 	TEGRA_PIN_SDMMC3_CMD_PO1,
116 	TEGRA_PIN_SDMMC3_DAT0_PO2,
117 	TEGRA_PIN_SDMMC3_DAT1_PO3,
118 	TEGRA_PIN_SDMMC3_DAT2_PO4,
119 	TEGRA_PIN_SDMMC3_DAT3_PO5,
120 	TEGRA_PIN_EXTPERIPH1_CLK_PP0,
121 	TEGRA_PIN_EXTPERIPH2_CLK_PP1,
122 	TEGRA_PIN_CAM_I2C_SCL_PP2,
123 	TEGRA_PIN_CAM_I2C_SDA_PP3,
124 	TEGRA_PIN_SOC_GPIO04_PP4,
125 	TEGRA_PIN_SOC_GPIO05_PP5,
126 	TEGRA_PIN_SOC_GPIO06_PP6,
127 	TEGRA_PIN_SOC_GPIO07_PP7,
128 	TEGRA_PIN_SOC_GPIO20_PQ0,
129 	TEGRA_PIN_SOC_GPIO21_PQ1,
130 	TEGRA_PIN_SOC_GPIO22_PQ2,
131 	TEGRA_PIN_SOC_GPIO23_PQ3,
132 	TEGRA_PIN_SOC_GPIO40_PQ4,
133 	TEGRA_PIN_SOC_GPIO41_PQ5,
134 	TEGRA_PIN_SOC_GPIO42_PQ6,
135 	TEGRA_PIN_SOC_GPIO43_PQ7,
136 	TEGRA_PIN_SOC_GPIO44_PR0,
137 	TEGRA_PIN_SOC_GPIO45_PR1,
138 	TEGRA_PIN_UART1_TX_PR2,
139 	TEGRA_PIN_UART1_RX_PR3,
140 	TEGRA_PIN_UART1_RTS_PR4,
141 	TEGRA_PIN_UART1_CTS_PR5,
142 	TEGRA_PIN_DAP1_SCLK_PS0,
143 	TEGRA_PIN_DAP1_DOUT_PS1,
144 	TEGRA_PIN_DAP1_DIN_PS2,
145 	TEGRA_PIN_DAP1_FS_PS3,
146 	TEGRA_PIN_AUD_MCLK_PS4,
147 	TEGRA_PIN_SOC_GPIO30_PS5,
148 	TEGRA_PIN_SOC_GPIO31_PS6,
149 	TEGRA_PIN_SOC_GPIO32_PS7,
150 	TEGRA_PIN_SOC_GPIO33_PT0,
151 	TEGRA_PIN_DAP3_SCLK_PT1,
152 	TEGRA_PIN_DAP3_DOUT_PT2,
153 	TEGRA_PIN_DAP3_DIN_PT3,
154 	TEGRA_PIN_DAP3_FS_PT4,
155 	TEGRA_PIN_DAP5_SCLK_PT5,
156 	TEGRA_PIN_DAP5_DOUT_PT6,
157 	TEGRA_PIN_DAP5_DIN_PT7,
158 	TEGRA_PIN_DAP5_FS_PU0,
159 	TEGRA_PIN_DIRECTDC1_CLK_PV0,
160 	TEGRA_PIN_DIRECTDC1_IN_PV1,
161 	TEGRA_PIN_DIRECTDC1_OUT0_PV2,
162 	TEGRA_PIN_DIRECTDC1_OUT1_PV3,
163 	TEGRA_PIN_DIRECTDC1_OUT2_PV4,
164 	TEGRA_PIN_DIRECTDC1_OUT3_PV5,
165 	TEGRA_PIN_DIRECTDC1_OUT4_PV6,
166 	TEGRA_PIN_DIRECTDC1_OUT5_PV7,
167 	TEGRA_PIN_DIRECTDC1_OUT6_PW0,
168 	TEGRA_PIN_DIRECTDC1_OUT7_PW1,
169 	TEGRA_PIN_GPU_PWR_REQ_PX0,
170 	TEGRA_PIN_CV_PWR_REQ_PX1,
171 	TEGRA_PIN_GP_PWM2_PX2,
172 	TEGRA_PIN_GP_PWM3_PX3,
173 	TEGRA_PIN_UART2_TX_PX4,
174 	TEGRA_PIN_UART2_RX_PX5,
175 	TEGRA_PIN_UART2_RTS_PX6,
176 	TEGRA_PIN_UART2_CTS_PX7,
177 	TEGRA_PIN_SPI3_SCK_PY0,
178 	TEGRA_PIN_SPI3_MISO_PY1,
179 	TEGRA_PIN_SPI3_MOSI_PY2,
180 	TEGRA_PIN_SPI3_CS0_PY3,
181 	TEGRA_PIN_SPI3_CS1_PY4,
182 	TEGRA_PIN_UART5_TX_PY5,
183 	TEGRA_PIN_UART5_RX_PY6,
184 	TEGRA_PIN_UART5_RTS_PY7,
185 	TEGRA_PIN_UART5_CTS_PZ0,
186 	TEGRA_PIN_USB_VBUS_EN0_PZ1,
187 	TEGRA_PIN_USB_VBUS_EN1_PZ2,
188 	TEGRA_PIN_SPI1_SCK_PZ3,
189 	TEGRA_PIN_SPI1_MISO_PZ4,
190 	TEGRA_PIN_SPI1_MOSI_PZ5,
191 	TEGRA_PIN_SPI1_CS0_PZ6,
192 	TEGRA_PIN_SPI1_CS1_PZ7,
193 	TEGRA_PIN_UFS0_REF_CLK_PFF0,
194 	TEGRA_PIN_UFS0_RST_PFF1,
195 	TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
196 	TEGRA_PIN_PEX_L5_RST_N_PGG1,
197 	TEGRA_PIN_DIRECTDC_COMP,
198 	TEGRA_PIN_SDMMC4_CLK,
199 	TEGRA_PIN_SDMMC4_CMD,
200 	TEGRA_PIN_SDMMC4_DQS,
201 	TEGRA_PIN_SDMMC4_DAT7,
202 	TEGRA_PIN_SDMMC4_DAT6,
203 	TEGRA_PIN_SDMMC4_DAT5,
204 	TEGRA_PIN_SDMMC4_DAT4,
205 	TEGRA_PIN_SDMMC4_DAT3,
206 	TEGRA_PIN_SDMMC4_DAT2,
207 	TEGRA_PIN_SDMMC4_DAT1,
208 	TEGRA_PIN_SDMMC4_DAT0,
209 	TEGRA_PIN_SDMMC1_COMP,
210 	TEGRA_PIN_SDMMC1_HV_TRIM,
211 	TEGRA_PIN_SDMMC3_COMP,
212 	TEGRA_PIN_SDMMC3_HV_TRIM,
213 	TEGRA_PIN_EQOS_COMP,
214 	TEGRA_PIN_QSPI_COMP,
215 };
216 
217 enum {
218 	TEGRA_PIN_CAN1_DOUT_PAA0,
219 	TEGRA_PIN_CAN1_DIN_PAA1,
220 	TEGRA_PIN_CAN0_DOUT_PAA2,
221 	TEGRA_PIN_CAN0_DIN_PAA3,
222 	TEGRA_PIN_CAN0_STB_PAA4,
223 	TEGRA_PIN_CAN0_EN_PAA5,
224 	TEGRA_PIN_CAN0_WAKE_PAA6,
225 	TEGRA_PIN_CAN0_ERR_PAA7,
226 	TEGRA_PIN_CAN1_STB_PBB0,
227 	TEGRA_PIN_CAN1_EN_PBB1,
228 	TEGRA_PIN_CAN1_WAKE_PBB2,
229 	TEGRA_PIN_CAN1_ERR_PBB3,
230 	TEGRA_PIN_SPI2_SCK_PCC0,
231 	TEGRA_PIN_SPI2_MISO_PCC1,
232 	TEGRA_PIN_SPI2_MOSI_PCC2,
233 	TEGRA_PIN_SPI2_CS0_PCC3,
234 	TEGRA_PIN_TOUCH_CLK_PCC4,
235 	TEGRA_PIN_UART3_TX_PCC5,
236 	TEGRA_PIN_UART3_RX_PCC6,
237 	TEGRA_PIN_GEN2_I2C_SCL_PCC7,
238 	TEGRA_PIN_GEN2_I2C_SDA_PDD0,
239 	TEGRA_PIN_GEN8_I2C_SCL_PDD1,
240 	TEGRA_PIN_GEN8_I2C_SDA_PDD2,
241 	TEGRA_PIN_SAFE_STATE_PEE0,
242 	TEGRA_PIN_VCOMP_ALERT_PEE1,
243 	TEGRA_PIN_AO_RETENTION_N_PEE2,
244 	TEGRA_PIN_BATT_OC_PEE3,
245 	TEGRA_PIN_POWER_ON_PEE4,
246 	TEGRA_PIN_PWR_I2C_SCL_PEE5,
247 	TEGRA_PIN_PWR_I2C_SDA_PEE6,
248 	TEGRA_PIN_SYS_RESET_N,
249 	TEGRA_PIN_SHUTDOWN_N,
250 	TEGRA_PIN_PMU_INT_N,
251 	TEGRA_PIN_SOC_PWR_REQ,
252 	TEGRA_PIN_CLK_32K_IN,
253 };
254 
255 /* Table for pin descriptor */
256 static const struct pinctrl_pin_desc tegra194_pins[] = {
257 	PINCTRL_PIN(TEGRA_PIN_DAP6_SCLK_PA0, "DAP6_SCLK_PA0"),
258 	PINCTRL_PIN(TEGRA_PIN_DAP6_DOUT_PA1, "DAP6_DOUT_PA1"),
259 	PINCTRL_PIN(TEGRA_PIN_DAP6_DIN_PA2, "DAP6_DIN_PA2"),
260 	PINCTRL_PIN(TEGRA_PIN_DAP6_FS_PA3, "DAP6_FS_PA3"),
261 	PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PA4, "DAP4_SCLK_PA4"),
262 	PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PA5, "DAP4_DOUT_PA5"),
263 	PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PA6, "DAP4_DIN_PA6"),
264 	PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PA7, "DAP4_FS_PA7"),
265 	PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_0_PB0, "CPU_PWR_REQ_0_PB0"),
266 	PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_1_PB1, "CPU_PWR_REQ_1_PB1"),
267 	PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PC0, "QSPI0_SCK_PC0"),
268 	PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PC1, "QSPI0_CS_N_PC1"),
269 	PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PC2, "QSPI0_IO0_PC2"),
270 	PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PC3, "QSPI0_IO1_PC3"),
271 	PINCTRL_PIN(TEGRA_PIN_QSPI0_IO2_PC4, "QSPI0_IO2_PC4"),
272 	PINCTRL_PIN(TEGRA_PIN_QSPI0_IO3_PC5, "QSPI0_IO3_PC5"),
273 	PINCTRL_PIN(TEGRA_PIN_QSPI1_SCK_PC6, "QSPI1_SCK_PC6"),
274 	PINCTRL_PIN(TEGRA_PIN_QSPI1_CS_N_PC7, "QSPI1_CS_N_PC7"),
275 	PINCTRL_PIN(TEGRA_PIN_QSPI1_IO0_PD0, "QSPI1_IO0_PD0"),
276 	PINCTRL_PIN(TEGRA_PIN_QSPI1_IO1_PD1, "QSPI1_IO1_PD1"),
277 	PINCTRL_PIN(TEGRA_PIN_QSPI1_IO2_PD2, "QSPI1_IO2_PD2"),
278 	PINCTRL_PIN(TEGRA_PIN_QSPI1_IO3_PD3, "QSPI1_IO3_PD3"),
279 	PINCTRL_PIN(TEGRA_PIN_EQOS_TXC_PE0, "EQOS_TXC_PE0"),
280 	PINCTRL_PIN(TEGRA_PIN_EQOS_TD0_PE1, "EQOS_TD0_PE1"),
281 	PINCTRL_PIN(TEGRA_PIN_EQOS_TD1_PE2, "EQOS_TD1_PE2"),
282 	PINCTRL_PIN(TEGRA_PIN_EQOS_TD2_PE3, "EQOS_TD2_PE3"),
283 	PINCTRL_PIN(TEGRA_PIN_EQOS_TD3_PE4, "EQOS_TD3_PE4"),
284 	PINCTRL_PIN(TEGRA_PIN_EQOS_TX_CTL_PE5, "EQOS_TX_CTL_PE5"),
285 	PINCTRL_PIN(TEGRA_PIN_EQOS_RD0_PE6, "EQOS_RD0_PE6"),
286 	PINCTRL_PIN(TEGRA_PIN_EQOS_RD1_PE7, "EQOS_RD1_PE7"),
287 	PINCTRL_PIN(TEGRA_PIN_EQOS_RD2_PF0, "EQOS_RD2_PF0"),
288 	PINCTRL_PIN(TEGRA_PIN_EQOS_RD3_PF1, "EQOS_RD3_PF1"),
289 	PINCTRL_PIN(TEGRA_PIN_EQOS_RX_CTL_PF2, "EQOS_RX_CTL_PF2"),
290 	PINCTRL_PIN(TEGRA_PIN_EQOS_RXC_PF3, "EQOS_RXC_PF3"),
291 	PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDIO_PF4, "EQOS_SMA_MDIO_PF4"),
292 	PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDC_PF5, "EQOS_SMA_MDC_PF5"),
293 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO00_PG0, "SOC_GPIO00_PG0"),
294 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO01_PG1, "SOC_GPIO01_PG1"),
295 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO02_PG2, "SOC_GPIO02_PG2"),
296 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO03_PG3, "SOC_GPIO03_PG3"),
297 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO08_PG4, "SOC_GPIO08_PG4"),
298 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO09_PG5, "SOC_GPIO09_PG5"),
299 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO10_PG6, "SOC_GPIO10_PG6"),
300 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO11_PG7, "SOC_GPIO11_PG7"),
301 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO12_PH0, "SOC_GPIO12_PH0"),
302 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO13_PH1, "SOC_GPIO13_PH1"),
303 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO14_PH2, "SOC_GPIO14_PH2"),
304 	PINCTRL_PIN(TEGRA_PIN_UART4_TX_PH3, "UART4_TX_PH3"),
305 	PINCTRL_PIN(TEGRA_PIN_UART4_RX_PH4, "UART4_RX_PH4"),
306 	PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PH5, "UART4_RTS_PH5"),
307 	PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PH6, "UART4_CTS_PH6"),
308 	PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PH7, "DAP2_SCLK_PH7"),
309 	PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PI0, "DAP2_DOUT_PI0"),
310 	PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PI1, "DAP2_DIN_PI1"),
311 	PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PI2, "DAP2_FS_PI2"),
312 	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PI3, "GEN1_I2C_SCL_PI3"),
313 	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PI4, "GEN1_I2C_SDA_PI4"),
314 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PJ0, "SDMMC1_CLK_PJ0"),
315 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PJ1, "SDMMC1_CMD_PJ1"),
316 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PJ2, "SDMMC1_DAT0_PJ2"),
317 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PJ3, "SDMMC1_DAT1_PJ3"),
318 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PJ4, "SDMMC1_DAT2_PJ4"),
319 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PJ5, "SDMMC1_DAT3_PJ5"),
320 	PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PK0, "PEX_L0_CLKREQ_N_PK0"),
321 	PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PK1, "PEX_L0_RST_N_PK1"),
322 	PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PK2, "PEX_L1_CLKREQ_N_PK2"),
323 	PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PK3, "PEX_L1_RST_N_PK3"),
324 	PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PK4, "PEX_L2_CLKREQ_N_PK4"),
325 	PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PK5, "PEX_L2_RST_N_PK5"),
326 	PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PK6, "PEX_L3_CLKREQ_N_PK6"),
327 	PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PK7, "PEX_L3_RST_N_PK7"),
328 	PINCTRL_PIN(TEGRA_PIN_PEX_L4_CLKREQ_N_PL0, "PEX_L4_CLKREQ_N_PL0"),
329 	PINCTRL_PIN(TEGRA_PIN_PEX_L4_RST_N_PL1, "PEX_L4_RST_N_PL1"),
330 	PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PL2, "PEX_WAKE_N_PL2"),
331 	PINCTRL_PIN(TEGRA_PIN_SATA_DEV_SLP_PL3, "SATA_DEV_SLP_PL3"),
332 	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PM0, "DP_AUX_CH0_HPD_PM0"),
333 	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PM1, "DP_AUX_CH1_HPD_PM1"),
334 	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_HPD_PM2, "DP_AUX_CH2_HPD_PM2"),
335 	PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_HPD_PM3, "DP_AUX_CH3_HPD_PM3"),
336 	PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PM4, "HDMI_CEC_PM4"),
337 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO50_PM5, "SOC_GPIO50_PM5"),
338 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO51_PM6, "SOC_GPIO51_PM6"),
339 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO52_PM7, "SOC_GPIO52_PM7"),
340 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO53_PN0, "SOC_GPIO53_PN0"),
341 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO54_PN1, "SOC_GPIO54_PN1"),
342 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO55_PN2, "SOC_GPIO55_PN2"),
343 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PO0, "SDMMC3_CLK_PO0"),
344 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PO1, "SDMMC3_CMD_PO1"),
345 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PO2, "SDMMC3_DAT0_PO2"),
346 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PO3, "SDMMC3_DAT1_PO3"),
347 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PO4, "SDMMC3_DAT2_PO4"),
348 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PO5, "SDMMC3_DAT3_PO5"),
349 	PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PP0, "EXTPERIPH1_CLK_PP0"),
350 	PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PP1, "EXTPERIPH2_CLK_PP1"),
351 	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PP2, "CAM_I2C_SCL_PP2"),
352 	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PP3, "CAM_I2C_SDA_PP3"),
353 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO04_PP4, "SOC_GPIO04_PP4"),
354 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO05_PP5, "SOC_GPIO05_PP5"),
355 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO06_PP6, "SOC_GPIO06_PP6"),
356 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PP7, "SOC_GPIO07_PP7"),
357 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO20_PQ0, "SOC_GPIO20_PQ0"),
358 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PQ1, "SOC_GPIO21_PQ1"),
359 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PQ2, "SOC_GPIO22_PQ2"),
360 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PQ3, "SOC_GPIO23_PQ3"),
361 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO40_PQ4, "SOC_GPIO40_PQ4"),
362 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO41_PQ5, "SOC_GPIO41_PQ5"),
363 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO42_PQ6, "SOC_GPIO42_PQ6"),
364 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO43_PQ7, "SOC_GPIO43_PQ7"),
365 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO44_PR0, "SOC_GPIO44_PR0"),
366 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO45_PR1, "SOC_GPIO45_PR1"),
367 	PINCTRL_PIN(TEGRA_PIN_UART1_TX_PR2, "UART1_TX_PR2"),
368 	PINCTRL_PIN(TEGRA_PIN_UART1_RX_PR3, "UART1_RX_PR3"),
369 	PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PR4, "UART1_RTS_PR4"),
370 	PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PR5, "UART1_CTS_PR5"),
371 	PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PS0, "DAP1_SCLK_PS0"),
372 	PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PS1, "DAP1_DOUT_PS1"),
373 	PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PS2, "DAP1_DIN_PS2"),
374 	PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PS3, "DAP1_FS_PS3"),
375 	PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PS4, "AUD_MCLK_PS4"),
376 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO30_PS5, "SOC_GPIO30_PS5"),
377 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO31_PS6, "SOC_GPIO31_PS6"),
378 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO32_PS7, "SOC_GPIO32_PS7"),
379 	PINCTRL_PIN(TEGRA_PIN_SOC_GPIO33_PT0, "SOC_GPIO33_PT0"),
380 	PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PT1, "DAP3_SCLK_PT1"),
381 	PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PT2, "DAP3_DOUT_PT2"),
382 	PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PT3, "DAP3_DIN_PT3"),
383 	PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PT4, "DAP3_FS_PT4"),
384 	PINCTRL_PIN(TEGRA_PIN_DAP5_SCLK_PT5, "DAP5_SCLK_PT5"),
385 	PINCTRL_PIN(TEGRA_PIN_DAP5_DOUT_PT6, "DAP5_DOUT_PT6"),
386 	PINCTRL_PIN(TEGRA_PIN_DAP5_DIN_PT7, "DAP5_DIN_PT7"),
387 	PINCTRL_PIN(TEGRA_PIN_DAP5_FS_PU0, "DAP5_FS_PU0"),
388 	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_CLK_PV0, "DIRECTDC1_CLK_PV0"),
389 	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_IN_PV1, "DIRECTDC1_IN_PV1"),
390 	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT0_PV2, "DIRECTDC1_OUT0_PV2"),
391 	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT1_PV3, "DIRECTDC1_OUT1_PV3"),
392 	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT2_PV4, "DIRECTDC1_OUT2_PV4"),
393 	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT3_PV5, "DIRECTDC1_OUT3_PV5"),
394 	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT4_PV6, "DIRECTDC1_OUT4_PV6"),
395 	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT5_PV7, "DIRECTDC1_OUT5_PV7"),
396 	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT6_PW0, "DIRECTDC1_OUT6_PW0"),
397 	PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT7_PW1, "DIRECTDC1_OUT7_PW1"),
398 	PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PX0, "GPU_PWR_REQ_PX0"),
399 	PINCTRL_PIN(TEGRA_PIN_CV_PWR_REQ_PX1, "CV_PWR_REQ_PX1"),
400 	PINCTRL_PIN(TEGRA_PIN_GP_PWM2_PX2, "GP_PWM2_PX2"),
401 	PINCTRL_PIN(TEGRA_PIN_GP_PWM3_PX3, "GP_PWM3_PX3"),
402 	PINCTRL_PIN(TEGRA_PIN_UART2_TX_PX4, "UART2_TX_PX4"),
403 	PINCTRL_PIN(TEGRA_PIN_UART2_RX_PX5, "UART2_RX_PX5"),
404 	PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PX6, "UART2_RTS_PX6"),
405 	PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PX7, "UART2_CTS_PX7"),
406 	PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PY0, "SPI3_SCK_PY0"),
407 	PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PY1, "SPI3_MISO_PY1"),
408 	PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PY2, "SPI3_MOSI_PY2"),
409 	PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PY3, "SPI3_CS0_PY3"),
410 	PINCTRL_PIN(TEGRA_PIN_SPI3_CS1_PY4, "SPI3_CS1_PY4"),
411 	PINCTRL_PIN(TEGRA_PIN_UART5_TX_PY5, "UART5_TX_PY5"),
412 	PINCTRL_PIN(TEGRA_PIN_UART5_RX_PY6, "UART5_RX_PY6"),
413 	PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PY7, "UART5_RTS_PY7"),
414 	PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PZ0, "UART5_CTS_PZ0"),
415 	PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PZ1, "USB_VBUS_EN0_PZ1"),
416 	PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PZ2, "USB_VBUS_EN1_PZ2"),
417 	PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PZ3, "SPI1_SCK_PZ3"),
418 	PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PZ4, "SPI1_MISO_PZ4"),
419 	PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PZ5, "SPI1_MOSI_PZ5"),
420 	PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PZ6, "SPI1_CS0_PZ6"),
421 	PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PZ7, "SPI1_CS1_PZ7"),
422 	PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PFF0, "UFS0_REF_CLK_PFF0"),
423 	PINCTRL_PIN(TEGRA_PIN_UFS0_RST_PFF1, "UFS0_RST_PFF1"),
424 	PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
425 	PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
426 	PINCTRL_PIN(TEGRA_PIN_DIRECTDC_COMP, "DIRECTDC_COMP"),
427 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK, "SDMMC4_CLK"),
428 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD, "SDMMC4_CMD"),
429 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DQS, "SDMMC4_DQS"),
430 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7, "SDMMC4_DAT7"),
431 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6, "SDMMC4_DAT6"),
432 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5, "SDMMC4_DAT5"),
433 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4, "SDMMC4_DAT4"),
434 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3, "SDMMC4_DAT3"),
435 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2, "SDMMC4_DAT2"),
436 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1, "SDMMC4_DAT1"),
437 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0, "SDMMC4_DAT0"),
438 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),
439 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_HV_TRIM, "SDMMC1_HV_TRIM"),
440 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_COMP, "SDMMC3_COMP"),
441 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_HV_TRIM, "SDMMC3_HV_TRIM"),
442 	PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"),
443 	PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"),
444 };
445 
446 static const unsigned int dap6_sclk_pa0_pins[] = {
447 	TEGRA_PIN_DAP6_SCLK_PA0,
448 };
449 static const unsigned int dap6_dout_pa1_pins[] = {
450 	TEGRA_PIN_DAP6_DOUT_PA1,
451 };
452 static const unsigned int dap6_din_pa2_pins[] = {
453 	TEGRA_PIN_DAP6_DIN_PA2,
454 };
455 static const unsigned int dap6_fs_pa3_pins[] = {
456 	TEGRA_PIN_DAP6_FS_PA3,
457 };
458 static const unsigned int dap4_sclk_pa4_pins[] = {
459 	TEGRA_PIN_DAP4_SCLK_PA4,
460 };
461 static const unsigned int dap4_dout_pa5_pins[] = {
462 	TEGRA_PIN_DAP4_DOUT_PA5,
463 };
464 static const unsigned int dap4_din_pa6_pins[] = {
465 	TEGRA_PIN_DAP4_DIN_PA6,
466 };
467 static const unsigned int dap4_fs_pa7_pins[] = {
468 	TEGRA_PIN_DAP4_FS_PA7,
469 };
470 static const unsigned int cpu_pwr_req_0_pb0_pins[] = {
471 	TEGRA_PIN_CPU_PWR_REQ_0_PB0,
472 };
473 static const unsigned int cpu_pwr_req_1_pb1_pins[] = {
474 	TEGRA_PIN_CPU_PWR_REQ_1_PB1,
475 };
476 static const unsigned int qspi0_sck_pc0_pins[] = {
477 	TEGRA_PIN_QSPI0_SCK_PC0,
478 };
479 static const unsigned int qspi0_cs_n_pc1_pins[] = {
480 	TEGRA_PIN_QSPI0_CS_N_PC1,
481 };
482 static const unsigned int qspi0_io0_pc2_pins[] = {
483 	TEGRA_PIN_QSPI0_IO0_PC2,
484 };
485 static const unsigned int qspi0_io1_pc3_pins[] = {
486 	TEGRA_PIN_QSPI0_IO1_PC3,
487 };
488 static const unsigned int qspi0_io2_pc4_pins[] = {
489 	TEGRA_PIN_QSPI0_IO2_PC4,
490 };
491 static const unsigned int qspi0_io3_pc5_pins[] = {
492 	TEGRA_PIN_QSPI0_IO3_PC5,
493 };
494 static const unsigned int qspi1_sck_pc6_pins[] = {
495 	TEGRA_PIN_QSPI1_SCK_PC6,
496 };
497 static const unsigned int qspi1_cs_n_pc7_pins[] = {
498 	TEGRA_PIN_QSPI1_CS_N_PC7,
499 };
500 static const unsigned int qspi1_io0_pd0_pins[] = {
501 	TEGRA_PIN_QSPI1_IO0_PD0,
502 };
503 static const unsigned int qspi1_io1_pd1_pins[] = {
504 	TEGRA_PIN_QSPI1_IO1_PD1,
505 };
506 static const unsigned int qspi1_io2_pd2_pins[] = {
507 	TEGRA_PIN_QSPI1_IO2_PD2,
508 };
509 static const unsigned int qspi1_io3_pd3_pins[] = {
510 	TEGRA_PIN_QSPI1_IO3_PD3,
511 };
512 static const unsigned int eqos_txc_pe0_pins[] = {
513 	TEGRA_PIN_EQOS_TXC_PE0,
514 };
515 static const unsigned int eqos_td0_pe1_pins[] = {
516 	TEGRA_PIN_EQOS_TD0_PE1,
517 };
518 static const unsigned int eqos_td1_pe2_pins[] = {
519 	TEGRA_PIN_EQOS_TD1_PE2,
520 };
521 static const unsigned int eqos_td2_pe3_pins[] = {
522 	TEGRA_PIN_EQOS_TD2_PE3,
523 };
524 static const unsigned int eqos_td3_pe4_pins[] = {
525 	TEGRA_PIN_EQOS_TD3_PE4,
526 };
527 static const unsigned int eqos_tx_ctl_pe5_pins[] = {
528 	TEGRA_PIN_EQOS_TX_CTL_PE5,
529 };
530 static const unsigned int eqos_rd0_pe6_pins[] = {
531 	TEGRA_PIN_EQOS_RD0_PE6,
532 };
533 static const unsigned int eqos_rd1_pe7_pins[] = {
534 	TEGRA_PIN_EQOS_RD1_PE7,
535 };
536 static const unsigned int eqos_rd2_pf0_pins[] = {
537 	TEGRA_PIN_EQOS_RD2_PF0,
538 };
539 static const unsigned int eqos_rd3_pf1_pins[] = {
540 	TEGRA_PIN_EQOS_RD3_PF1,
541 };
542 static const unsigned int eqos_rx_ctl_pf2_pins[] = {
543 	TEGRA_PIN_EQOS_RX_CTL_PF2,
544 };
545 static const unsigned int eqos_rxc_pf3_pins[] = {
546 	TEGRA_PIN_EQOS_RXC_PF3,
547 };
548 static const unsigned int eqos_sma_mdio_pf4_pins[] = {
549 	TEGRA_PIN_EQOS_SMA_MDIO_PF4,
550 };
551 static const unsigned int eqos_sma_mdc_pf5_pins[] = {
552 	TEGRA_PIN_EQOS_SMA_MDC_PF5,
553 };
554 static const unsigned int soc_gpio00_pg0_pins[] = {
555 	TEGRA_PIN_SOC_GPIO00_PG0,
556 };
557 static const unsigned int soc_gpio01_pg1_pins[] = {
558 	TEGRA_PIN_SOC_GPIO01_PG1,
559 };
560 static const unsigned int soc_gpio02_pg2_pins[] = {
561 	TEGRA_PIN_SOC_GPIO02_PG2,
562 };
563 static const unsigned int soc_gpio03_pg3_pins[] = {
564 	TEGRA_PIN_SOC_GPIO03_PG3,
565 };
566 static const unsigned int soc_gpio08_pg4_pins[] = {
567 	TEGRA_PIN_SOC_GPIO08_PG4,
568 };
569 static const unsigned int soc_gpio09_pg5_pins[] = {
570 	TEGRA_PIN_SOC_GPIO09_PG5,
571 };
572 static const unsigned int soc_gpio10_pg6_pins[] = {
573 	TEGRA_PIN_SOC_GPIO10_PG6,
574 };
575 static const unsigned int soc_gpio11_pg7_pins[] = {
576 	TEGRA_PIN_SOC_GPIO11_PG7,
577 };
578 static const unsigned int soc_gpio12_ph0_pins[] = {
579 	TEGRA_PIN_SOC_GPIO12_PH0,
580 };
581 static const unsigned int soc_gpio13_ph1_pins[] = {
582 	TEGRA_PIN_SOC_GPIO13_PH1,
583 };
584 static const unsigned int soc_gpio14_ph2_pins[] = {
585 	TEGRA_PIN_SOC_GPIO14_PH2,
586 };
587 static const unsigned int uart4_tx_ph3_pins[] = {
588 	TEGRA_PIN_UART4_TX_PH3,
589 };
590 static const unsigned int uart4_rx_ph4_pins[] = {
591 	TEGRA_PIN_UART4_RX_PH4,
592 };
593 static const unsigned int uart4_rts_ph5_pins[] = {
594 	TEGRA_PIN_UART4_RTS_PH5,
595 };
596 static const unsigned int uart4_cts_ph6_pins[] = {
597 	TEGRA_PIN_UART4_CTS_PH6,
598 };
599 static const unsigned int dap2_sclk_ph7_pins[] = {
600 	TEGRA_PIN_DAP2_SCLK_PH7,
601 };
602 static const unsigned int dap2_dout_pi0_pins[] = {
603 	TEGRA_PIN_DAP2_DOUT_PI0,
604 };
605 static const unsigned int dap2_din_pi1_pins[] = {
606 	TEGRA_PIN_DAP2_DIN_PI1,
607 };
608 static const unsigned int dap2_fs_pi2_pins[] = {
609 	TEGRA_PIN_DAP2_FS_PI2,
610 };
611 static const unsigned int gen1_i2c_scl_pi3_pins[] = {
612 	TEGRA_PIN_GEN1_I2C_SCL_PI3,
613 };
614 static const unsigned int gen1_i2c_sda_pi4_pins[] = {
615 	TEGRA_PIN_GEN1_I2C_SDA_PI4,
616 };
617 static const unsigned int sdmmc1_clk_pj0_pins[] = {
618 	TEGRA_PIN_SDMMC1_CLK_PJ0,
619 };
620 static const unsigned int sdmmc1_cmd_pj1_pins[] = {
621 	TEGRA_PIN_SDMMC1_CMD_PJ1,
622 };
623 static const unsigned int sdmmc1_dat0_pj2_pins[] = {
624 	TEGRA_PIN_SDMMC1_DAT0_PJ2,
625 };
626 static const unsigned int sdmmc1_dat1_pj3_pins[] = {
627 	TEGRA_PIN_SDMMC1_DAT1_PJ3,
628 };
629 static const unsigned int sdmmc1_dat2_pj4_pins[] = {
630 	TEGRA_PIN_SDMMC1_DAT2_PJ4,
631 };
632 static const unsigned int sdmmc1_dat3_pj5_pins[] = {
633 	TEGRA_PIN_SDMMC1_DAT3_PJ5,
634 };
635 static const unsigned int pex_l0_clkreq_n_pk0_pins[] = {
636 	TEGRA_PIN_PEX_L0_CLKREQ_N_PK0,
637 };
638 static const unsigned int pex_l0_rst_n_pk1_pins[] = {
639 	TEGRA_PIN_PEX_L0_RST_N_PK1,
640 };
641 static const unsigned int pex_l1_clkreq_n_pk2_pins[] = {
642 	TEGRA_PIN_PEX_L1_CLKREQ_N_PK2,
643 };
644 static const unsigned int pex_l1_rst_n_pk3_pins[] = {
645 	TEGRA_PIN_PEX_L1_RST_N_PK3,
646 };
647 static const unsigned int pex_l2_clkreq_n_pk4_pins[] = {
648 	TEGRA_PIN_PEX_L2_CLKREQ_N_PK4,
649 };
650 static const unsigned int pex_l2_rst_n_pk5_pins[] = {
651 	TEGRA_PIN_PEX_L2_RST_N_PK5,
652 };
653 static const unsigned int pex_l3_clkreq_n_pk6_pins[] = {
654 	TEGRA_PIN_PEX_L3_CLKREQ_N_PK6,
655 };
656 static const unsigned int pex_l3_rst_n_pk7_pins[] = {
657 	TEGRA_PIN_PEX_L3_RST_N_PK7,
658 };
659 static const unsigned int pex_l4_clkreq_n_pl0_pins[] = {
660 	TEGRA_PIN_PEX_L4_CLKREQ_N_PL0,
661 };
662 static const unsigned int pex_l4_rst_n_pl1_pins[] = {
663 	TEGRA_PIN_PEX_L4_RST_N_PL1,
664 };
665 static const unsigned int pex_wake_n_pl2_pins[] = {
666 	TEGRA_PIN_PEX_WAKE_N_PL2,
667 };
668 static const unsigned int sata_dev_slp_pl3_pins[] = {
669 	TEGRA_PIN_SATA_DEV_SLP_PL3,
670 };
671 static const unsigned int dp_aux_ch0_hpd_pm0_pins[] = {
672 	TEGRA_PIN_DP_AUX_CH0_HPD_PM0,
673 };
674 static const unsigned int dp_aux_ch1_hpd_pm1_pins[] = {
675 	TEGRA_PIN_DP_AUX_CH1_HPD_PM1,
676 };
677 static const unsigned int dp_aux_ch2_hpd_pm2_pins[] = {
678 	TEGRA_PIN_DP_AUX_CH2_HPD_PM2,
679 };
680 static const unsigned int dp_aux_ch3_hpd_pm3_pins[] = {
681 	TEGRA_PIN_DP_AUX_CH3_HPD_PM3,
682 };
683 static const unsigned int hdmi_cec_pm4_pins[] = {
684 	TEGRA_PIN_HDMI_CEC_PM4,
685 };
686 static const unsigned int soc_gpio50_pm5_pins[] = {
687 	TEGRA_PIN_SOC_GPIO50_PM5,
688 };
689 static const unsigned int soc_gpio51_pm6_pins[] = {
690 	TEGRA_PIN_SOC_GPIO51_PM6,
691 };
692 static const unsigned int soc_gpio52_pm7_pins[] = {
693 	TEGRA_PIN_SOC_GPIO52_PM7,
694 };
695 static const unsigned int soc_gpio53_pn0_pins[] = {
696 	TEGRA_PIN_SOC_GPIO53_PN0,
697 };
698 static const unsigned int soc_gpio54_pn1_pins[] = {
699 	TEGRA_PIN_SOC_GPIO54_PN1,
700 };
701 static const unsigned int soc_gpio55_pn2_pins[] = {
702 	TEGRA_PIN_SOC_GPIO55_PN2,
703 };
704 static const unsigned int sdmmc3_clk_po0_pins[] = {
705 	TEGRA_PIN_SDMMC3_CLK_PO0,
706 };
707 static const unsigned int sdmmc3_cmd_po1_pins[] = {
708 	TEGRA_PIN_SDMMC3_CMD_PO1,
709 };
710 static const unsigned int sdmmc3_dat0_po2_pins[] = {
711 	TEGRA_PIN_SDMMC3_DAT0_PO2,
712 };
713 static const unsigned int sdmmc3_dat1_po3_pins[] = {
714 	TEGRA_PIN_SDMMC3_DAT1_PO3,
715 };
716 static const unsigned int sdmmc3_dat2_po4_pins[] = {
717 	TEGRA_PIN_SDMMC3_DAT2_PO4,
718 };
719 static const unsigned int sdmmc3_dat3_po5_pins[] = {
720 	TEGRA_PIN_SDMMC3_DAT3_PO5,
721 };
722 static const unsigned int extperiph1_clk_pp0_pins[] = {
723 	TEGRA_PIN_EXTPERIPH1_CLK_PP0,
724 };
725 static const unsigned int extperiph2_clk_pp1_pins[] = {
726 	TEGRA_PIN_EXTPERIPH2_CLK_PP1,
727 };
728 static const unsigned int cam_i2c_scl_pp2_pins[] = {
729 	TEGRA_PIN_CAM_I2C_SCL_PP2,
730 };
731 static const unsigned int cam_i2c_sda_pp3_pins[] = {
732 	TEGRA_PIN_CAM_I2C_SDA_PP3,
733 };
734 static const unsigned int soc_gpio04_pp4_pins[] = {
735 	TEGRA_PIN_SOC_GPIO04_PP4,
736 };
737 static const unsigned int soc_gpio05_pp5_pins[] = {
738 	TEGRA_PIN_SOC_GPIO05_PP5,
739 };
740 static const unsigned int soc_gpio06_pp6_pins[] = {
741 	TEGRA_PIN_SOC_GPIO06_PP6,
742 };
743 static const unsigned int soc_gpio07_pp7_pins[] = {
744 	TEGRA_PIN_SOC_GPIO07_PP7,
745 };
746 static const unsigned int soc_gpio20_pq0_pins[] = {
747 	TEGRA_PIN_SOC_GPIO20_PQ0,
748 };
749 static const unsigned int soc_gpio21_pq1_pins[] = {
750 	TEGRA_PIN_SOC_GPIO21_PQ1,
751 };
752 static const unsigned int soc_gpio22_pq2_pins[] = {
753 	TEGRA_PIN_SOC_GPIO22_PQ2,
754 };
755 static const unsigned int soc_gpio23_pq3_pins[] = {
756 	TEGRA_PIN_SOC_GPIO23_PQ3,
757 };
758 static const unsigned int soc_gpio40_pq4_pins[] = {
759 	TEGRA_PIN_SOC_GPIO40_PQ4,
760 };
761 static const unsigned int soc_gpio41_pq5_pins[] = {
762 	TEGRA_PIN_SOC_GPIO41_PQ5,
763 };
764 static const unsigned int soc_gpio42_pq6_pins[] = {
765 	TEGRA_PIN_SOC_GPIO42_PQ6,
766 };
767 static const unsigned int soc_gpio43_pq7_pins[] = {
768 	TEGRA_PIN_SOC_GPIO43_PQ7,
769 };
770 static const unsigned int soc_gpio44_pr0_pins[] = {
771 	TEGRA_PIN_SOC_GPIO44_PR0,
772 };
773 static const unsigned int soc_gpio45_pr1_pins[] = {
774 	TEGRA_PIN_SOC_GPIO45_PR1,
775 };
776 static const unsigned int uart1_tx_pr2_pins[] = {
777 	TEGRA_PIN_UART1_TX_PR2,
778 };
779 static const unsigned int uart1_rx_pr3_pins[] = {
780 	TEGRA_PIN_UART1_RX_PR3,
781 };
782 static const unsigned int uart1_rts_pr4_pins[] = {
783 	TEGRA_PIN_UART1_RTS_PR4,
784 };
785 static const unsigned int uart1_cts_pr5_pins[] = {
786 	TEGRA_PIN_UART1_CTS_PR5,
787 };
788 static const unsigned int dap1_sclk_ps0_pins[] = {
789 	TEGRA_PIN_DAP1_SCLK_PS0,
790 };
791 static const unsigned int dap1_dout_ps1_pins[] = {
792 	TEGRA_PIN_DAP1_DOUT_PS1,
793 };
794 static const unsigned int dap1_din_ps2_pins[] = {
795 	TEGRA_PIN_DAP1_DIN_PS2,
796 };
797 static const unsigned int dap1_fs_ps3_pins[] = {
798 	TEGRA_PIN_DAP1_FS_PS3,
799 };
800 static const unsigned int aud_mclk_ps4_pins[] = {
801 	TEGRA_PIN_AUD_MCLK_PS4,
802 };
803 static const unsigned int soc_gpio30_ps5_pins[] = {
804 	TEGRA_PIN_SOC_GPIO30_PS5,
805 };
806 static const unsigned int soc_gpio31_ps6_pins[] = {
807 	TEGRA_PIN_SOC_GPIO31_PS6,
808 };
809 static const unsigned int soc_gpio32_ps7_pins[] = {
810 	TEGRA_PIN_SOC_GPIO32_PS7,
811 };
812 static const unsigned int soc_gpio33_pt0_pins[] = {
813 	TEGRA_PIN_SOC_GPIO33_PT0,
814 };
815 static const unsigned int dap3_sclk_pt1_pins[] = {
816 	TEGRA_PIN_DAP3_SCLK_PT1,
817 };
818 static const unsigned int dap3_dout_pt2_pins[] = {
819 	TEGRA_PIN_DAP3_DOUT_PT2,
820 };
821 static const unsigned int dap3_din_pt3_pins[] = {
822 	TEGRA_PIN_DAP3_DIN_PT3,
823 };
824 static const unsigned int dap3_fs_pt4_pins[] = {
825 	TEGRA_PIN_DAP3_FS_PT4,
826 };
827 static const unsigned int dap5_sclk_pt5_pins[] = {
828 	TEGRA_PIN_DAP5_SCLK_PT5,
829 };
830 static const unsigned int dap5_dout_pt6_pins[] = {
831 	TEGRA_PIN_DAP5_DOUT_PT6,
832 };
833 static const unsigned int dap5_din_pt7_pins[] = {
834 	TEGRA_PIN_DAP5_DIN_PT7,
835 };
836 static const unsigned int dap5_fs_pu0_pins[] = {
837 	TEGRA_PIN_DAP5_FS_PU0,
838 };
839 static const unsigned int directdc1_clk_pv0_pins[] = {
840 	TEGRA_PIN_DIRECTDC1_CLK_PV0,
841 };
842 static const unsigned int directdc1_in_pv1_pins[] = {
843 	TEGRA_PIN_DIRECTDC1_IN_PV1,
844 };
845 static const unsigned int directdc1_out0_pv2_pins[] = {
846 	TEGRA_PIN_DIRECTDC1_OUT0_PV2,
847 };
848 static const unsigned int directdc1_out1_pv3_pins[] = {
849 	TEGRA_PIN_DIRECTDC1_OUT1_PV3,
850 };
851 static const unsigned int directdc1_out2_pv4_pins[] = {
852 	TEGRA_PIN_DIRECTDC1_OUT2_PV4,
853 };
854 static const unsigned int directdc1_out3_pv5_pins[] = {
855 	TEGRA_PIN_DIRECTDC1_OUT3_PV5,
856 };
857 static const unsigned int directdc1_out4_pv6_pins[] = {
858 	TEGRA_PIN_DIRECTDC1_OUT4_PV6,
859 };
860 static const unsigned int directdc1_out5_pv7_pins[] = {
861 	TEGRA_PIN_DIRECTDC1_OUT5_PV7,
862 };
863 static const unsigned int directdc1_out6_pw0_pins[] = {
864 	TEGRA_PIN_DIRECTDC1_OUT6_PW0,
865 };
866 static const unsigned int directdc1_out7_pw1_pins[] = {
867 	TEGRA_PIN_DIRECTDC1_OUT7_PW1,
868 };
869 static const unsigned int gpu_pwr_req_px0_pins[] = {
870 	TEGRA_PIN_GPU_PWR_REQ_PX0,
871 };
872 static const unsigned int cv_pwr_req_px1_pins[] = {
873 	TEGRA_PIN_CV_PWR_REQ_PX1,
874 };
875 static const unsigned int gp_pwm2_px2_pins[] = {
876 	TEGRA_PIN_GP_PWM2_PX2,
877 };
878 static const unsigned int gp_pwm3_px3_pins[] = {
879 	TEGRA_PIN_GP_PWM3_PX3,
880 };
881 static const unsigned int uart2_tx_px4_pins[] = {
882 	TEGRA_PIN_UART2_TX_PX4,
883 };
884 static const unsigned int uart2_rx_px5_pins[] = {
885 	TEGRA_PIN_UART2_RX_PX5,
886 };
887 static const unsigned int uart2_rts_px6_pins[] = {
888 	TEGRA_PIN_UART2_RTS_PX6,
889 };
890 static const unsigned int uart2_cts_px7_pins[] = {
891 	TEGRA_PIN_UART2_CTS_PX7,
892 };
893 static const unsigned int spi3_sck_py0_pins[] = {
894 	TEGRA_PIN_SPI3_SCK_PY0,
895 };
896 static const unsigned int spi3_miso_py1_pins[] = {
897 	TEGRA_PIN_SPI3_MISO_PY1,
898 };
899 static const unsigned int spi3_mosi_py2_pins[] = {
900 	TEGRA_PIN_SPI3_MOSI_PY2,
901 };
902 static const unsigned int spi3_cs0_py3_pins[] = {
903 	TEGRA_PIN_SPI3_CS0_PY3,
904 };
905 static const unsigned int spi3_cs1_py4_pins[] = {
906 	TEGRA_PIN_SPI3_CS1_PY4,
907 };
908 static const unsigned int uart5_tx_py5_pins[] = {
909 	TEGRA_PIN_UART5_TX_PY5,
910 };
911 static const unsigned int uart5_rx_py6_pins[] = {
912 	TEGRA_PIN_UART5_RX_PY6,
913 };
914 static const unsigned int uart5_rts_py7_pins[] = {
915 	TEGRA_PIN_UART5_RTS_PY7,
916 };
917 static const unsigned int uart5_cts_pz0_pins[] = {
918 	TEGRA_PIN_UART5_CTS_PZ0,
919 };
920 static const unsigned int usb_vbus_en0_pz1_pins[] = {
921 	TEGRA_PIN_USB_VBUS_EN0_PZ1,
922 };
923 static const unsigned int usb_vbus_en1_pz2_pins[] = {
924 	TEGRA_PIN_USB_VBUS_EN1_PZ2,
925 };
926 static const unsigned int spi1_sck_pz3_pins[] = {
927 	TEGRA_PIN_SPI1_SCK_PZ3,
928 };
929 static const unsigned int spi1_miso_pz4_pins[] = {
930 	TEGRA_PIN_SPI1_MISO_PZ4,
931 };
932 static const unsigned int spi1_mosi_pz5_pins[] = {
933 	TEGRA_PIN_SPI1_MOSI_PZ5,
934 };
935 static const unsigned int spi1_cs0_pz6_pins[] = {
936 	TEGRA_PIN_SPI1_CS0_PZ6,
937 };
938 static const unsigned int spi1_cs1_pz7_pins[] = {
939 	TEGRA_PIN_SPI1_CS1_PZ7,
940 };
941 static const unsigned int can1_dout_paa0_pins[] = {
942 	TEGRA_PIN_CAN1_DOUT_PAA0,
943 };
944 static const unsigned int can1_din_paa1_pins[] = {
945 	TEGRA_PIN_CAN1_DIN_PAA1,
946 };
947 static const unsigned int can0_dout_paa2_pins[] = {
948 	TEGRA_PIN_CAN0_DOUT_PAA2,
949 };
950 static const unsigned int can0_din_paa3_pins[] = {
951 	TEGRA_PIN_CAN0_DIN_PAA3,
952 };
953 static const unsigned int can0_stb_paa4_pins[] = {
954 	TEGRA_PIN_CAN0_STB_PAA4,
955 };
956 static const unsigned int can0_en_paa5_pins[] = {
957 	TEGRA_PIN_CAN0_EN_PAA5,
958 };
959 static const unsigned int can0_wake_paa6_pins[] = {
960 	TEGRA_PIN_CAN0_WAKE_PAA6,
961 };
962 static const unsigned int can0_err_paa7_pins[] = {
963 	TEGRA_PIN_CAN0_ERR_PAA7,
964 };
965 static const unsigned int can1_stb_pbb0_pins[] = {
966 	TEGRA_PIN_CAN1_STB_PBB0,
967 };
968 static const unsigned int can1_en_pbb1_pins[] = {
969 	TEGRA_PIN_CAN1_EN_PBB1,
970 };
971 static const unsigned int can1_wake_pbb2_pins[] = {
972 	TEGRA_PIN_CAN1_WAKE_PBB2,
973 };
974 static const unsigned int can1_err_pbb3_pins[] = {
975 	TEGRA_PIN_CAN1_ERR_PBB3,
976 };
977 static const unsigned int spi2_sck_pcc0_pins[] = {
978 	TEGRA_PIN_SPI2_SCK_PCC0,
979 };
980 static const unsigned int spi2_miso_pcc1_pins[] = {
981 	TEGRA_PIN_SPI2_MISO_PCC1,
982 };
983 static const unsigned int spi2_mosi_pcc2_pins[] = {
984 	TEGRA_PIN_SPI2_MOSI_PCC2,
985 };
986 static const unsigned int spi2_cs0_pcc3_pins[] = {
987 	TEGRA_PIN_SPI2_CS0_PCC3,
988 };
989 static const unsigned int touch_clk_pcc4_pins[] = {
990 	TEGRA_PIN_TOUCH_CLK_PCC4,
991 };
992 static const unsigned int uart3_tx_pcc5_pins[] = {
993 	TEGRA_PIN_UART3_TX_PCC5,
994 };
995 static const unsigned int uart3_rx_pcc6_pins[] = {
996 	TEGRA_PIN_UART3_RX_PCC6,
997 };
998 static const unsigned int gen2_i2c_scl_pcc7_pins[] = {
999 	TEGRA_PIN_GEN2_I2C_SCL_PCC7,
1000 };
1001 static const unsigned int gen2_i2c_sda_pdd0_pins[] = {
1002 	TEGRA_PIN_GEN2_I2C_SDA_PDD0,
1003 };
1004 static const unsigned int gen8_i2c_scl_pdd1_pins[] = {
1005 	TEGRA_PIN_GEN8_I2C_SCL_PDD1,
1006 };
1007 static const unsigned int gen8_i2c_sda_pdd2_pins[] = {
1008 	TEGRA_PIN_GEN8_I2C_SDA_PDD2,
1009 };
1010 static const unsigned int safe_state_pee0_pins[] = {
1011 	TEGRA_PIN_SAFE_STATE_PEE0,
1012 };
1013 static const unsigned int vcomp_alert_pee1_pins[] = {
1014 	TEGRA_PIN_VCOMP_ALERT_PEE1,
1015 };
1016 static const unsigned int ao_retention_n_pee2_pins[] = {
1017 	TEGRA_PIN_AO_RETENTION_N_PEE2,
1018 };
1019 static const unsigned int batt_oc_pee3_pins[] = {
1020 	TEGRA_PIN_BATT_OC_PEE3,
1021 };
1022 static const unsigned int power_on_pee4_pins[] = {
1023 	TEGRA_PIN_POWER_ON_PEE4,
1024 };
1025 static const unsigned int pwr_i2c_scl_pee5_pins[] = {
1026 	TEGRA_PIN_PWR_I2C_SCL_PEE5,
1027 };
1028 static const unsigned int pwr_i2c_sda_pee6_pins[] = {
1029 	TEGRA_PIN_PWR_I2C_SDA_PEE6,
1030 };
1031 static const unsigned int ufs0_ref_clk_pff0_pins[] = {
1032 	TEGRA_PIN_UFS0_REF_CLK_PFF0,
1033 };
1034 static const unsigned int ufs0_rst_pff1_pins[] = {
1035 	TEGRA_PIN_UFS0_RST_PFF1,
1036 };
1037 static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {
1038 	TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
1039 };
1040 static const unsigned int pex_l5_rst_n_pgg1_pins[] = {
1041 	TEGRA_PIN_PEX_L5_RST_N_PGG1,
1042 };
1043 static const unsigned int directdc_comp_pins[] = {
1044 	TEGRA_PIN_DIRECTDC_COMP,
1045 };
1046 static const unsigned int sdmmc4_clk_pins[] = {
1047 	TEGRA_PIN_SDMMC4_CLK,
1048 };
1049 static const unsigned int sdmmc4_cmd_pins[] = {
1050 	TEGRA_PIN_SDMMC4_CMD,
1051 };
1052 static const unsigned int sdmmc4_dqs_pins[] = {
1053 	TEGRA_PIN_SDMMC4_DQS,
1054 };
1055 static const unsigned int sdmmc4_dat7_pins[] = {
1056 	TEGRA_PIN_SDMMC4_DAT7,
1057 };
1058 static const unsigned int sdmmc4_dat6_pins[] = {
1059 	TEGRA_PIN_SDMMC4_DAT6,
1060 };
1061 static const unsigned int sdmmc4_dat5_pins[] = {
1062 	TEGRA_PIN_SDMMC4_DAT5,
1063 };
1064 static const unsigned int sdmmc4_dat4_pins[] = {
1065 	TEGRA_PIN_SDMMC4_DAT4,
1066 };
1067 static const unsigned int sdmmc4_dat3_pins[] = {
1068 	TEGRA_PIN_SDMMC4_DAT3,
1069 };
1070 static const unsigned int sdmmc4_dat2_pins[] = {
1071 	TEGRA_PIN_SDMMC4_DAT2,
1072 };
1073 static const unsigned int sdmmc4_dat1_pins[] = {
1074 	TEGRA_PIN_SDMMC4_DAT1,
1075 };
1076 static const unsigned int sdmmc4_dat0_pins[] = {
1077 	TEGRA_PIN_SDMMC4_DAT0,
1078 };
1079 static const unsigned int sdmmc1_comp_pins[] = {
1080 	TEGRA_PIN_SDMMC1_COMP,
1081 };
1082 static const unsigned int sdmmc3_comp_pins[] = {
1083 	TEGRA_PIN_SDMMC3_COMP,
1084 };
1085 static const unsigned int eqos_comp_pins[] = {
1086 	TEGRA_PIN_EQOS_COMP,
1087 };
1088 static const unsigned int qspi_comp_pins[] = {
1089 	TEGRA_PIN_QSPI_COMP,
1090 };
1091 static const unsigned int shutdown_n_pins[] = {
1092 	TEGRA_PIN_SHUTDOWN_N,
1093 };
1094 static const unsigned int pmu_int_n_pins[] = {
1095 	TEGRA_PIN_PMU_INT_N,
1096 };
1097 static const unsigned int soc_pwr_req_pins[] = {
1098 	TEGRA_PIN_SOC_PWR_REQ,
1099 };
1100 static const unsigned int clk_32k_in_pins[] = {
1101 	TEGRA_PIN_CLK_32K_IN,
1102 };
1103 
1104 /* Define unique ID for each function */
1105 enum tegra_mux_dt {
1106 	TEGRA_MUX_RSVD0,
1107 	TEGRA_MUX_RSVD1,
1108 	TEGRA_MUX_RSVD2,
1109 	TEGRA_MUX_RSVD3,
1110 	TEGRA_MUX_TOUCH,
1111 	TEGRA_MUX_UARTC,
1112 	TEGRA_MUX_I2C8,
1113 	TEGRA_MUX_UARTG,
1114 	TEGRA_MUX_SPI2,
1115 	TEGRA_MUX_GP,
1116 	TEGRA_MUX_DCA,
1117 	TEGRA_MUX_WDT,
1118 	TEGRA_MUX_I2C2,
1119 	TEGRA_MUX_CAN1,
1120 	TEGRA_MUX_CAN0,
1121 	TEGRA_MUX_DMIC3,
1122 	TEGRA_MUX_DMIC5,
1123 	TEGRA_MUX_GPIO,
1124 	TEGRA_MUX_DSPK1,
1125 	TEGRA_MUX_DSPK0,
1126 	TEGRA_MUX_SPDIF,
1127 	TEGRA_MUX_AUD,
1128 	TEGRA_MUX_I2S1,
1129 	TEGRA_MUX_DMIC1,
1130 	TEGRA_MUX_DMIC2,
1131 	TEGRA_MUX_I2S3,
1132 	TEGRA_MUX_DMIC4,
1133 	TEGRA_MUX_I2S4,
1134 	TEGRA_MUX_EXTPERIPH2,
1135 	TEGRA_MUX_EXTPERIPH1,
1136 	TEGRA_MUX_I2C3,
1137 	TEGRA_MUX_VGP1,
1138 	TEGRA_MUX_VGP2,
1139 	TEGRA_MUX_VGP3,
1140 	TEGRA_MUX_VGP4,
1141 	TEGRA_MUX_VGP5,
1142 	TEGRA_MUX_VGP6,
1143 	TEGRA_MUX_SLVS,
1144 	TEGRA_MUX_EXTPERIPH3,
1145 	TEGRA_MUX_EXTPERIPH4,
1146 	TEGRA_MUX_I2S2,
1147 	TEGRA_MUX_UARTD,
1148 	TEGRA_MUX_I2C1,
1149 	TEGRA_MUX_UARTA,
1150 	TEGRA_MUX_DIRECTDC1,
1151 	TEGRA_MUX_DIRECTDC,
1152 	TEGRA_MUX_IQC1,
1153 	TEGRA_MUX_IQC2,
1154 	TEGRA_MUX_I2S6,
1155 	TEGRA_MUX_SDMMC3,
1156 	TEGRA_MUX_SDMMC1,
1157 	TEGRA_MUX_DP,
1158 	TEGRA_MUX_HDMI,
1159 	TEGRA_MUX_PE2,
1160 	TEGRA_MUX_IGPU,
1161 	TEGRA_MUX_SATA,
1162 	TEGRA_MUX_PE1,
1163 	TEGRA_MUX_PE0,
1164 	TEGRA_MUX_PE3,
1165 	TEGRA_MUX_PE4,
1166 	TEGRA_MUX_PE5,
1167 	TEGRA_MUX_SOC,
1168 	TEGRA_MUX_EQOS,
1169 	TEGRA_MUX_QSPI,
1170 	TEGRA_MUX_QSPI0,
1171 	TEGRA_MUX_QSPI1,
1172 	TEGRA_MUX_MIPI,
1173 	TEGRA_MUX_SCE,
1174 	TEGRA_MUX_I2C5,
1175 	TEGRA_MUX_DISPLAYA,
1176 	TEGRA_MUX_DISPLAYB,
1177 	TEGRA_MUX_DCB,
1178 	TEGRA_MUX_SPI1,
1179 	TEGRA_MUX_UARTB,
1180 	TEGRA_MUX_UARTE,
1181 	TEGRA_MUX_SPI3,
1182 	TEGRA_MUX_NV,
1183 	TEGRA_MUX_CCLA,
1184 	TEGRA_MUX_I2S5,
1185 	TEGRA_MUX_USB,
1186 	TEGRA_MUX_UFS0,
1187 	TEGRA_MUX_DGPU,
1188 	TEGRA_MUX_SDMMC4,
1189 };
1190 
1191 /* Make list of each function name */
1192 #define TEGRA_PIN_FUNCTION(lid) #lid
1193 
1194 static const char * const tegra194_functions[] = {
1195 	TEGRA_PIN_FUNCTION(rsvd0),
1196 	TEGRA_PIN_FUNCTION(rsvd1),
1197 	TEGRA_PIN_FUNCTION(rsvd2),
1198 	TEGRA_PIN_FUNCTION(rsvd3),
1199 	TEGRA_PIN_FUNCTION(touch),
1200 	TEGRA_PIN_FUNCTION(uartc),
1201 	TEGRA_PIN_FUNCTION(i2c8),
1202 	TEGRA_PIN_FUNCTION(uartg),
1203 	TEGRA_PIN_FUNCTION(spi2),
1204 	TEGRA_PIN_FUNCTION(gp),
1205 	TEGRA_PIN_FUNCTION(dca),
1206 	TEGRA_PIN_FUNCTION(wdt),
1207 	TEGRA_PIN_FUNCTION(i2c2),
1208 	TEGRA_PIN_FUNCTION(can1),
1209 	TEGRA_PIN_FUNCTION(can0),
1210 	TEGRA_PIN_FUNCTION(dmic3),
1211 	TEGRA_PIN_FUNCTION(dmic5),
1212 	TEGRA_PIN_FUNCTION(gpio),
1213 	TEGRA_PIN_FUNCTION(dspk1),
1214 	TEGRA_PIN_FUNCTION(dspk0),
1215 	TEGRA_PIN_FUNCTION(spdif),
1216 	TEGRA_PIN_FUNCTION(aud),
1217 	TEGRA_PIN_FUNCTION(i2s1),
1218 	TEGRA_PIN_FUNCTION(dmic1),
1219 	TEGRA_PIN_FUNCTION(dmic2),
1220 	TEGRA_PIN_FUNCTION(i2s3),
1221 	TEGRA_PIN_FUNCTION(dmic4),
1222 	TEGRA_PIN_FUNCTION(i2s4),
1223 	TEGRA_PIN_FUNCTION(extperiph2),
1224 	TEGRA_PIN_FUNCTION(extperiph1),
1225 	TEGRA_PIN_FUNCTION(i2c3),
1226 	TEGRA_PIN_FUNCTION(vgp1),
1227 	TEGRA_PIN_FUNCTION(vgp2),
1228 	TEGRA_PIN_FUNCTION(vgp3),
1229 	TEGRA_PIN_FUNCTION(vgp4),
1230 	TEGRA_PIN_FUNCTION(vgp5),
1231 	TEGRA_PIN_FUNCTION(vgp6),
1232 	TEGRA_PIN_FUNCTION(slvs),
1233 	TEGRA_PIN_FUNCTION(extperiph3),
1234 	TEGRA_PIN_FUNCTION(extperiph4),
1235 	TEGRA_PIN_FUNCTION(i2s2),
1236 	TEGRA_PIN_FUNCTION(uartd),
1237 	TEGRA_PIN_FUNCTION(i2c1),
1238 	TEGRA_PIN_FUNCTION(uarta),
1239 	TEGRA_PIN_FUNCTION(directdc1),
1240 	TEGRA_PIN_FUNCTION(directdc),
1241 	TEGRA_PIN_FUNCTION(iqc1),
1242 	TEGRA_PIN_FUNCTION(iqc2),
1243 	TEGRA_PIN_FUNCTION(i2s6),
1244 	TEGRA_PIN_FUNCTION(sdmmc3),
1245 	TEGRA_PIN_FUNCTION(sdmmc1),
1246 	TEGRA_PIN_FUNCTION(dp),
1247 	TEGRA_PIN_FUNCTION(hdmi),
1248 	TEGRA_PIN_FUNCTION(pe2),
1249 	TEGRA_PIN_FUNCTION(igpu),
1250 	TEGRA_PIN_FUNCTION(sata),
1251 	TEGRA_PIN_FUNCTION(pe1),
1252 	TEGRA_PIN_FUNCTION(pe0),
1253 	TEGRA_PIN_FUNCTION(pe3),
1254 	TEGRA_PIN_FUNCTION(pe4),
1255 	TEGRA_PIN_FUNCTION(pe5),
1256 	TEGRA_PIN_FUNCTION(soc),
1257 	TEGRA_PIN_FUNCTION(eqos),
1258 	TEGRA_PIN_FUNCTION(qspi),
1259 	TEGRA_PIN_FUNCTION(qspi0),
1260 	TEGRA_PIN_FUNCTION(qspi1),
1261 	TEGRA_PIN_FUNCTION(mipi),
1262 	TEGRA_PIN_FUNCTION(sce),
1263 	TEGRA_PIN_FUNCTION(i2c5),
1264 	TEGRA_PIN_FUNCTION(displaya),
1265 	TEGRA_PIN_FUNCTION(displayb),
1266 	TEGRA_PIN_FUNCTION(dcb),
1267 	TEGRA_PIN_FUNCTION(spi1),
1268 	TEGRA_PIN_FUNCTION(uartb),
1269 	TEGRA_PIN_FUNCTION(uarte),
1270 	TEGRA_PIN_FUNCTION(spi3),
1271 	TEGRA_PIN_FUNCTION(nv),
1272 	TEGRA_PIN_FUNCTION(ccla),
1273 	TEGRA_PIN_FUNCTION(i2s5),
1274 	TEGRA_PIN_FUNCTION(usb),
1275 	TEGRA_PIN_FUNCTION(ufs0),
1276 	TEGRA_PIN_FUNCTION(dgpu),
1277 	TEGRA_PIN_FUNCTION(sdmmc4),
1278 
1279 };
1280 
1281 #define PINGROUP_REG_Y(r) ((r))
1282 #define PINGROUP_REG_N(r) -1
1283 
1284 #define DRV_PINGROUP_Y(r) ((r))
1285 #define DRV_PINGROUP_N(r) -1
1286 
1287 #define DRV_PINGROUP_ENTRY_N(pg_name)				\
1288 		.drv_reg = -1,					\
1289 		.drv_bank = -1,					\
1290 		.drvdn_bit = -1,				\
1291 		.drvup_bit = -1,				\
1292 		.slwr_bit = -1,					\
1293 		.slwf_bit = -1
1294 
1295 #define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b,	\
1296 			     drvup_w, slwr_b, slwr_w, slwf_b,	\
1297 			     slwf_w, bank)			\
1298 		.drv_reg = ((r)),				\
1299 		.drv_bank = bank,				\
1300 		.drvdn_bit = drvdn_b,				\
1301 		.drvdn_width = drvdn_w,				\
1302 		.drvup_bit = drvup_b,				\
1303 		.drvup_width = drvup_w,				\
1304 		.slwr_bit = slwr_b,				\
1305 		.slwr_width = slwr_w,				\
1306 		.slwf_bit = slwf_b,				\
1307 		.slwf_width = slwf_w
1308 
1309 #define PIN_PINGROUP_ENTRY_N(pg_name)				\
1310 		.mux_reg = -1,					\
1311 		.pupd_reg = -1,					\
1312 		.tri_reg = -1,					\
1313 		.einput_bit = -1,				\
1314 		.e_io_hv_bit = -1,				\
1315 		.odrain_bit = -1,				\
1316 		.lock_bit = -1,					\
1317 		.parked_bit = -1,				\
1318 		.lpmd_bit = -1,					\
1319 		.drvtype_bit = -1,				\
1320 		.lpdr_bit = -1,					\
1321 		.pbias_buf_bit = -1,				\
1322 		.preemp_bit = -1,				\
1323 		.rfu_in_bit = -1
1324 
1325 #define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input,	\
1326 			     e_lpdr, e_pbias_buf, gpio_sfio_sel, \
1327 			     e_od, schmitt_b, drvtype, epreemp,	\
1328 			     io_reset, rfu_in, io_rail)		\
1329 		.mux_reg = PINGROUP_REG_Y(r),			\
1330 		.lpmd_bit = -1,					\
1331 		.lock_bit = -1,					\
1332 		.hsm_bit = -1,					\
1333 		.mux_bank = bank,				\
1334 		.mux_bit = 0,					\
1335 		.pupd_reg = PINGROUP_REG_##pupd(r),		\
1336 		.pupd_bank = bank,				\
1337 		.pupd_bit = 2,					\
1338 		.tri_reg = PINGROUP_REG_Y(r),			\
1339 		.tri_bank = bank,				\
1340 		.tri_bit = 4,					\
1341 		.einput_bit = e_input,				\
1342 		.sfsel_bit = gpio_sfio_sel,			\
1343 		.odrain_bit = e_od,				\
1344 		.schmitt_bit = schmitt_b,			\
1345 		.drvtype_bit = 13,				\
1346 		.lpdr_bit = e_lpdr,				\
1347 
1348 /* main drive pin groups */
1349 #define drive_soc_gpio33_pt0            DRV_PINGROUP_ENTRY_Y(0x1004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1350 #define drive_soc_gpio32_ps7            DRV_PINGROUP_ENTRY_Y(0x100c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1351 #define drive_soc_gpio31_ps6            DRV_PINGROUP_ENTRY_Y(0x1014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1352 #define drive_soc_gpio30_ps5            DRV_PINGROUP_ENTRY_Y(0x101c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1353 #define drive_aud_mclk_ps4              DRV_PINGROUP_ENTRY_Y(0x1024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1354 #define drive_dap1_fs_ps3               DRV_PINGROUP_ENTRY_Y(0x102c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1355 #define drive_dap1_din_ps2              DRV_PINGROUP_ENTRY_Y(0x1034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1356 #define drive_dap1_dout_ps1             DRV_PINGROUP_ENTRY_Y(0x103c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1357 #define drive_dap1_sclk_ps0             DRV_PINGROUP_ENTRY_Y(0x1044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1358 #define drive_dap3_fs_pt4               DRV_PINGROUP_ENTRY_Y(0x104c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1359 #define drive_dap3_din_pt3              DRV_PINGROUP_ENTRY_Y(0x1054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1360 #define drive_dap3_dout_pt2             DRV_PINGROUP_ENTRY_Y(0x105c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1361 #define drive_dap3_sclk_pt1             DRV_PINGROUP_ENTRY_Y(0x1064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1362 #define drive_dap5_fs_pu0               DRV_PINGROUP_ENTRY_Y(0x106c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1363 #define drive_dap5_din_pt7              DRV_PINGROUP_ENTRY_Y(0x1074,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1364 #define drive_dap5_dout_pt6             DRV_PINGROUP_ENTRY_Y(0x107c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1365 #define drive_dap5_sclk_pt5             DRV_PINGROUP_ENTRY_Y(0x1084,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1366 #define drive_dap6_fs_pa3               DRV_PINGROUP_ENTRY_Y(0x2004,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1367 #define drive_dap6_din_pa2              DRV_PINGROUP_ENTRY_Y(0x200c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1368 #define drive_dap6_dout_pa1             DRV_PINGROUP_ENTRY_Y(0x2014,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1369 #define drive_dap6_sclk_pa0             DRV_PINGROUP_ENTRY_Y(0x201c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1370 #define drive_dap4_fs_pa7               DRV_PINGROUP_ENTRY_Y(0x2024,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1371 #define drive_dap4_din_pa6              DRV_PINGROUP_ENTRY_Y(0x202c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1372 #define drive_dap4_dout_pa5             DRV_PINGROUP_ENTRY_Y(0x2034,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1373 #define drive_dap4_sclk_pa4             DRV_PINGROUP_ENTRY_Y(0x203c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1374 #define drive_extperiph2_clk_pp1        DRV_PINGROUP_ENTRY_Y(0x0004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1375 #define drive_extperiph1_clk_pp0        DRV_PINGROUP_ENTRY_Y(0x000c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1376 #define drive_cam_i2c_sda_pp3           DRV_PINGROUP_ENTRY_Y(0x0014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1377 #define drive_cam_i2c_scl_pp2           DRV_PINGROUP_ENTRY_Y(0x001c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1378 #define drive_soc_gpio40_pq4            DRV_PINGROUP_ENTRY_Y(0x0024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1379 #define drive_soc_gpio41_pq5            DRV_PINGROUP_ENTRY_Y(0x002c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1380 #define drive_soc_gpio42_pq6            DRV_PINGROUP_ENTRY_Y(0x0034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1381 #define drive_soc_gpio43_pq7            DRV_PINGROUP_ENTRY_Y(0x003c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1382 #define drive_soc_gpio44_pr0            DRV_PINGROUP_ENTRY_Y(0x0044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1383 #define drive_soc_gpio45_pr1            DRV_PINGROUP_ENTRY_Y(0x004c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1384 #define drive_soc_gpio20_pq0            DRV_PINGROUP_ENTRY_Y(0x0054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1385 #define drive_soc_gpio21_pq1            DRV_PINGROUP_ENTRY_Y(0x005c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1386 #define drive_soc_gpio22_pq2            DRV_PINGROUP_ENTRY_Y(0x0064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1387 #define drive_soc_gpio23_pq3            DRV_PINGROUP_ENTRY_Y(0x006c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1388 #define drive_soc_gpio04_pp4            DRV_PINGROUP_ENTRY_Y(0x0074,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1389 #define drive_soc_gpio05_pp5            DRV_PINGROUP_ENTRY_Y(0x007c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1390 #define drive_soc_gpio06_pp6            DRV_PINGROUP_ENTRY_Y(0x0084,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1391 #define drive_soc_gpio07_pp7            DRV_PINGROUP_ENTRY_Y(0x008c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1392 #define drive_uart1_cts_pr5             DRV_PINGROUP_ENTRY_Y(0x0094,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1393 #define drive_uart1_rts_pr4             DRV_PINGROUP_ENTRY_Y(0x009c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1394 #define drive_uart1_rx_pr3              DRV_PINGROUP_ENTRY_Y(0x00a4,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1395 #define drive_uart1_tx_pr2              DRV_PINGROUP_ENTRY_Y(0x00ac,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1396 #define drive_dap2_din_pi1              DRV_PINGROUP_ENTRY_Y(0x4004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1397 #define drive_dap2_dout_pi0             DRV_PINGROUP_ENTRY_Y(0x400c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1398 #define drive_dap2_fs_pi2               DRV_PINGROUP_ENTRY_Y(0x4014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1399 #define drive_dap2_sclk_ph7             DRV_PINGROUP_ENTRY_Y(0x401c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1400 #define drive_uart4_cts_ph6             DRV_PINGROUP_ENTRY_Y(0x4024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1401 #define drive_uart4_rts_ph5             DRV_PINGROUP_ENTRY_Y(0x402c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1402 #define drive_uart4_rx_ph4              DRV_PINGROUP_ENTRY_Y(0x4034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1403 #define drive_uart4_tx_ph3              DRV_PINGROUP_ENTRY_Y(0x403c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1404 #define drive_soc_gpio03_pg3            DRV_PINGROUP_ENTRY_Y(0x4044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1405 #define drive_soc_gpio02_pg2            DRV_PINGROUP_ENTRY_Y(0x404c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1406 #define drive_soc_gpio01_pg1            DRV_PINGROUP_ENTRY_Y(0x4054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1407 #define drive_soc_gpio00_pg0            DRV_PINGROUP_ENTRY_Y(0x405c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1408 #define drive_gen1_i2c_scl_pi3          DRV_PINGROUP_ENTRY_Y(0x4064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1409 #define drive_gen1_i2c_sda_pi4          DRV_PINGROUP_ENTRY_Y(0x406c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1410 #define drive_soc_gpio08_pg4            DRV_PINGROUP_ENTRY_Y(0x4074,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1411 #define drive_soc_gpio09_pg5            DRV_PINGROUP_ENTRY_Y(0x407c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1412 #define drive_soc_gpio10_pg6            DRV_PINGROUP_ENTRY_Y(0x4084,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1413 #define drive_soc_gpio11_pg7            DRV_PINGROUP_ENTRY_Y(0x408c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1414 #define drive_soc_gpio12_ph0            DRV_PINGROUP_ENTRY_Y(0x4094,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1415 #define drive_soc_gpio13_ph1            DRV_PINGROUP_ENTRY_Y(0x409c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1416 #define drive_soc_gpio14_ph2            DRV_PINGROUP_ENTRY_Y(0x40a4,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1417 #define drive_soc_gpio50_pm5            DRV_PINGROUP_ENTRY_Y(0x10004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1418 #define drive_soc_gpio51_pm6            DRV_PINGROUP_ENTRY_Y(0x1000c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1419 #define drive_soc_gpio52_pm7            DRV_PINGROUP_ENTRY_Y(0x10014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1420 #define drive_soc_gpio53_pn0            DRV_PINGROUP_ENTRY_Y(0x1001c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1421 #define drive_soc_gpio54_pn1            DRV_PINGROUP_ENTRY_Y(0x10024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1422 #define drive_soc_gpio55_pn2            DRV_PINGROUP_ENTRY_Y(0x1002c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1423 #define drive_dp_aux_ch0_hpd_pm0        DRV_PINGROUP_ENTRY_Y(0x10034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1424 #define drive_dp_aux_ch1_hpd_pm1        DRV_PINGROUP_ENTRY_Y(0x1003c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1425 #define drive_dp_aux_ch2_hpd_pm2        DRV_PINGROUP_ENTRY_Y(0x10044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1426 #define drive_dp_aux_ch3_hpd_pm3        DRV_PINGROUP_ENTRY_Y(0x1004c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1427 #define drive_hdmi_cec_pm4              DRV_PINGROUP_ENTRY_Y(0x10054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1428 #define drive_pex_l2_clkreq_n_pk4       DRV_PINGROUP_ENTRY_Y(0x7004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1429 #define drive_pex_wake_n_pl2            DRV_PINGROUP_ENTRY_Y(0x700c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1430 #define drive_pex_l1_clkreq_n_pk2       DRV_PINGROUP_ENTRY_Y(0x7014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1431 #define drive_pex_l1_rst_n_pk3          DRV_PINGROUP_ENTRY_Y(0x701c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1432 #define drive_pex_l0_clkreq_n_pk0       DRV_PINGROUP_ENTRY_Y(0x7024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1433 #define drive_pex_l0_rst_n_pk1          DRV_PINGROUP_ENTRY_Y(0x702c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1434 #define drive_pex_l2_rst_n_pk5          DRV_PINGROUP_ENTRY_Y(0x7034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1435 #define drive_pex_l3_clkreq_n_pk6       DRV_PINGROUP_ENTRY_Y(0x703c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1436 #define drive_pex_l3_rst_n_pk7          DRV_PINGROUP_ENTRY_Y(0x7044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1437 #define drive_pex_l4_clkreq_n_pl0       DRV_PINGROUP_ENTRY_Y(0x704c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1438 #define drive_pex_l4_rst_n_pl1          DRV_PINGROUP_ENTRY_Y(0x7054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1439 #define drive_sata_dev_slp_pl3          DRV_PINGROUP_ENTRY_Y(0x705c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1440 #define drive_pex_l5_clkreq_n_pgg0      DRV_PINGROUP_ENTRY_Y(0x14004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1441 #define drive_pex_l5_rst_n_pgg1         DRV_PINGROUP_ENTRY_Y(0x1400c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1442 #define drive_cpu_pwr_req_1_pb1         DRV_PINGROUP_ENTRY_Y(0x16004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1443 #define drive_cpu_pwr_req_0_pb0         DRV_PINGROUP_ENTRY_Y(0x1600c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1444 #define drive_sdmmc1_clk_pj0            DRV_PINGROUP_ENTRY_Y(0x8004,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)
1445 #define drive_sdmmc1_cmd_pj1            DRV_PINGROUP_ENTRY_Y(0x800c,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)
1446 #define drive_sdmmc1_dat3_pj5           DRV_PINGROUP_ENTRY_Y(0x801c,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)
1447 #define drive_sdmmc1_dat2_pj4           DRV_PINGROUP_ENTRY_Y(0x8024,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)
1448 #define drive_sdmmc1_dat1_pj3           DRV_PINGROUP_ENTRY_Y(0x802c,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)
1449 #define drive_sdmmc1_dat0_pj2           DRV_PINGROUP_ENTRY_Y(0x8034,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)
1450 #define drive_sdmmc3_dat3_po5           DRV_PINGROUP_ENTRY_Y(0xa004,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)
1451 #define drive_sdmmc3_dat2_po4           DRV_PINGROUP_ENTRY_Y(0xa00c,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)
1452 #define drive_sdmmc3_dat1_po3           DRV_PINGROUP_ENTRY_Y(0xa014,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)
1453 #define drive_sdmmc3_dat0_po2           DRV_PINGROUP_ENTRY_Y(0xa01c,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)
1454 #define drive_sdmmc3_cmd_po1            DRV_PINGROUP_ENTRY_Y(0xa02c,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)
1455 #define drive_sdmmc3_clk_po0            DRV_PINGROUP_ENTRY_Y(0xa034,	-1,	-1,	-1,	-1,	28,	2,	30,	2,	0)
1456 #define drive_gpu_pwr_req_px0           DRV_PINGROUP_ENTRY_Y(0xD004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1457 #define drive_spi3_miso_py1             DRV_PINGROUP_ENTRY_Y(0xD00c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1458 #define drive_spi1_cs0_pz6              DRV_PINGROUP_ENTRY_Y(0xD014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1459 #define drive_spi3_cs0_py3              DRV_PINGROUP_ENTRY_Y(0xD01c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1460 #define drive_spi1_miso_pz4             DRV_PINGROUP_ENTRY_Y(0xD024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1461 #define drive_spi3_cs1_py4              DRV_PINGROUP_ENTRY_Y(0xD02c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1462 #define drive_gp_pwm3_px3               DRV_PINGROUP_ENTRY_Y(0xD034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1463 #define drive_gp_pwm2_px2               DRV_PINGROUP_ENTRY_Y(0xD03c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1464 #define drive_spi1_sck_pz3              DRV_PINGROUP_ENTRY_Y(0xD044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1465 #define drive_spi3_sck_py0              DRV_PINGROUP_ENTRY_Y(0xD04c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1466 #define drive_spi1_cs1_pz7              DRV_PINGROUP_ENTRY_Y(0xD054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1467 #define drive_spi1_mosi_pz5             DRV_PINGROUP_ENTRY_Y(0xD05c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1468 #define drive_spi3_mosi_py2             DRV_PINGROUP_ENTRY_Y(0xD064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1469 #define drive_cv_pwr_req_px1            DRV_PINGROUP_ENTRY_Y(0xD06c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1470 #define drive_uart2_tx_px4              DRV_PINGROUP_ENTRY_Y(0xD074,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1471 #define drive_uart2_rx_px5              DRV_PINGROUP_ENTRY_Y(0xD07c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1472 #define drive_uart2_rts_px6             DRV_PINGROUP_ENTRY_Y(0xD084,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1473 #define drive_uart2_cts_px7             DRV_PINGROUP_ENTRY_Y(0xD08c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1474 #define drive_uart5_rx_py6              DRV_PINGROUP_ENTRY_Y(0xD094,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1475 #define drive_uart5_tx_py5              DRV_PINGROUP_ENTRY_Y(0xD09c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1476 #define drive_uart5_rts_py7             DRV_PINGROUP_ENTRY_Y(0xD0a4,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1477 #define drive_uart5_cts_pz0             DRV_PINGROUP_ENTRY_Y(0xD0ac,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1478 #define drive_usb_vbus_en0_pz1          DRV_PINGROUP_ENTRY_Y(0xD0b4,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1479 #define drive_usb_vbus_en1_pz2          DRV_PINGROUP_ENTRY_Y(0xD0bc,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1480 #define drive_ufs0_rst_pff1             DRV_PINGROUP_ENTRY_Y(0x11004,	12,	9,	24,	8,	-1,	-1,	-1,	-1,	0)
1481 #define drive_ufs0_ref_clk_pff0         DRV_PINGROUP_ENTRY_Y(0x1100c,	12,	9,	24,	8,	-1,	-1,	-1,	-1,	0)
1482 
1483 #define drive_directdc_comp             DRV_PINGROUP_ENTRY_N(no_entry)
1484 #define drive_sdmmc1_comp               DRV_PINGROUP_ENTRY_N(no_entry)
1485 #define drive_eqos_comp                 DRV_PINGROUP_ENTRY_N(no_entry)
1486 #define drive_sdmmc3_comp               DRV_PINGROUP_ENTRY_N(no_entry)
1487 #define drive_sdmmc4_clk                DRV_PINGROUP_ENTRY_N(no_entry)
1488 #define drive_sdmmc4_cmd                DRV_PINGROUP_ENTRY_N(no_entry)
1489 #define drive_sdmmc4_dqs                DRV_PINGROUP_ENTRY_N(no_entry)
1490 #define drive_sdmmc4_dat7               DRV_PINGROUP_ENTRY_N(no_entry)
1491 #define drive_sdmmc4_dat6               DRV_PINGROUP_ENTRY_N(no_entry)
1492 #define drive_sdmmc4_dat5               DRV_PINGROUP_ENTRY_N(no_entry)
1493 #define drive_sdmmc4_dat4               DRV_PINGROUP_ENTRY_N(no_entry)
1494 #define drive_sdmmc4_dat3               DRV_PINGROUP_ENTRY_N(no_entry)
1495 #define drive_sdmmc4_dat2               DRV_PINGROUP_ENTRY_N(no_entry)
1496 #define drive_sdmmc4_dat1               DRV_PINGROUP_ENTRY_N(no_entry)
1497 #define drive_sdmmc4_dat0               DRV_PINGROUP_ENTRY_N(no_entry)
1498 #define drive_qspi_comp                 DRV_PINGROUP_ENTRY_N(no_entry)
1499 #define drive_qspi1_cs_n_pc7            DRV_PINGROUP_ENTRY_N(no_entry)
1500 #define drive_qspi1_sck_pc6             DRV_PINGROUP_ENTRY_N(no_entry)
1501 #define drive_qspi1_io0_pd0             DRV_PINGROUP_ENTRY_N(no_entry)
1502 #define drive_qspi1_io1_pd1             DRV_PINGROUP_ENTRY_N(no_entry)
1503 #define drive_qspi1_io2_pd2             DRV_PINGROUP_ENTRY_N(no_entry)
1504 #define drive_qspi1_io3_pd3             DRV_PINGROUP_ENTRY_N(no_entry)
1505 #define drive_qspi0_io0_pc2             DRV_PINGROUP_ENTRY_N(no_entry)
1506 #define drive_qspi0_io1_pc3             DRV_PINGROUP_ENTRY_N(no_entry)
1507 #define drive_qspi0_io2_pc4             DRV_PINGROUP_ENTRY_N(no_entry)
1508 #define drive_qspi0_io3_pc5             DRV_PINGROUP_ENTRY_N(no_entry)
1509 #define drive_qspi0_cs_n_pc1            DRV_PINGROUP_ENTRY_N(no_entry)
1510 #define drive_qspi0_sck_pc0             DRV_PINGROUP_ENTRY_N(no_entry)
1511 #define drive_eqos_rx_ctl_pf2           DRV_PINGROUP_ENTRY_N(no_entry)
1512 #define drive_eqos_tx_ctl_pe5           DRV_PINGROUP_ENTRY_N(no_entry)
1513 #define drive_eqos_rxc_pf3              DRV_PINGROUP_ENTRY_N(no_entry)
1514 #define drive_eqos_txc_pe0              DRV_PINGROUP_ENTRY_N(no_entry)
1515 #define drive_eqos_sma_mdc_pf5          DRV_PINGROUP_ENTRY_N(no_entry)
1516 #define drive_eqos_sma_mdio_pf4         DRV_PINGROUP_ENTRY_N(no_entry)
1517 #define drive_eqos_rd0_pe6              DRV_PINGROUP_ENTRY_N(no_entry)
1518 #define drive_eqos_rd1_pe7              DRV_PINGROUP_ENTRY_N(no_entry)
1519 #define drive_eqos_rd2_pf0              DRV_PINGROUP_ENTRY_N(no_entry)
1520 #define drive_eqos_rd3_pf1              DRV_PINGROUP_ENTRY_N(no_entry)
1521 #define drive_eqos_td0_pe1              DRV_PINGROUP_ENTRY_N(no_entry)
1522 #define drive_eqos_td1_pe2              DRV_PINGROUP_ENTRY_N(no_entry)
1523 #define drive_eqos_td2_pe3              DRV_PINGROUP_ENTRY_N(no_entry)
1524 #define drive_eqos_td3_pe4              DRV_PINGROUP_ENTRY_N(no_entry)
1525 #define drive_directdc1_out7_pw1        DRV_PINGROUP_ENTRY_N(no_entry)
1526 #define drive_directdc1_out6_pw0        DRV_PINGROUP_ENTRY_N(no_entry)
1527 #define drive_directdc1_out5_pv7        DRV_PINGROUP_ENTRY_N(no_entry)
1528 #define drive_directdc1_out4_pv6        DRV_PINGROUP_ENTRY_N(no_entry)
1529 #define drive_directdc1_out3_pv5        DRV_PINGROUP_ENTRY_N(no_entry)
1530 #define drive_directdc1_out2_pv4        DRV_PINGROUP_ENTRY_N(no_entry)
1531 #define drive_directdc1_out1_pv3        DRV_PINGROUP_ENTRY_N(no_entry)
1532 #define drive_directdc1_out0_pv2        DRV_PINGROUP_ENTRY_N(no_entry)
1533 #define drive_directdc1_in_pv1          DRV_PINGROUP_ENTRY_N(no_entry)
1534 #define drive_directdc1_clk_pv0         DRV_PINGROUP_ENTRY_N(no_entry)
1535 
1536 /* AON drive pin groups */
1537 #define drive_shutdown_n                DRV_PINGROUP_ENTRY_Y(0x1004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1538 #define drive_pmu_int_n                 DRV_PINGROUP_ENTRY_Y(0x100c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1539 #define drive_safe_state_pee0           DRV_PINGROUP_ENTRY_Y(0x1014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1540 #define drive_vcomp_alert_pee1          DRV_PINGROUP_ENTRY_Y(0x101c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1541 #define drive_soc_pwr_req               DRV_PINGROUP_ENTRY_Y(0x1024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1542 #define drive_batt_oc_pee3              DRV_PINGROUP_ENTRY_Y(0x102c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1543 #define drive_clk_32k_in                DRV_PINGROUP_ENTRY_Y(0x1034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1544 #define drive_power_on_pee4             DRV_PINGROUP_ENTRY_Y(0x103c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1545 #define drive_pwr_i2c_scl_pee5          DRV_PINGROUP_ENTRY_Y(0x1044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1546 #define drive_pwr_i2c_sda_pee6          DRV_PINGROUP_ENTRY_Y(0x104c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1547 #define drive_ao_retention_n_pee2       DRV_PINGROUP_ENTRY_Y(0x1064,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1548 #define drive_touch_clk_pcc4            DRV_PINGROUP_ENTRY_Y(0x2004,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1549 #define drive_uart3_rx_pcc6             DRV_PINGROUP_ENTRY_Y(0x200c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1550 #define drive_uart3_tx_pcc5             DRV_PINGROUP_ENTRY_Y(0x2014,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1551 #define drive_gen8_i2c_sda_pdd2         DRV_PINGROUP_ENTRY_Y(0x201c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1552 #define drive_gen8_i2c_scl_pdd1         DRV_PINGROUP_ENTRY_Y(0x2024,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1553 #define drive_spi2_mosi_pcc2            DRV_PINGROUP_ENTRY_Y(0x202c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1554 #define drive_gen2_i2c_scl_pcc7         DRV_PINGROUP_ENTRY_Y(0x2034,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1555 #define drive_spi2_cs0_pcc3             DRV_PINGROUP_ENTRY_Y(0x203c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1556 #define drive_gen2_i2c_sda_pdd0         DRV_PINGROUP_ENTRY_Y(0x2044,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1557 #define drive_spi2_sck_pcc0             DRV_PINGROUP_ENTRY_Y(0x204c,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1558 #define drive_spi2_miso_pcc1            DRV_PINGROUP_ENTRY_Y(0x2054,	12,	5,	20,	5,	-1,	-1,	-1,	-1,	0)
1559 #define drive_can1_dout_paa0            DRV_PINGROUP_ENTRY_Y(0x3004,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1560 #define drive_can1_din_paa1             DRV_PINGROUP_ENTRY_Y(0x300c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1561 #define drive_can0_dout_paa2            DRV_PINGROUP_ENTRY_Y(0x3014,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1562 #define drive_can0_din_paa3             DRV_PINGROUP_ENTRY_Y(0x301c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1563 #define drive_can0_stb_paa4             DRV_PINGROUP_ENTRY_Y(0x3024,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1564 #define drive_can0_en_paa5              DRV_PINGROUP_ENTRY_Y(0x302c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1565 #define drive_can0_wake_paa6            DRV_PINGROUP_ENTRY_Y(0x3034,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1566 #define drive_can0_err_paa7             DRV_PINGROUP_ENTRY_Y(0x303c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1567 #define drive_can1_stb_pbb0             DRV_PINGROUP_ENTRY_Y(0x3044,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1568 #define drive_can1_en_pbb1              DRV_PINGROUP_ENTRY_Y(0x304c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1569 #define drive_can1_wake_pbb2            DRV_PINGROUP_ENTRY_Y(0x3054,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1570 #define drive_can1_err_pbb3             DRV_PINGROUP_ENTRY_Y(0x305c,	28,	2,	30,	2,	-1,	-1,	-1,	-1,	0)
1571 
1572 #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \
1573 			gpio_sfio_sel, e_od, schmitt_b, drvtype, epreemp, io_reset, rfu_in, io_rail)	\
1574 	{							\
1575 		.name = #pg_name,				\
1576 		.pins = pg_name##_pins,				\
1577 		.npins = ARRAY_SIZE(pg_name##_pins),		\
1578 			.funcs = {				\
1579 				TEGRA_MUX_##f0,			\
1580 				TEGRA_MUX_##f1,			\
1581 				TEGRA_MUX_##f2,			\
1582 				TEGRA_MUX_##f3,			\
1583 			},					\
1584 		PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk,	\
1585 				     e_input, e_lpdr, e_pbias_buf, \
1586 				     gpio_sfio_sel, e_od,	\
1587 				     schmitt_b, drvtype,	\
1588 				     epreemp, io_reset,		\
1589 				     rfu_in, io_rail)		\
1590 		drive_##pg_name,				\
1591 	}
1592 
1593 static const struct tegra_pingroup tegra194_groups[] = {
1594 	PINGROUP(soc_gpio33_pt0,	RSVD0,		SPDIF,		RSVD2,		RSVD3,		0x1000,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1595 	PINGROUP(soc_gpio32_ps7,	RSVD0,		SPDIF,		RSVD2,		RSVD3,		0x1008,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1596 	PINGROUP(soc_gpio31_ps6,	RSVD0,		SDMMC1,		RSVD2,		RSVD3,		0x1010,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1597 	PINGROUP(soc_gpio30_ps5,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1018,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1598 	PINGROUP(aud_mclk_ps4,		AUD,		RSVD1,		RSVD2,		RSVD3,		0x1020,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1599 	PINGROUP(dap1_fs_ps3,		I2S1,		RSVD1,		RSVD2,		RSVD3,		0x1028,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1600 	PINGROUP(dap1_din_ps2,		I2S1,		RSVD1,		RSVD2,		RSVD3,		0x1030,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1601 	PINGROUP(dap1_dout_ps1,		I2S1,		RSVD1,		RSVD2,		RSVD3,		0x1038,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1602 	PINGROUP(dap1_sclk_ps0,		I2S1,		RSVD1,		RSVD2,		RSVD3,		0x1040,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1603 	PINGROUP(dap3_fs_pt4,		I2S3,		DMIC2,		RSVD2,		RSVD3,		0x1048,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1604 	PINGROUP(dap3_din_pt3,		I2S3,		DMIC2,		RSVD2,		RSVD3,		0x1050,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1605 	PINGROUP(dap3_dout_pt2,		I2S3,		DMIC1,		RSVD2,		RSVD3,		0x1058,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1606 	PINGROUP(dap3_sclk_pt1,		I2S3,		DMIC1,		RSVD2,		RSVD3,		0x1060,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1607 	PINGROUP(dap5_fs_pu0,		I2S5,		DMIC4,		DSPK1,		RSVD3,		0x1068,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1608 	PINGROUP(dap5_din_pt7,		I2S5,		DMIC4,		DSPK1,		RSVD3,		0x1070,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1609 	PINGROUP(dap5_dout_pt6,		I2S5,		DSPK0,		RSVD2,		RSVD3,		0x1078,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1610 	PINGROUP(dap5_sclk_pt5,		I2S5,		DSPK0,		RSVD2,		RSVD3,		0x1080,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_audio"),
1611 	PINGROUP(dap6_fs_pa3,		I2S6,		IQC1,		RSVD2,		RSVD3,		0x2000,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),
1612 	PINGROUP(dap6_din_pa2,		I2S6,		IQC1,		RSVD2,		RSVD3,		0x2008,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),
1613 	PINGROUP(dap6_dout_pa1,		I2S6,		IQC1,		RSVD2,		RSVD3,		0x2010,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),
1614 	PINGROUP(dap6_sclk_pa0,		I2S6,		IQC1,		RSVD2,		RSVD3,		0x2018,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),
1615 	PINGROUP(dap4_fs_pa7,		I2S4,		IQC2,		RSVD2,		RSVD3,		0x2020,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),
1616 	PINGROUP(dap4_din_pa6,		I2S4,		IQC2,		RSVD2,		RSVD3,		0x2028,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),
1617 	PINGROUP(dap4_dout_pa5,		I2S4,		IQC2,		RSVD2,		RSVD3,		0x2030,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),
1618 	PINGROUP(dap4_sclk_pa4,		I2S4,		IQC2,		RSVD2,		RSVD3,		0x2038,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_audio_hv"),
1619 	PINGROUP(extperiph2_clk_pp1,	EXTPERIPH2,	RSVD1,		RSVD2,		RSVD3,		0x0000,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1620 	PINGROUP(extperiph1_clk_pp0,	EXTPERIPH1,	RSVD1,		RSVD2,		RSVD3,		0x0008,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1621 	PINGROUP(cam_i2c_sda_pp3,	I2C3,		RSVD1,		RSVD2,		RSVD3,		0x0010,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1622 	PINGROUP(cam_i2c_scl_pp2,	I2C3,		RSVD1,		RSVD2,		RSVD3,		0x0018,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1623 	PINGROUP(soc_gpio40_pq4,	VGP1,		SLVS,		RSVD2,		RSVD3,		0x0020,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1624 	PINGROUP(soc_gpio41_pq5,	VGP2,		EXTPERIPH3,	RSVD2,		RSVD3,		0x0028,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1625 	PINGROUP(soc_gpio42_pq6,	VGP3,		EXTPERIPH4,	RSVD2,		RSVD3,		0x0030,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1626 	PINGROUP(soc_gpio43_pq7,	VGP4,		SLVS,		RSVD2,		RSVD3,		0x0038,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1627 	PINGROUP(soc_gpio44_pr0,	VGP5,		GP,		RSVD2,		RSVD3,		0x0040,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1628 	PINGROUP(soc_gpio45_pr1,	VGP6,		RSVD1,		RSVD2,		RSVD3,		0x0048,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1629 	PINGROUP(soc_gpio20_pq0,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x0050,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1630 	PINGROUP(soc_gpio21_pq1,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x0058,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1631 	PINGROUP(soc_gpio22_pq2,	RSVD0,		NV,		RSVD2,		RSVD3,		0x0060,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1632 	PINGROUP(soc_gpio23_pq3,	RSVD0,		WDT,		RSVD2,		RSVD3,		0x0068,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1633 	PINGROUP(soc_gpio04_pp4,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x0070,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1634 	PINGROUP(soc_gpio05_pp5,	RSVD0,		IGPU,		RSVD2,		RSVD3,		0x0078,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1635 	PINGROUP(soc_gpio06_pp6,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x0080,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1636 	PINGROUP(soc_gpio07_pp7,	RSVD0,		SATA,		SOC,		RSVD3,		0x0088,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1637 	PINGROUP(uart1_cts_pr5,		UARTA,		RSVD1,		RSVD2,		RSVD3,		0x0090,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1638 	PINGROUP(uart1_rts_pr4,		UARTA,		RSVD1,		RSVD2,		RSVD3,		0x0098,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1639 	PINGROUP(uart1_rx_pr3,		UARTA,		RSVD1,		RSVD2,		RSVD3,		0x00a0,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1640 	PINGROUP(uart1_tx_pr2,		UARTA,		RSVD1,		RSVD2,		RSVD3,		0x00a8,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_cam"),
1641 	PINGROUP(dap2_din_pi1,		I2S2,		RSVD1,		RSVD2,		RSVD3,		0x4000,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1642 	PINGROUP(dap2_dout_pi0,		I2S2,		RSVD1,		RSVD2,		RSVD3,		0x4008,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1643 	PINGROUP(dap2_fs_pi2,		I2S2,		RSVD1,		RSVD2,		RSVD3,		0x4010,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1644 	PINGROUP(dap2_sclk_ph7,		I2S2,		RSVD1,		RSVD2,		RSVD3,		0x4018,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1645 	PINGROUP(uart4_cts_ph6,		UARTD,		RSVD1,		RSVD2,		RSVD3,		0x4020,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1646 	PINGROUP(uart4_rts_ph5,		UARTD,		RSVD1,		RSVD2,		RSVD3,		0x4028,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1647 	PINGROUP(uart4_rx_ph4,		UARTD,		RSVD1,		RSVD2,		RSVD3,		0x4030,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1648 	PINGROUP(uart4_tx_ph3,		UARTD,		RSVD1,		RSVD2,		RSVD3,		0x4038,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1649 	PINGROUP(soc_gpio03_pg3,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x4040,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1650 	PINGROUP(soc_gpio02_pg2,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x4048,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1651 	PINGROUP(soc_gpio01_pg1,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x4050,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1652 	PINGROUP(soc_gpio00_pg0,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x4058,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1653 	PINGROUP(gen1_i2c_scl_pi3,	I2C1,		RSVD1,		RSVD2,		RSVD3,		0x4060,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1654 	PINGROUP(gen1_i2c_sda_pi4,	I2C1,		RSVD1,		RSVD2,		RSVD3,		0x4068,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1655 	PINGROUP(soc_gpio08_pg4,	RSVD0,		CCLA,		RSVD2,		RSVD3,		0x4070,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1656 	PINGROUP(soc_gpio09_pg5,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x4078,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1657 	PINGROUP(soc_gpio10_pg6,	GP,		RSVD1,		RSVD2,		RSVD3,		0x4080,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1658 	PINGROUP(soc_gpio11_pg7,	RSVD0,		SDMMC1,		RSVD2,		RSVD3,		0x4088,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1659 	PINGROUP(soc_gpio12_ph0,	RSVD0,		GP,		RSVD2,		RSVD3,		0x4090,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1660 	PINGROUP(soc_gpio13_ph1,	RSVD0,		GP,		RSVD2,		RSVD3,		0x4098,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1661 	PINGROUP(soc_gpio14_ph2,	RSVD0,		SDMMC1,		RSVD2,		RSVD3,		0x40a0,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_conn"),
1662 	PINGROUP(directdc1_out7_pw1,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5008,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),
1663 	PINGROUP(directdc1_out6_pw0,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5010,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),
1664 	PINGROUP(directdc1_out5_pv7,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5018,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),
1665 	PINGROUP(directdc1_out4_pv6,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5020,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),
1666 	PINGROUP(directdc1_out3_pv5,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5028,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),
1667 	PINGROUP(directdc1_out2_pv4,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5030,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),
1668 	PINGROUP(directdc1_out1_pv3,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5038,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),
1669 	PINGROUP(directdc1_out0_pv2,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5040,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),
1670 	PINGROUP(directdc1_in_pv1,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5048,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),
1671 	PINGROUP(directdc1_clk_pv0,	DIRECTDC1,	RSVD1,		RSVD2,		RSVD3,		0x5050,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_debug"),
1672 	PINGROUP(directdc_comp,		DIRECTDC,	RSVD1,		RSVD2,		RSVD3,		0x5058,		0,	N,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	Y,	"vddio_debug"),
1673 	PINGROUP(soc_gpio50_pm5,	RSVD0,		DCA,		RSVD2,		RSVD3,		0x10000,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),
1674 	PINGROUP(soc_gpio51_pm6,	RSVD0,		DCA,		RSVD2,		RSVD3,		0x10008,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),
1675 	PINGROUP(soc_gpio52_pm7,	RSVD0,		DCB,		DGPU,		RSVD3,		0x10010,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),
1676 	PINGROUP(soc_gpio53_pn0,	RSVD0,		DCB,		RSVD2,		RSVD3,		0x10018,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),
1677 	PINGROUP(soc_gpio54_pn1,	RSVD0,		SDMMC3,		GP,		RSVD3,		0x10020,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),
1678 	PINGROUP(soc_gpio55_pn2,	RSVD0,		SDMMC3,		RSVD2,		RSVD3,		0x10028,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),
1679 	PINGROUP(dp_aux_ch0_hpd_pm0,	DP,		RSVD1,		RSVD2,		RSVD3,		0x10030,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),
1680 	PINGROUP(dp_aux_ch1_hpd_pm1,	DP,		RSVD1,		RSVD2,		RSVD3,		0x10038,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),
1681 	PINGROUP(dp_aux_ch2_hpd_pm2,	DP,		DISPLAYA,	RSVD2,		RSVD3,		0x10040,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),
1682 	PINGROUP(dp_aux_ch3_hpd_pm3,	DP,		DISPLAYB,	RSVD2,		RSVD3,		0x10048,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),
1683 	PINGROUP(hdmi_cec_pm4,		HDMI,		RSVD1,		RSVD2,		RSVD3,		0x10050,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_edp"),
1684 	PINGROUP(eqos_td3_pe4,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15000,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1685 	PINGROUP(eqos_td2_pe3,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15008,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1686 	PINGROUP(eqos_td1_pe2,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15010,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1687 	PINGROUP(eqos_td0_pe1,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15018,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1688 	PINGROUP(eqos_rd3_pf1,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15020,	0,	Y,	-1,	5,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1689 	PINGROUP(eqos_rd2_pf0,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15028,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1690 	PINGROUP(eqos_rd1_pe7,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15030,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1691 	PINGROUP(eqos_sma_mdio_pf4,	EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15038,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1692 	PINGROUP(eqos_rd0_pe6,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15040,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1693 	PINGROUP(eqos_sma_mdc_pf5,	EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15048,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1694 	PINGROUP(eqos_comp,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15050,	0,	N,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	Y,	"vddio_eqos"),
1695 	PINGROUP(eqos_txc_pe0,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15058,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1696 	PINGROUP(eqos_rxc_pf3,		EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15060,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1697 	PINGROUP(eqos_tx_ctl_pe5,	EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15068,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1698 	PINGROUP(eqos_rx_ctl_pf2,	EQOS,		RSVD1,		RSVD2,		RSVD3,		0x15070,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_eqos"),
1699 	PINGROUP(pex_l2_clkreq_n_pk4,	PE2,		RSVD1,		RSVD2,		RSVD3,		0x7000,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),
1700 	PINGROUP(pex_wake_n_pl2,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x7008,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),
1701 	PINGROUP(pex_l1_clkreq_n_pk2,	PE1,		RSVD1,		RSVD2,		RSVD3,		0x7010,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),
1702 	PINGROUP(pex_l1_rst_n_pk3,	PE1,		RSVD1,		RSVD2,		RSVD3,		0x7018,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),
1703 	PINGROUP(pex_l0_clkreq_n_pk0,	PE0,		RSVD1,		RSVD2,		RSVD3,		0x7020,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),
1704 	PINGROUP(pex_l0_rst_n_pk1,	PE0,		RSVD1,		RSVD2,		RSVD3,		0x7028,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),
1705 	PINGROUP(pex_l2_rst_n_pk5,	PE2,		RSVD1,		RSVD2,		RSVD3,		0x7030,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),
1706 	PINGROUP(pex_l3_clkreq_n_pk6,	PE3,		RSVD1,		RSVD2,		RSVD3,		0x7038,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),
1707 	PINGROUP(pex_l3_rst_n_pk7,	PE3,		RSVD1,		RSVD2,		RSVD3,		0x7040,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),
1708 	PINGROUP(pex_l4_clkreq_n_pl0,	PE4,		RSVD1,		RSVD2,		RSVD3,		0x7048,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),
1709 	PINGROUP(pex_l4_rst_n_pl1,	PE4,		RSVD1,		RSVD2,		RSVD3,		0x7050,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),
1710 	PINGROUP(sata_dev_slp_pl3,	SATA,		RSVD1,		RSVD2,		RSVD3,		0x7058,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl"),
1711 	PINGROUP(pex_l5_clkreq_n_pgg0,	PE5,		RSVD1,		RSVD2,		RSVD3,		0x14000,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl_2"),
1712 	PINGROUP(pex_l5_rst_n_pgg1,	PE5,		RSVD1,		RSVD2,		RSVD3,		0x14008,	0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pex_ctl_2"),
1713 	PINGROUP(cpu_pwr_req_1_pb1,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x16000,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pwr_ctl"),
1714 	PINGROUP(cpu_pwr_req_0_pb0,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x16008,	0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_pwr_ctl"),
1715 	PINGROUP(qspi0_io3_pc5,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB000,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),
1716 	PINGROUP(qspi0_io2_pc4,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB008,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),
1717 	PINGROUP(qspi0_io1_pc3,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB010,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),
1718 	PINGROUP(qspi0_io0_pc2,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB018,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),
1719 	PINGROUP(qspi0_sck_pc0,		QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB020,		0,	Y,	-1,	5,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),
1720 	PINGROUP(qspi0_cs_n_pc1,	QSPI0,		RSVD1,		RSVD2,		RSVD3,		0xB028,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),
1721 	PINGROUP(qspi1_io3_pd3,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB030,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),
1722 	PINGROUP(qspi1_io2_pd2,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB038,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),
1723 	PINGROUP(qspi1_io1_pd1,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB040,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),
1724 	PINGROUP(qspi1_io0_pd0,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB048,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),
1725 	PINGROUP(qspi1_sck_pc6,		QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB050,		0,	Y,	-1,	5,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),
1726 	PINGROUP(qspi1_cs_n_pc7,	QSPI1,		RSVD1,		RSVD2,		RSVD3,		0xB058,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_qspi"),
1727 	PINGROUP(qspi_comp,		QSPI,		RSVD1,		RSVD2,		RSVD3,		0xB060,		0,	N,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	Y,	"vddio_qspi"),
1728 	PINGROUP(sdmmc1_clk_pj0,	SDMMC1,		RSVD1,		MIPI,		RSVD3,		0x8000,		0,	Y,	-1,	5,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc1_hv"),
1729 	PINGROUP(sdmmc1_cmd_pj1,	SDMMC1,		RSVD1,		MIPI,		RSVD3,		0x8008,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc1_hv"),
1730 	PINGROUP(sdmmc1_comp,		SDMMC1,		RSVD1,		RSVD2,		RSVD3,		0x8010,		0,	N,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	N,	-1,	-1,	N,	"vddio_sdmmc1_hv"),
1731 	PINGROUP(sdmmc1_dat3_pj5,	SDMMC1,		RSVD1,		MIPI,		RSVD3,		0x8018,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc1_hv"),
1732 	PINGROUP(sdmmc1_dat2_pj4,	SDMMC1,		RSVD1,		MIPI,		RSVD3,		0x8020,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc1_hv"),
1733 	PINGROUP(sdmmc1_dat1_pj3,	SDMMC1,		RSVD1,		MIPI,		RSVD3,		0x8028,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc1_hv"),
1734 	PINGROUP(sdmmc1_dat0_pj2,	SDMMC1,		RSVD1,		MIPI,		RSVD3,		0x8030,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc1_hv"),
1735 	PINGROUP(sdmmc3_dat3_po5,	SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA000,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc3_hv"),
1736 	PINGROUP(sdmmc3_dat2_po4,	SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA008,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc3_hv"),
1737 	PINGROUP(sdmmc3_dat1_po3,	SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA010,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc3_hv"),
1738 	PINGROUP(sdmmc3_dat0_po2,	SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA018,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc3_hv"),
1739 	PINGROUP(sdmmc3_comp,		SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA020,		0,	N,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	-1,	N,	-1,	-1,	N,	"vddio_sdmmc3_hv"),
1740 	PINGROUP(sdmmc3_cmd_po1,	SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA028,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc3_hv"),
1741 	PINGROUP(sdmmc3_clk_po0,	SDMMC3,		RSVD1,		RSVD2,		RSVD3,		0xA030,		0,	Y,	-1,	5,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_sdmmc3_hv"),
1742 	PINGROUP(sdmmc4_clk,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6008,		0,	Y,	-1,	5,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),
1743 	PINGROUP(sdmmc4_cmd,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6010,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),
1744 	PINGROUP(sdmmc4_dqs,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6018,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	N,	-1,	-1,	N,	"vddio_sdmmc4"),
1745 	PINGROUP(sdmmc4_dat7,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6020,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),
1746 	PINGROUP(sdmmc4_dat6,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6028,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),
1747 	PINGROUP(sdmmc4_dat5,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6030,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),
1748 	PINGROUP(sdmmc4_dat4,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6038,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),
1749 	PINGROUP(sdmmc4_dat3,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6040,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),
1750 	PINGROUP(sdmmc4_dat2,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6048,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),
1751 	PINGROUP(sdmmc4_dat1,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6050,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),
1752 	PINGROUP(sdmmc4_dat0,		SDMMC4,		RSVD1,		RSVD2,		RSVD3,		0x6058,		0,	Y,	-1,	-1,	6,	-1,	-1,	-1,	-1,	-1,	Y,	-1,	-1,	N,	"vddio_sdmmc4"),
1753 	PINGROUP(gpu_pwr_req_px0,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0xD000,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1754 	PINGROUP(spi3_miso_py1,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD008,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1755 	PINGROUP(spi1_cs0_pz6,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD010,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1756 	PINGROUP(spi3_cs0_py3,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD018,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1757 	PINGROUP(spi1_miso_pz4,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD020,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1758 	PINGROUP(spi3_cs1_py4,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD028,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1759 	PINGROUP(gp_pwm3_px3,		GP,		RSVD1,		RSVD2,		RSVD3,		0xD030,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1760 	PINGROUP(gp_pwm2_px2,		GP,		RSVD1,		RSVD2,		RSVD3,		0xD038,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1761 	PINGROUP(spi1_sck_pz3,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD040,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1762 	PINGROUP(spi3_sck_py0,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD048,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1763 	PINGROUP(spi1_cs1_pz7,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD050,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1764 	PINGROUP(spi1_mosi_pz5,		SPI1,		RSVD1,		RSVD2,		RSVD3,		0xD058,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1765 	PINGROUP(spi3_mosi_py2,		SPI3,		RSVD1,		RSVD2,		RSVD3,		0xD060,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1766 	PINGROUP(cv_pwr_req_px1,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0xD068,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1767 	PINGROUP(uart2_tx_px4,		UARTB,		RSVD1,		RSVD2,		RSVD3,		0xD070,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1768 	PINGROUP(uart2_rx_px5,		UARTB,		RSVD1,		RSVD2,		RSVD3,		0xD078,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1769 	PINGROUP(uart2_rts_px6,		UARTB,		RSVD1,		RSVD2,		RSVD3,		0xD080,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1770 	PINGROUP(uart2_cts_px7,		UARTB,		RSVD1,		RSVD2,		RSVD3,		0xD088,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1771 	PINGROUP(uart5_rx_py6,		UARTE,		RSVD1,		RSVD2,		RSVD3,		0xD090,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1772 	PINGROUP(uart5_tx_py5,		UARTE,		RSVD1,		RSVD2,		RSVD3,		0xD098,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1773 	PINGROUP(uart5_rts_py7,		UARTE,		RSVD1,		RSVD2,		RSVD3,		0xD0a0,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1774 	PINGROUP(uart5_cts_pz0,		UARTE,		RSVD1,		RSVD2,		RSVD3,		0xD0a8,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1775 	PINGROUP(usb_vbus_en0_pz1,	USB,		RSVD1,		RSVD2,		RSVD3,		0xD0b0,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1776 	PINGROUP(usb_vbus_en1_pz2,	USB,		RSVD1,		RSVD2,		RSVD3,		0xD0b8,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_uart"),
1777 	PINGROUP(ufs0_rst_pff1,		UFS0,		RSVD1,		RSVD2,		RSVD3,		0x11000,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_ufs"),
1778 	PINGROUP(ufs0_ref_clk_pff0,	UFS0,		RSVD1,		RSVD2,		RSVD3,		0x11008,	0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	15,	17,	Y,	"vddio_ufs"),
1779 };
1780 
1781 static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
1782 	.pins = tegra194_pins,
1783 	.npins = ARRAY_SIZE(tegra194_pins),
1784 	.functions = tegra194_functions,
1785 	.nfunctions = ARRAY_SIZE(tegra194_functions),
1786 	.groups = tegra194_groups,
1787 	.ngroups = ARRAY_SIZE(tegra194_groups),
1788 	.hsm_in_mux = true,
1789 	.schmitt_in_mux = true,
1790 	.drvtype_in_mux = true,
1791 	.sfsel_in_mux = true,
1792 };
1793 
1794 static const struct pinctrl_pin_desc tegra194_aon_pins[] = {
1795 	PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA0, "CAN1_DOUT_PAA0"),
1796 	PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA1, "CAN1_DIN_PAA1"),
1797 	PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA2, "CAN0_DOUT_PAA2"),
1798 	PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA3, "CAN0_DIN_PAA3"),
1799 	PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"),
1800 	PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"),
1801 	PINCTRL_PIN(TEGRA_PIN_CAN0_WAKE_PAA6, "CAN0_WAKE_PAA6"),
1802 	PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"),
1803 	PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"),
1804 	PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"),
1805 	PINCTRL_PIN(TEGRA_PIN_CAN1_WAKE_PBB2, "CAN1_WAKE_PBB2"),
1806 	PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"),
1807 	PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"),
1808 	PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"),
1809 	PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"),
1810 	PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"),
1811 	PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"),
1812 	PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"),
1813 	PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"),
1814 	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"),
1815 	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"),
1816 	PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"),
1817 	PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"),
1818 	PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PEE0, "SAFE_STATE_PEE0"),
1819 	PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"),
1820 	PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"),
1821 	PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"),
1822 	PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"),
1823 	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PEE5, "PWR_I2C_SCL_PEE5"),
1824 	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PEE6, "PWR_I2C_SDA_PEE6"),
1825 	PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
1826 	PINCTRL_PIN(TEGRA_PIN_SHUTDOWN_N, "SHUTDOWN_N"),
1827 	PINCTRL_PIN(TEGRA_PIN_PMU_INT_N, "PMU_INT_N"),
1828 	PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"),
1829 	PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
1830 };
1831 
1832 static const struct tegra_pingroup tegra194_aon_groups[] = {
1833 	PINGROUP(shutdown_n,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1000,		0,	Y,	5,	-1,	6,	8,	-1,	-1,	-1,	12,	N,	-1,	-1,	N,	"vddio_sys"),
1834 	PINGROUP(pmu_int_n,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1008,		0,	Y,	-1,	-1,	6,	8,	-1,	-1,	-1,	12,	N,	-1,	-1,	N,	"vddio_sys"),
1835 	PINGROUP(safe_state_pee0,	SCE,		RSVD1,		RSVD2,		RSVD3,		0x1010,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),
1836 	PINGROUP(vcomp_alert_pee1,	SOC,		RSVD1,		RSVD2,		RSVD3,		0x1018,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),
1837 	PINGROUP(soc_pwr_req,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1020,		0,	Y,	-1,	-1,	6,	8,	-1,	-1,	-1,	12,	N,	-1,	-1,	N,	"vddio_sys"),
1838 	PINGROUP(batt_oc_pee3,		SOC,		RSVD1,		RSVD2,		RSVD3,		0x1028,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),
1839 	PINGROUP(clk_32k_in,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1030,		0,	Y,	-1,	-1,	-1,	8,	-1,	-1,	-1,	12,	N,	-1,	-1,	N,	"vddio_sys"),
1840 	PINGROUP(power_on_pee4,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x1038,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),
1841 	PINGROUP(pwr_i2c_scl_pee5,	I2C5,		RSVD1,		RSVD2,		RSVD3,		0x1040,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),
1842 	PINGROUP(pwr_i2c_sda_pee6,	I2C5,		RSVD1,		RSVD2,		RSVD3,		0x1048,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),
1843 	PINGROUP(ao_retention_n_pee2,	GPIO,		RSVD1,		RSVD2,		RSVD3,		0x1060,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_sys"),
1844 	PINGROUP(touch_clk_pcc4,	GP,		TOUCH,		RSVD2,		RSVD3,		0x2000,		0,	Y,	-1,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),
1845 	PINGROUP(uart3_rx_pcc6,		UARTC,		RSVD1,		RSVD2,		RSVD3,		0x2008,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),
1846 	PINGROUP(uart3_tx_pcc5,		UARTC,		RSVD1,		RSVD2,		RSVD3,		0x2010,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),
1847 	PINGROUP(gen8_i2c_sda_pdd2,	I2C8,		RSVD1,		RSVD2,		RSVD3,		0x2018,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),
1848 	PINGROUP(gen8_i2c_scl_pdd1,	I2C8,		RSVD1,		RSVD2,		RSVD3,		0x2020,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),
1849 	PINGROUP(spi2_mosi_pcc2,	SPI2,		UARTG,		RSVD2,		RSVD3,		0x2028,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),
1850 	PINGROUP(gen2_i2c_scl_pcc7,	I2C2,		RSVD1,		RSVD2,		RSVD3,		0x2030,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),
1851 	PINGROUP(spi2_cs0_pcc3,		SPI2,		UARTG,		RSVD2,		RSVD3,		0x2038,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),
1852 	PINGROUP(gen2_i2c_sda_pdd0,	I2C2,		RSVD1,		RSVD2,		RSVD3,		0x2040,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),
1853 	PINGROUP(spi2_sck_pcc0,		SPI2,		UARTG,		RSVD2,		RSVD3,		0x2048,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),
1854 	PINGROUP(spi2_miso_pcc1,	SPI2,		UARTG,		RSVD2,		RSVD3,		0x2050,		0,	Y,	5,	-1,	6,	8,	-1,	10,	11,	12,	N,	-1,	-1,	N,	"vddio_ao"),
1855 	PINGROUP(can1_dout_paa0,	CAN1,		RSVD1,		RSVD2,		RSVD3,		0x3000,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),
1856 	PINGROUP(can1_din_paa1,		CAN1,		RSVD1,		RSVD2,		RSVD3,		0x3008,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),
1857 	PINGROUP(can0_dout_paa2,	CAN0,		RSVD1,		RSVD2,		RSVD3,		0x3010,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),
1858 	PINGROUP(can0_din_paa3,		CAN0,		RSVD1,		RSVD2,		RSVD3,		0x3018,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),
1859 	PINGROUP(can0_stb_paa4,		RSVD0,		WDT,		RSVD2,		RSVD3,		0x3020,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),
1860 	PINGROUP(can0_en_paa5,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x3028,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),
1861 	PINGROUP(can0_wake_paa6,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x3030,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),
1862 	PINGROUP(can0_err_paa7,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x3038,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),
1863 	PINGROUP(can1_stb_pbb0,		RSVD0,		DMIC3,		DMIC5,		RSVD3,		0x3040,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),
1864 	PINGROUP(can1_en_pbb1,		RSVD0,		DMIC3,		DMIC5,		RSVD3,		0x3048,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),
1865 	PINGROUP(can1_wake_pbb2,	RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x3050,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),
1866 	PINGROUP(can1_err_pbb3,		RSVD0,		RSVD1,		RSVD2,		RSVD3,		0x3058,		0,	Y,	-1,	-1,	6,	-1,	9,	10,	-1,	12,	Y,	-1,	-1,	Y,	"vddio_ao_hv"),
1867 };
1868 
1869 static const struct tegra_pinctrl_soc_data tegra194_pinctrl_aon = {
1870 	.pins = tegra194_aon_pins,
1871 	.npins = ARRAY_SIZE(tegra194_aon_pins),
1872 	.functions = tegra194_functions,
1873 	.nfunctions = ARRAY_SIZE(tegra194_functions),
1874 	.groups = tegra194_aon_groups,
1875 	.ngroups = ARRAY_SIZE(tegra194_aon_groups),
1876 	.hsm_in_mux = true,
1877 	.schmitt_in_mux = true,
1878 	.drvtype_in_mux = true,
1879 	.sfsel_in_mux = true,
1880 };
1881 
1882 static int tegra194_pinctrl_probe(struct platform_device *pdev)
1883 {
1884 	const struct tegra_pinctrl_soc_data *soc = of_device_get_match_data(&pdev->dev);
1885 
1886 	return tegra_pinctrl_probe(pdev, soc);
1887 }
1888 
1889 static const struct of_device_id tegra194_pinctrl_of_match[] = {
1890 	{ .compatible = "nvidia,tegra194-pinmux", .data = &tegra194_pinctrl },
1891 	{ .compatible = "nvidia,tegra194-pinmux-aon", .data = &tegra194_pinctrl_aon },
1892 	{ },
1893 };
1894 
1895 static struct platform_driver tegra194_pinctrl_driver = {
1896 	.driver = {
1897 		.name = "tegra194-pinctrl",
1898 		.of_match_table = tegra194_pinctrl_of_match,
1899 	},
1900 	.probe = tegra194_pinctrl_probe,
1901 };
1902 
1903 static int __init tegra194_pinctrl_init(void)
1904 {
1905 	return platform_driver_register(&tegra194_pinctrl_driver);
1906 }
1907 arch_initcall(tegra194_pinctrl_init);
1908