1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Pinctrl data for the NVIDIA Tegra194 pinmux 4 * 5 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 */ 16 17 #include <linux/init.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/pinctrl/pinctrl.h> 21 #include <linux/pinctrl/pinmux.h> 22 23 #include "pinctrl-tegra.h" 24 25 /* Define unique ID for each pins */ 26 enum pin_id { 27 TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0 = 256, 28 TEGRA_PIN_PEX_L5_RST_N_PGG1 = 257, 29 TEGRA_PIN_NUM_GPIOS = 258, 30 }; 31 32 /* Table for pin descriptor */ 33 static const struct pinctrl_pin_desc tegra194_pins[] = { 34 PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, 35 "TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0"), 36 PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, 37 "TEGRA_PIN_PEX_L5_RST_N_PGG1"), 38 }; 39 40 static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = { 41 TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, 42 }; 43 44 static const unsigned int pex_l5_rst_n_pgg1_pins[] = { 45 TEGRA_PIN_PEX_L5_RST_N_PGG1, 46 }; 47 48 /* Define unique ID for each function */ 49 enum tegra_mux_dt { 50 TEGRA_MUX_RSVD0, 51 TEGRA_MUX_RSVD1, 52 TEGRA_MUX_RSVD2, 53 TEGRA_MUX_RSVD3, 54 TEGRA_MUX_PE5, 55 }; 56 57 /* Make list of each function name */ 58 #define TEGRA_PIN_FUNCTION(lid) \ 59 { \ 60 .name = #lid, \ 61 } 62 static struct tegra_function tegra194_functions[] = { 63 TEGRA_PIN_FUNCTION(rsvd0), 64 TEGRA_PIN_FUNCTION(rsvd1), 65 TEGRA_PIN_FUNCTION(rsvd2), 66 TEGRA_PIN_FUNCTION(rsvd3), 67 TEGRA_PIN_FUNCTION(pe5), 68 }; 69 70 #define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \ 71 drvup_w, slwr_b, slwr_w, slwf_b, \ 72 slwf_w, bank) \ 73 .drv_reg = ((r)), \ 74 .drv_bank = bank, \ 75 .drvdn_bit = drvdn_b, \ 76 .drvdn_width = drvdn_w, \ 77 .drvup_bit = drvup_b, \ 78 .drvup_width = drvup_w, \ 79 .slwr_bit = slwr_b, \ 80 .slwr_width = slwr_w, \ 81 .slwf_bit = slwf_b, \ 82 .slwf_width = slwf_w 83 84 #define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, e_input, \ 85 e_od, schmitt_b, drvtype) \ 86 .mux_reg = ((r)), \ 87 .lpmd_bit = -1, \ 88 .lock_bit = -1, \ 89 .hsm_bit = -1, \ 90 .mux_bank = bank, \ 91 .mux_bit = 0, \ 92 .pupd_reg = ((r)), \ 93 .pupd_bank = bank, \ 94 .pupd_bit = 2, \ 95 .tri_reg = ((r)), \ 96 .tri_bank = bank, \ 97 .tri_bit = 4, \ 98 .einput_bit = e_input, \ 99 .odrain_bit = e_od, \ 100 .schmitt_bit = schmitt_b, \ 101 .drvtype_bit = 13, \ 102 .drv_reg = -1, \ 103 .parked_bitmask = 0 104 105 #define drive_pex_l5_clkreq_n_pgg0 \ 106 DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 107 #define drive_pex_l5_rst_n_pgg1 \ 108 DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 109 110 #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk, \ 111 e_input, e_lpdr, e_od, schmitt_b, drvtype, io_rail) \ 112 { \ 113 .name = #pg_name, \ 114 .pins = pg_name##_pins, \ 115 .npins = ARRAY_SIZE(pg_name##_pins), \ 116 .funcs = { \ 117 TEGRA_MUX_##f0, \ 118 TEGRA_MUX_##f1, \ 119 TEGRA_MUX_##f2, \ 120 TEGRA_MUX_##f3, \ 121 }, \ 122 PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, \ 123 e_input, e_od, \ 124 schmitt_b, drvtype), \ 125 drive_##pg_name, \ 126 } 127 128 static const struct tegra_pingroup tegra194_groups[] = { 129 PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0, 130 Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"), 131 PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0, 132 Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"), 133 }; 134 135 static const struct tegra_pinctrl_soc_data tegra194_pinctrl = { 136 .ngpios = TEGRA_PIN_NUM_GPIOS, 137 .pins = tegra194_pins, 138 .npins = ARRAY_SIZE(tegra194_pins), 139 .functions = tegra194_functions, 140 .nfunctions = ARRAY_SIZE(tegra194_functions), 141 .groups = tegra194_groups, 142 .ngroups = ARRAY_SIZE(tegra194_groups), 143 .hsm_in_mux = true, 144 .schmitt_in_mux = true, 145 .drvtype_in_mux = true, 146 }; 147 148 static int tegra194_pinctrl_probe(struct platform_device *pdev) 149 { 150 return tegra_pinctrl_probe(pdev, &tegra194_pinctrl); 151 } 152 153 static const struct of_device_id tegra194_pinctrl_of_match[] = { 154 { .compatible = "nvidia,tegra194-pinmux", }, 155 { }, 156 }; 157 158 static struct platform_driver tegra194_pinctrl_driver = { 159 .driver = { 160 .name = "tegra194-pinctrl", 161 .of_match_table = tegra194_pinctrl_of_match, 162 }, 163 .probe = tegra194_pinctrl_probe, 164 }; 165 166 static int __init tegra194_pinctrl_init(void) 167 { 168 return platform_driver_register(&tegra194_pinctrl_driver); 169 } 170 arch_initcall(tegra194_pinctrl_init); 171