1 /*
2  * Pinctrl data for the NVIDIA Tegra124 pinmux
3  *
4  * Author: Ashwini Ghuge <aghuge@nvidia.com>
5  *
6  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2, as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  */
17 
18 #include <linux/init.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 
24 #include "pinctrl-tegra.h"
25 
26 /*
27  * Most pins affected by the pinmux can also be GPIOs. Define these first.
28  * These must match how the GPIO driver names/numbers its pins.
29  */
30 #define _GPIO(offset)				(offset)
31 
32 #define TEGRA_PIN_CLK_32K_OUT_PA0		_GPIO(0)
33 #define TEGRA_PIN_UART3_CTS_N_PA1		_GPIO(1)
34 #define TEGRA_PIN_DAP2_FS_PA2			_GPIO(2)
35 #define TEGRA_PIN_DAP2_SCLK_PA3			_GPIO(3)
36 #define TEGRA_PIN_DAP2_DIN_PA4			_GPIO(4)
37 #define TEGRA_PIN_DAP2_DOUT_PA5			_GPIO(5)
38 #define TEGRA_PIN_SDMMC3_CLK_PA6		_GPIO(6)
39 #define TEGRA_PIN_SDMMC3_CMD_PA7		_GPIO(7)
40 #define TEGRA_PIN_PB0				_GPIO(8)
41 #define TEGRA_PIN_PB1				_GPIO(9)
42 #define TEGRA_PIN_SDMMC3_DAT3_PB4		_GPIO(12)
43 #define TEGRA_PIN_SDMMC3_DAT2_PB5		_GPIO(13)
44 #define TEGRA_PIN_SDMMC3_DAT1_PB6		_GPIO(14)
45 #define TEGRA_PIN_SDMMC3_DAT0_PB7		_GPIO(15)
46 #define TEGRA_PIN_UART3_RTS_N_PC0		_GPIO(16)
47 #define TEGRA_PIN_UART2_TXD_PC2			_GPIO(18)
48 #define TEGRA_PIN_UART2_RXD_PC3			_GPIO(19)
49 #define TEGRA_PIN_GEN1_I2C_SCL_PC4		_GPIO(20)
50 #define TEGRA_PIN_GEN1_I2C_SDA_PC5		_GPIO(21)
51 #define TEGRA_PIN_PC7				_GPIO(23)
52 #define TEGRA_PIN_PG0				_GPIO(48)
53 #define TEGRA_PIN_PG1				_GPIO(49)
54 #define TEGRA_PIN_PG2				_GPIO(50)
55 #define TEGRA_PIN_PG3				_GPIO(51)
56 #define TEGRA_PIN_PG4				_GPIO(52)
57 #define TEGRA_PIN_PG5				_GPIO(53)
58 #define TEGRA_PIN_PG6				_GPIO(54)
59 #define TEGRA_PIN_PG7				_GPIO(55)
60 #define TEGRA_PIN_PH0				_GPIO(56)
61 #define TEGRA_PIN_PH1				_GPIO(57)
62 #define TEGRA_PIN_PH2				_GPIO(58)
63 #define TEGRA_PIN_PH3				_GPIO(59)
64 #define TEGRA_PIN_PH4				_GPIO(60)
65 #define TEGRA_PIN_PH5				_GPIO(61)
66 #define TEGRA_PIN_PH6				_GPIO(62)
67 #define TEGRA_PIN_PH7				_GPIO(63)
68 #define TEGRA_PIN_PI0				_GPIO(64)
69 #define TEGRA_PIN_PI1				_GPIO(65)
70 #define TEGRA_PIN_PI2				_GPIO(66)
71 #define TEGRA_PIN_PI3				_GPIO(67)
72 #define TEGRA_PIN_PI4				_GPIO(68)
73 #define TEGRA_PIN_PI5				_GPIO(69)
74 #define TEGRA_PIN_PI6				_GPIO(70)
75 #define TEGRA_PIN_PI7				_GPIO(71)
76 #define TEGRA_PIN_PJ0				_GPIO(72)
77 #define TEGRA_PIN_PJ2				_GPIO(74)
78 #define TEGRA_PIN_UART2_CTS_N_PJ5		_GPIO(77)
79 #define TEGRA_PIN_UART2_RTS_N_PJ6		_GPIO(78)
80 #define TEGRA_PIN_PJ7				_GPIO(79)
81 #define TEGRA_PIN_PK0				_GPIO(80)
82 #define TEGRA_PIN_PK1				_GPIO(81)
83 #define TEGRA_PIN_PK2				_GPIO(82)
84 #define TEGRA_PIN_PK3				_GPIO(83)
85 #define TEGRA_PIN_PK4				_GPIO(84)
86 #define TEGRA_PIN_SPDIF_OUT_PK5			_GPIO(85)
87 #define TEGRA_PIN_SPDIF_IN_PK6			_GPIO(86)
88 #define TEGRA_PIN_PK7				_GPIO(87)
89 #define TEGRA_PIN_DAP1_FS_PN0			_GPIO(104)
90 #define TEGRA_PIN_DAP1_DIN_PN1			_GPIO(105)
91 #define TEGRA_PIN_DAP1_DOUT_PN2			_GPIO(106)
92 #define TEGRA_PIN_DAP1_SCLK_PN3			_GPIO(107)
93 #define TEGRA_PIN_USB_VBUS_EN0_PN4		_GPIO(108)
94 #define TEGRA_PIN_USB_VBUS_EN1_PN5		_GPIO(109)
95 #define TEGRA_PIN_HDMI_INT_PN7			_GPIO(111)
96 #define TEGRA_PIN_ULPI_DATA7_PO0		_GPIO(112)
97 #define TEGRA_PIN_ULPI_DATA0_PO1		_GPIO(113)
98 #define TEGRA_PIN_ULPI_DATA1_PO2		_GPIO(114)
99 #define TEGRA_PIN_ULPI_DATA2_PO3		_GPIO(115)
100 #define TEGRA_PIN_ULPI_DATA3_PO4		_GPIO(116)
101 #define TEGRA_PIN_ULPI_DATA4_PO5		_GPIO(117)
102 #define TEGRA_PIN_ULPI_DATA5_PO6		_GPIO(118)
103 #define TEGRA_PIN_ULPI_DATA6_PO7		_GPIO(119)
104 #define TEGRA_PIN_DAP3_FS_PP0			_GPIO(120)
105 #define TEGRA_PIN_DAP3_DIN_PP1			_GPIO(121)
106 #define TEGRA_PIN_DAP3_DOUT_PP2			_GPIO(122)
107 #define TEGRA_PIN_DAP3_SCLK_PP3			_GPIO(123)
108 #define TEGRA_PIN_DAP4_FS_PP4			_GPIO(124)
109 #define TEGRA_PIN_DAP4_DIN_PP5			_GPIO(125)
110 #define TEGRA_PIN_DAP4_DOUT_PP6			_GPIO(126)
111 #define TEGRA_PIN_DAP4_SCLK_PP7			_GPIO(127)
112 #define TEGRA_PIN_KB_COL0_PQ0			_GPIO(128)
113 #define TEGRA_PIN_KB_COL1_PQ1			_GPIO(129)
114 #define TEGRA_PIN_KB_COL2_PQ2			_GPIO(130)
115 #define TEGRA_PIN_KB_COL3_PQ3			_GPIO(131)
116 #define TEGRA_PIN_KB_COL4_PQ4			_GPIO(132)
117 #define TEGRA_PIN_KB_COL5_PQ5			_GPIO(133)
118 #define TEGRA_PIN_KB_COL6_PQ6			_GPIO(134)
119 #define TEGRA_PIN_KB_COL7_PQ7			_GPIO(135)
120 #define TEGRA_PIN_KB_ROW0_PR0			_GPIO(136)
121 #define TEGRA_PIN_KB_ROW1_PR1			_GPIO(137)
122 #define TEGRA_PIN_KB_ROW2_PR2			_GPIO(138)
123 #define TEGRA_PIN_KB_ROW3_PR3			_GPIO(139)
124 #define TEGRA_PIN_KB_ROW4_PR4			_GPIO(140)
125 #define TEGRA_PIN_KB_ROW5_PR5			_GPIO(141)
126 #define TEGRA_PIN_KB_ROW6_PR6			_GPIO(142)
127 #define TEGRA_PIN_KB_ROW7_PR7			_GPIO(143)
128 #define TEGRA_PIN_KB_ROW8_PS0			_GPIO(144)
129 #define TEGRA_PIN_KB_ROW9_PS1			_GPIO(145)
130 #define TEGRA_PIN_KB_ROW10_PS2			_GPIO(146)
131 #define TEGRA_PIN_KB_ROW11_PS3			_GPIO(147)
132 #define TEGRA_PIN_KB_ROW12_PS4			_GPIO(148)
133 #define TEGRA_PIN_KB_ROW13_PS5			_GPIO(149)
134 #define TEGRA_PIN_KB_ROW14_PS6			_GPIO(150)
135 #define TEGRA_PIN_KB_ROW15_PS7			_GPIO(151)
136 #define TEGRA_PIN_KB_ROW16_PT0			_GPIO(152)
137 #define TEGRA_PIN_KB_ROW17_PT1			_GPIO(153)
138 #define TEGRA_PIN_GEN2_I2C_SCL_PT5		_GPIO(157)
139 #define TEGRA_PIN_GEN2_I2C_SDA_PT6		_GPIO(158)
140 #define TEGRA_PIN_SDMMC4_CMD_PT7		_GPIO(159)
141 #define TEGRA_PIN_PU0				_GPIO(160)
142 #define TEGRA_PIN_PU1				_GPIO(161)
143 #define TEGRA_PIN_PU2				_GPIO(162)
144 #define TEGRA_PIN_PU3				_GPIO(163)
145 #define TEGRA_PIN_PU4				_GPIO(164)
146 #define TEGRA_PIN_PU5				_GPIO(165)
147 #define TEGRA_PIN_PU6				_GPIO(166)
148 #define TEGRA_PIN_PV0				_GPIO(168)
149 #define TEGRA_PIN_PV1				_GPIO(169)
150 #define TEGRA_PIN_SDMMC3_CD_N_PV2		_GPIO(170)
151 #define TEGRA_PIN_SDMMC1_WP_N_PV3		_GPIO(171)
152 #define TEGRA_PIN_DDC_SCL_PV4			_GPIO(172)
153 #define TEGRA_PIN_DDC_SDA_PV5			_GPIO(173)
154 #define TEGRA_PIN_GPIO_W2_AUD_PW2		_GPIO(178)
155 #define TEGRA_PIN_GPIO_W3_AUD_PW3		_GPIO(179)
156 #define TEGRA_PIN_DAP_MCLK1_PW4			_GPIO(180)
157 #define TEGRA_PIN_CLK2_OUT_PW5			_GPIO(181)
158 #define TEGRA_PIN_UART3_TXD_PW6			_GPIO(182)
159 #define TEGRA_PIN_UART3_RXD_PW7			_GPIO(183)
160 #define TEGRA_PIN_DVFS_PWM_PX0			_GPIO(184)
161 #define TEGRA_PIN_GPIO_X1_AUD_PX1		_GPIO(185)
162 #define TEGRA_PIN_DVFS_CLK_PX2			_GPIO(186)
163 #define TEGRA_PIN_GPIO_X3_AUD_PX3		_GPIO(187)
164 #define TEGRA_PIN_GPIO_X4_AUD_PX4		_GPIO(188)
165 #define TEGRA_PIN_GPIO_X5_AUD_PX5		_GPIO(189)
166 #define TEGRA_PIN_GPIO_X6_AUD_PX6		_GPIO(190)
167 #define TEGRA_PIN_GPIO_X7_AUD_PX7		_GPIO(191)
168 #define TEGRA_PIN_ULPI_CLK_PY0			_GPIO(192)
169 #define TEGRA_PIN_ULPI_DIR_PY1			_GPIO(193)
170 #define TEGRA_PIN_ULPI_NXT_PY2			_GPIO(194)
171 #define TEGRA_PIN_ULPI_STP_PY3			_GPIO(195)
172 #define TEGRA_PIN_SDMMC1_DAT3_PY4		_GPIO(196)
173 #define TEGRA_PIN_SDMMC1_DAT2_PY5		_GPIO(197)
174 #define TEGRA_PIN_SDMMC1_DAT1_PY6		_GPIO(198)
175 #define TEGRA_PIN_SDMMC1_DAT0_PY7		_GPIO(199)
176 #define TEGRA_PIN_SDMMC1_CLK_PZ0		_GPIO(200)
177 #define TEGRA_PIN_SDMMC1_CMD_PZ1		_GPIO(201)
178 #define TEGRA_PIN_PWR_I2C_SCL_PZ6		_GPIO(206)
179 #define TEGRA_PIN_PWR_I2C_SDA_PZ7		_GPIO(207)
180 #define TEGRA_PIN_SDMMC4_DAT0_PAA0		_GPIO(208)
181 #define TEGRA_PIN_SDMMC4_DAT1_PAA1		_GPIO(209)
182 #define TEGRA_PIN_SDMMC4_DAT2_PAA2		_GPIO(210)
183 #define TEGRA_PIN_SDMMC4_DAT3_PAA3		_GPIO(211)
184 #define TEGRA_PIN_SDMMC4_DAT4_PAA4		_GPIO(212)
185 #define TEGRA_PIN_SDMMC4_DAT5_PAA5		_GPIO(213)
186 #define TEGRA_PIN_SDMMC4_DAT6_PAA6		_GPIO(214)
187 #define TEGRA_PIN_SDMMC4_DAT7_PAA7		_GPIO(215)
188 #define TEGRA_PIN_PBB0				_GPIO(216)
189 #define TEGRA_PIN_CAM_I2C_SCL_PBB1		_GPIO(217)
190 #define TEGRA_PIN_CAM_I2C_SDA_PBB2		_GPIO(218)
191 #define TEGRA_PIN_PBB3				_GPIO(219)
192 #define TEGRA_PIN_PBB4				_GPIO(220)
193 #define TEGRA_PIN_PBB5				_GPIO(221)
194 #define TEGRA_PIN_PBB6				_GPIO(222)
195 #define TEGRA_PIN_PBB7				_GPIO(223)
196 #define TEGRA_PIN_CAM_MCLK_PCC0			_GPIO(224)
197 #define TEGRA_PIN_PCC1				_GPIO(225)
198 #define TEGRA_PIN_PCC2				_GPIO(226)
199 #define TEGRA_PIN_SDMMC4_CLK_PCC4		_GPIO(228)
200 #define TEGRA_PIN_CLK2_REQ_PCC5			_GPIO(229)
201 #define TEGRA_PIN_PEX_L0_RST_N_PDD1		_GPIO(233)
202 #define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2		_GPIO(234)
203 #define TEGRA_PIN_PEX_WAKE_N_PDD3		_GPIO(235)
204 #define TEGRA_PIN_PEX_L1_RST_N_PDD5		_GPIO(237)
205 #define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6		_GPIO(238)
206 #define TEGRA_PIN_CLK3_OUT_PEE0			_GPIO(240)
207 #define TEGRA_PIN_CLK3_REQ_PEE1			_GPIO(241)
208 #define TEGRA_PIN_DAP_MCLK1_REQ_PEE2		_GPIO(242)
209 #define TEGRA_PIN_HDMI_CEC_PEE3			_GPIO(243)
210 #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4	_GPIO(244)
211 #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5		_GPIO(245)
212 #define TEGRA_PIN_DP_HPD_PFF0			_GPIO(248)
213 #define TEGRA_PIN_USB_VBUS_EN2_PFF1		_GPIO(249)
214 #define TEGRA_PIN_PFF2				_GPIO(250)
215 
216 /* All non-GPIO pins follow */
217 #define NUM_GPIOS				(TEGRA_PIN_PFF2 + 1)
218 #define _PIN(offset)				(NUM_GPIOS + (offset))
219 
220 /* Non-GPIO pins */
221 #define TEGRA_PIN_CORE_PWR_REQ			_PIN(0)
222 #define TEGRA_PIN_CPU_PWR_REQ			_PIN(1)
223 #define TEGRA_PIN_PWR_INT_N			_PIN(2)
224 #define TEGRA_PIN_GMI_CLK_LB			_PIN(3)
225 #define TEGRA_PIN_RESET_OUT_N			_PIN(4)
226 #define TEGRA_PIN_OWR				_PIN(5)
227 #define TEGRA_PIN_CLK_32K_IN			_PIN(6)
228 #define TEGRA_PIN_JTAG_RTCK			_PIN(7)
229 #define TEGRA_PIN_DSI_B_CLK_P			_PIN(8)
230 #define TEGRA_PIN_DSI_B_CLK_N			_PIN(9)
231 #define TEGRA_PIN_DSI_B_D0_P			_PIN(10)
232 #define TEGRA_PIN_DSI_B_D0_N			_PIN(11)
233 #define TEGRA_PIN_DSI_B_D1_P			_PIN(12)
234 #define TEGRA_PIN_DSI_B_D1_N			_PIN(13)
235 #define TEGRA_PIN_DSI_B_D2_P			_PIN(14)
236 #define TEGRA_PIN_DSI_B_D2_N			_PIN(15)
237 #define TEGRA_PIN_DSI_B_D3_P			_PIN(16)
238 #define TEGRA_PIN_DSI_B_D3_N			_PIN(17)
239 
240 static const struct pinctrl_pin_desc tegra124_pins[] = {
241 	PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
242 	PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
243 	PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
244 	PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
245 	PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
246 	PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
247 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
248 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
249 	PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"),
250 	PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"),
251 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
252 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
253 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
254 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
255 	PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
256 	PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
257 	PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
258 	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
259 	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
260 	PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"),
261 	PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"),
262 	PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"),
263 	PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"),
264 	PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"),
265 	PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"),
266 	PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"),
267 	PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"),
268 	PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"),
269 	PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"),
270 	PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"),
271 	PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"),
272 	PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"),
273 	PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"),
274 	PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"),
275 	PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
276 	PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"),
277 	PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"),
278 	PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"),
279 	PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"),
280 	PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"),
281 	PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"),
282 	PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"),
283 	PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"),
284 	PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"),
285 	PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"),
286 	PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"),
287 	PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
288 	PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
289 	PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"),
290 	PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
291 	PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
292 	PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
293 	PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
294 	PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
295 	PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
296 	PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
297 	PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
298 	PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
299 	PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
300 	PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
301 	PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
302 	PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
303 	PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
304 	PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
305 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
306 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
307 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
308 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
309 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
310 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
311 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
312 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
313 	PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
314 	PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
315 	PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
316 	PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
317 	PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
318 	PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
319 	PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
320 	PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
321 	PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
322 	PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
323 	PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
324 	PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
325 	PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
326 	PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
327 	PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
328 	PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
329 	PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
330 	PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
331 	PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
332 	PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
333 	PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
334 	PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
335 	PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
336 	PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
337 	PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
338 	PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
339 	PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
340 	PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
341 	PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
342 	PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
343 	PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
344 	PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
345 	PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW16 PT0"),
346 	PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW17 PT1"),
347 	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
348 	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
349 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
350 	PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
351 	PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
352 	PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
353 	PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
354 	PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
355 	PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
356 	PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
357 	PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
358 	PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
359 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
360 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
361 	PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
362 	PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
363 	PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
364 	PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
365 	PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
366 	PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
367 	PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
368 	PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
369 	PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
370 	PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
371 	PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
372 	PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
373 	PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
374 	PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
375 	PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
376 	PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
377 	PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
378 	PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
379 	PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
380 	PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
381 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
382 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
383 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
384 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
385 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
386 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
387 	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
388 	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
389 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
390 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
391 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
392 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
393 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
394 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
395 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
396 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
397 	PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
398 	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
399 	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
400 	PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
401 	PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
402 	PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
403 	PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
404 	PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
405 	PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
406 	PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
407 	PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
408 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
409 	PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
410 	PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
411 	PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
412 	PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
413 	PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
414 	PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
415 	PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
416 	PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
417 	PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"),
418 	PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
419 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
420 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
421 	PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
422 	PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
423 	PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
424 	PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
425 	PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
426 	PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
427 	PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
428 	PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
429 	PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
430 	PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
431 	PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
432 	PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"),
433 	PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"),
434 	PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"),
435 	PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"),
436 	PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"),
437 	PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"),
438 	PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"),
439 	PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"),
440 	PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"),
441 	PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"),
442 };
443 
444 static const unsigned clk_32k_out_pa0_pins[] = {
445 	TEGRA_PIN_CLK_32K_OUT_PA0,
446 };
447 
448 static const unsigned uart3_cts_n_pa1_pins[] = {
449 	TEGRA_PIN_UART3_CTS_N_PA1,
450 };
451 
452 static const unsigned dap2_fs_pa2_pins[] = {
453 	TEGRA_PIN_DAP2_FS_PA2,
454 };
455 
456 static const unsigned dap2_sclk_pa3_pins[] = {
457 	TEGRA_PIN_DAP2_SCLK_PA3,
458 };
459 
460 static const unsigned dap2_din_pa4_pins[] = {
461 	TEGRA_PIN_DAP2_DIN_PA4,
462 };
463 
464 static const unsigned dap2_dout_pa5_pins[] = {
465 	TEGRA_PIN_DAP2_DOUT_PA5,
466 };
467 
468 static const unsigned sdmmc3_clk_pa6_pins[] = {
469 	TEGRA_PIN_SDMMC3_CLK_PA6,
470 };
471 
472 static const unsigned sdmmc3_cmd_pa7_pins[] = {
473 	TEGRA_PIN_SDMMC3_CMD_PA7,
474 };
475 
476 static const unsigned pb0_pins[] = {
477 	TEGRA_PIN_PB0,
478 };
479 
480 static const unsigned pb1_pins[] = {
481 	TEGRA_PIN_PB1,
482 };
483 
484 static const unsigned sdmmc3_dat3_pb4_pins[] = {
485 	TEGRA_PIN_SDMMC3_DAT3_PB4,
486 };
487 
488 static const unsigned sdmmc3_dat2_pb5_pins[] = {
489 	TEGRA_PIN_SDMMC3_DAT2_PB5,
490 };
491 
492 static const unsigned sdmmc3_dat1_pb6_pins[] = {
493 	TEGRA_PIN_SDMMC3_DAT1_PB6,
494 };
495 
496 static const unsigned sdmmc3_dat0_pb7_pins[] = {
497 	TEGRA_PIN_SDMMC3_DAT0_PB7,
498 };
499 
500 static const unsigned uart3_rts_n_pc0_pins[] = {
501 	TEGRA_PIN_UART3_RTS_N_PC0,
502 };
503 
504 static const unsigned uart2_txd_pc2_pins[] = {
505 	TEGRA_PIN_UART2_TXD_PC2,
506 };
507 
508 static const unsigned uart2_rxd_pc3_pins[] = {
509 	TEGRA_PIN_UART2_RXD_PC3,
510 };
511 
512 static const unsigned gen1_i2c_scl_pc4_pins[] = {
513 	TEGRA_PIN_GEN1_I2C_SCL_PC4,
514 };
515 
516 static const unsigned gen1_i2c_sda_pc5_pins[] = {
517 	TEGRA_PIN_GEN1_I2C_SDA_PC5,
518 };
519 
520 static const unsigned pc7_pins[] = {
521 	TEGRA_PIN_PC7,
522 };
523 
524 static const unsigned pg0_pins[] = {
525 	TEGRA_PIN_PG0,
526 };
527 
528 static const unsigned pg1_pins[] = {
529 	TEGRA_PIN_PG1,
530 };
531 
532 static const unsigned pg2_pins[] = {
533 	TEGRA_PIN_PG2,
534 };
535 
536 static const unsigned pg3_pins[] = {
537 	TEGRA_PIN_PG3,
538 };
539 
540 static const unsigned pg4_pins[] = {
541 	TEGRA_PIN_PG4,
542 };
543 
544 static const unsigned pg5_pins[] = {
545 	TEGRA_PIN_PG5,
546 };
547 
548 static const unsigned pg6_pins[] = {
549 	TEGRA_PIN_PG6,
550 };
551 
552 static const unsigned pg7_pins[] = {
553 	TEGRA_PIN_PG7,
554 };
555 
556 static const unsigned ph0_pins[] = {
557 	TEGRA_PIN_PH0,
558 };
559 
560 static const unsigned ph1_pins[] = {
561 	TEGRA_PIN_PH1,
562 };
563 
564 static const unsigned ph2_pins[] = {
565 	TEGRA_PIN_PH2,
566 };
567 
568 static const unsigned ph3_pins[] = {
569 	TEGRA_PIN_PH3,
570 };
571 
572 static const unsigned ph4_pins[] = {
573 	TEGRA_PIN_PH4,
574 };
575 
576 static const unsigned ph5_pins[] = {
577 	TEGRA_PIN_PH5,
578 };
579 
580 static const unsigned ph6_pins[] = {
581 	TEGRA_PIN_PH6,
582 };
583 
584 static const unsigned ph7_pins[] = {
585 	TEGRA_PIN_PH7,
586 };
587 
588 static const unsigned pi0_pins[] = {
589 	TEGRA_PIN_PI0,
590 };
591 
592 static const unsigned pi1_pins[] = {
593 	TEGRA_PIN_PI1,
594 };
595 
596 static const unsigned pi2_pins[] = {
597 	TEGRA_PIN_PI2,
598 };
599 
600 static const unsigned pi3_pins[] = {
601 	TEGRA_PIN_PI3,
602 };
603 
604 static const unsigned pi4_pins[] = {
605 	TEGRA_PIN_PI4,
606 };
607 
608 static const unsigned pi5_pins[] = {
609 	TEGRA_PIN_PI5,
610 };
611 
612 static const unsigned pi6_pins[] = {
613 	TEGRA_PIN_PI6,
614 };
615 
616 static const unsigned pi7_pins[] = {
617 	TEGRA_PIN_PI7,
618 };
619 
620 static const unsigned pj0_pins[] = {
621 	TEGRA_PIN_PJ0,
622 };
623 
624 static const unsigned pj2_pins[] = {
625 	TEGRA_PIN_PJ2,
626 };
627 
628 static const unsigned uart2_cts_n_pj5_pins[] = {
629 	TEGRA_PIN_UART2_CTS_N_PJ5,
630 };
631 
632 static const unsigned uart2_rts_n_pj6_pins[] = {
633 	TEGRA_PIN_UART2_RTS_N_PJ6,
634 };
635 
636 static const unsigned pj7_pins[] = {
637 	TEGRA_PIN_PJ7,
638 };
639 
640 static const unsigned pk0_pins[] = {
641 	TEGRA_PIN_PK0,
642 };
643 
644 static const unsigned pk1_pins[] = {
645 	TEGRA_PIN_PK1,
646 };
647 
648 static const unsigned pk2_pins[] = {
649 	TEGRA_PIN_PK2,
650 };
651 
652 static const unsigned pk3_pins[] = {
653 	TEGRA_PIN_PK3,
654 };
655 
656 static const unsigned pk4_pins[] = {
657 	TEGRA_PIN_PK4,
658 };
659 
660 static const unsigned spdif_out_pk5_pins[] = {
661 	TEGRA_PIN_SPDIF_OUT_PK5,
662 };
663 
664 static const unsigned spdif_in_pk6_pins[] = {
665 	TEGRA_PIN_SPDIF_IN_PK6,
666 };
667 
668 static const unsigned pk7_pins[] = {
669 	TEGRA_PIN_PK7,
670 };
671 
672 static const unsigned dap1_fs_pn0_pins[] = {
673 	TEGRA_PIN_DAP1_FS_PN0,
674 };
675 
676 static const unsigned dap1_din_pn1_pins[] = {
677 	TEGRA_PIN_DAP1_DIN_PN1,
678 };
679 
680 static const unsigned dap1_dout_pn2_pins[] = {
681 	TEGRA_PIN_DAP1_DOUT_PN2,
682 };
683 
684 static const unsigned dap1_sclk_pn3_pins[] = {
685 	TEGRA_PIN_DAP1_SCLK_PN3,
686 };
687 
688 static const unsigned usb_vbus_en0_pn4_pins[] = {
689 	TEGRA_PIN_USB_VBUS_EN0_PN4,
690 };
691 
692 static const unsigned usb_vbus_en1_pn5_pins[] = {
693 	TEGRA_PIN_USB_VBUS_EN1_PN5,
694 };
695 
696 static const unsigned hdmi_int_pn7_pins[] = {
697 	TEGRA_PIN_HDMI_INT_PN7,
698 };
699 
700 static const unsigned ulpi_data7_po0_pins[] = {
701 	TEGRA_PIN_ULPI_DATA7_PO0,
702 };
703 
704 static const unsigned ulpi_data0_po1_pins[] = {
705 	TEGRA_PIN_ULPI_DATA0_PO1,
706 };
707 
708 static const unsigned ulpi_data1_po2_pins[] = {
709 	TEGRA_PIN_ULPI_DATA1_PO2,
710 };
711 
712 static const unsigned ulpi_data2_po3_pins[] = {
713 	TEGRA_PIN_ULPI_DATA2_PO3,
714 };
715 
716 static const unsigned ulpi_data3_po4_pins[] = {
717 	TEGRA_PIN_ULPI_DATA3_PO4,
718 };
719 
720 static const unsigned ulpi_data4_po5_pins[] = {
721 	TEGRA_PIN_ULPI_DATA4_PO5,
722 };
723 
724 static const unsigned ulpi_data5_po6_pins[] = {
725 	TEGRA_PIN_ULPI_DATA5_PO6,
726 };
727 
728 static const unsigned ulpi_data6_po7_pins[] = {
729 	TEGRA_PIN_ULPI_DATA6_PO7,
730 };
731 
732 static const unsigned dap3_fs_pp0_pins[] = {
733 	TEGRA_PIN_DAP3_FS_PP0,
734 };
735 
736 static const unsigned dap3_din_pp1_pins[] = {
737 	TEGRA_PIN_DAP3_DIN_PP1,
738 };
739 
740 static const unsigned dap3_dout_pp2_pins[] = {
741 	TEGRA_PIN_DAP3_DOUT_PP2,
742 };
743 
744 static const unsigned dap3_sclk_pp3_pins[] = {
745 	TEGRA_PIN_DAP3_SCLK_PP3,
746 };
747 
748 static const unsigned dap4_fs_pp4_pins[] = {
749 	TEGRA_PIN_DAP4_FS_PP4,
750 };
751 
752 static const unsigned dap4_din_pp5_pins[] = {
753 	TEGRA_PIN_DAP4_DIN_PP5,
754 };
755 
756 static const unsigned dap4_dout_pp6_pins[] = {
757 	TEGRA_PIN_DAP4_DOUT_PP6,
758 };
759 
760 static const unsigned dap4_sclk_pp7_pins[] = {
761 	TEGRA_PIN_DAP4_SCLK_PP7,
762 };
763 
764 static const unsigned kb_col0_pq0_pins[] = {
765 	TEGRA_PIN_KB_COL0_PQ0,
766 };
767 
768 static const unsigned kb_col1_pq1_pins[] = {
769 	TEGRA_PIN_KB_COL1_PQ1,
770 };
771 
772 static const unsigned kb_col2_pq2_pins[] = {
773 	TEGRA_PIN_KB_COL2_PQ2,
774 };
775 
776 static const unsigned kb_col3_pq3_pins[] = {
777 	TEGRA_PIN_KB_COL3_PQ3,
778 };
779 
780 static const unsigned kb_col4_pq4_pins[] = {
781 	TEGRA_PIN_KB_COL4_PQ4,
782 };
783 
784 static const unsigned kb_col5_pq5_pins[] = {
785 	TEGRA_PIN_KB_COL5_PQ5,
786 };
787 
788 static const unsigned kb_col6_pq6_pins[] = {
789 	TEGRA_PIN_KB_COL6_PQ6,
790 };
791 
792 static const unsigned kb_col7_pq7_pins[] = {
793 	TEGRA_PIN_KB_COL7_PQ7,
794 };
795 
796 static const unsigned kb_row0_pr0_pins[] = {
797 	TEGRA_PIN_KB_ROW0_PR0,
798 };
799 
800 static const unsigned kb_row1_pr1_pins[] = {
801 	TEGRA_PIN_KB_ROW1_PR1,
802 };
803 
804 static const unsigned kb_row2_pr2_pins[] = {
805 	TEGRA_PIN_KB_ROW2_PR2,
806 };
807 
808 static const unsigned kb_row3_pr3_pins[] = {
809 	TEGRA_PIN_KB_ROW3_PR3,
810 };
811 
812 static const unsigned kb_row4_pr4_pins[] = {
813 	TEGRA_PIN_KB_ROW4_PR4,
814 };
815 
816 static const unsigned kb_row5_pr5_pins[] = {
817 	TEGRA_PIN_KB_ROW5_PR5,
818 };
819 
820 static const unsigned kb_row6_pr6_pins[] = {
821 	TEGRA_PIN_KB_ROW6_PR6,
822 };
823 
824 static const unsigned kb_row7_pr7_pins[] = {
825 	TEGRA_PIN_KB_ROW7_PR7,
826 };
827 
828 static const unsigned kb_row8_ps0_pins[] = {
829 	TEGRA_PIN_KB_ROW8_PS0,
830 };
831 
832 static const unsigned kb_row9_ps1_pins[] = {
833 	TEGRA_PIN_KB_ROW9_PS1,
834 };
835 
836 static const unsigned kb_row10_ps2_pins[] = {
837 	TEGRA_PIN_KB_ROW10_PS2,
838 };
839 
840 static const unsigned kb_row11_ps3_pins[] = {
841 	TEGRA_PIN_KB_ROW11_PS3,
842 };
843 
844 static const unsigned kb_row12_ps4_pins[] = {
845 	TEGRA_PIN_KB_ROW12_PS4,
846 };
847 
848 static const unsigned kb_row13_ps5_pins[] = {
849 	TEGRA_PIN_KB_ROW13_PS5,
850 };
851 
852 static const unsigned kb_row14_ps6_pins[] = {
853 	TEGRA_PIN_KB_ROW14_PS6,
854 };
855 
856 static const unsigned kb_row15_ps7_pins[] = {
857 	TEGRA_PIN_KB_ROW15_PS7,
858 };
859 
860 static const unsigned kb_row16_pt0_pins[] = {
861 	TEGRA_PIN_KB_ROW16_PT0,
862 };
863 
864 static const unsigned kb_row17_pt1_pins[] = {
865 	TEGRA_PIN_KB_ROW17_PT1,
866 };
867 
868 static const unsigned gen2_i2c_scl_pt5_pins[] = {
869 	TEGRA_PIN_GEN2_I2C_SCL_PT5,
870 };
871 
872 static const unsigned gen2_i2c_sda_pt6_pins[] = {
873 	TEGRA_PIN_GEN2_I2C_SDA_PT6,
874 };
875 
876 static const unsigned sdmmc4_cmd_pt7_pins[] = {
877 	TEGRA_PIN_SDMMC4_CMD_PT7,
878 };
879 
880 static const unsigned pu0_pins[] = {
881 	TEGRA_PIN_PU0,
882 };
883 
884 static const unsigned pu1_pins[] = {
885 	TEGRA_PIN_PU1,
886 };
887 
888 static const unsigned pu2_pins[] = {
889 	TEGRA_PIN_PU2,
890 };
891 
892 static const unsigned pu3_pins[] = {
893 	TEGRA_PIN_PU3,
894 };
895 
896 static const unsigned pu4_pins[] = {
897 	TEGRA_PIN_PU4,
898 };
899 
900 static const unsigned pu5_pins[] = {
901 	TEGRA_PIN_PU5,
902 };
903 
904 static const unsigned pu6_pins[] = {
905 	TEGRA_PIN_PU6,
906 };
907 
908 static const unsigned pv0_pins[] = {
909 	TEGRA_PIN_PV0,
910 };
911 
912 static const unsigned pv1_pins[] = {
913 	TEGRA_PIN_PV1,
914 };
915 
916 static const unsigned sdmmc3_cd_n_pv2_pins[] = {
917 	TEGRA_PIN_SDMMC3_CD_N_PV2,
918 };
919 
920 static const unsigned sdmmc1_wp_n_pv3_pins[] = {
921 	TEGRA_PIN_SDMMC1_WP_N_PV3,
922 };
923 
924 static const unsigned ddc_scl_pv4_pins[] = {
925 	TEGRA_PIN_DDC_SCL_PV4,
926 };
927 
928 static const unsigned ddc_sda_pv5_pins[] = {
929 	TEGRA_PIN_DDC_SDA_PV5,
930 };
931 
932 static const unsigned gpio_w2_aud_pw2_pins[] = {
933 	TEGRA_PIN_GPIO_W2_AUD_PW2,
934 };
935 
936 static const unsigned gpio_w3_aud_pw3_pins[] = {
937 	TEGRA_PIN_GPIO_W3_AUD_PW3,
938 };
939 
940 static const unsigned dap_mclk1_pw4_pins[] = {
941 	TEGRA_PIN_DAP_MCLK1_PW4,
942 };
943 
944 static const unsigned clk2_out_pw5_pins[] = {
945 	TEGRA_PIN_CLK2_OUT_PW5,
946 };
947 
948 static const unsigned uart3_txd_pw6_pins[] = {
949 	TEGRA_PIN_UART3_TXD_PW6,
950 };
951 
952 static const unsigned uart3_rxd_pw7_pins[] = {
953 	TEGRA_PIN_UART3_RXD_PW7,
954 };
955 
956 static const unsigned dvfs_pwm_px0_pins[] = {
957 	TEGRA_PIN_DVFS_PWM_PX0,
958 };
959 
960 static const unsigned gpio_x1_aud_px1_pins[] = {
961 	TEGRA_PIN_GPIO_X1_AUD_PX1,
962 };
963 
964 static const unsigned dvfs_clk_px2_pins[] = {
965 	TEGRA_PIN_DVFS_CLK_PX2,
966 };
967 
968 static const unsigned gpio_x3_aud_px3_pins[] = {
969 	TEGRA_PIN_GPIO_X3_AUD_PX3,
970 };
971 
972 static const unsigned gpio_x4_aud_px4_pins[] = {
973 	TEGRA_PIN_GPIO_X4_AUD_PX4,
974 };
975 
976 static const unsigned gpio_x5_aud_px5_pins[] = {
977 	TEGRA_PIN_GPIO_X5_AUD_PX5,
978 };
979 
980 static const unsigned gpio_x6_aud_px6_pins[] = {
981 	TEGRA_PIN_GPIO_X6_AUD_PX6,
982 };
983 
984 static const unsigned gpio_x7_aud_px7_pins[] = {
985 	TEGRA_PIN_GPIO_X7_AUD_PX7,
986 };
987 
988 static const unsigned ulpi_clk_py0_pins[] = {
989 	TEGRA_PIN_ULPI_CLK_PY0,
990 };
991 
992 static const unsigned ulpi_dir_py1_pins[] = {
993 	TEGRA_PIN_ULPI_DIR_PY1,
994 };
995 
996 static const unsigned ulpi_nxt_py2_pins[] = {
997 	TEGRA_PIN_ULPI_NXT_PY2,
998 };
999 
1000 static const unsigned ulpi_stp_py3_pins[] = {
1001 	TEGRA_PIN_ULPI_STP_PY3,
1002 };
1003 
1004 static const unsigned sdmmc1_dat3_py4_pins[] = {
1005 	TEGRA_PIN_SDMMC1_DAT3_PY4,
1006 };
1007 
1008 static const unsigned sdmmc1_dat2_py5_pins[] = {
1009 	TEGRA_PIN_SDMMC1_DAT2_PY5,
1010 };
1011 
1012 static const unsigned sdmmc1_dat1_py6_pins[] = {
1013 	TEGRA_PIN_SDMMC1_DAT1_PY6,
1014 };
1015 
1016 static const unsigned sdmmc1_dat0_py7_pins[] = {
1017 	TEGRA_PIN_SDMMC1_DAT0_PY7,
1018 };
1019 
1020 static const unsigned sdmmc1_clk_pz0_pins[] = {
1021 	TEGRA_PIN_SDMMC1_CLK_PZ0,
1022 };
1023 
1024 static const unsigned sdmmc1_cmd_pz1_pins[] = {
1025 	TEGRA_PIN_SDMMC1_CMD_PZ1,
1026 };
1027 
1028 static const unsigned pwr_i2c_scl_pz6_pins[] = {
1029 	TEGRA_PIN_PWR_I2C_SCL_PZ6,
1030 };
1031 
1032 static const unsigned pwr_i2c_sda_pz7_pins[] = {
1033 	TEGRA_PIN_PWR_I2C_SDA_PZ7,
1034 };
1035 
1036 static const unsigned sdmmc4_dat0_paa0_pins[] = {
1037 	TEGRA_PIN_SDMMC4_DAT0_PAA0,
1038 };
1039 
1040 static const unsigned sdmmc4_dat1_paa1_pins[] = {
1041 	TEGRA_PIN_SDMMC4_DAT1_PAA1,
1042 };
1043 
1044 static const unsigned sdmmc4_dat2_paa2_pins[] = {
1045 	TEGRA_PIN_SDMMC4_DAT2_PAA2,
1046 };
1047 
1048 static const unsigned sdmmc4_dat3_paa3_pins[] = {
1049 	TEGRA_PIN_SDMMC4_DAT3_PAA3,
1050 };
1051 
1052 static const unsigned sdmmc4_dat4_paa4_pins[] = {
1053 	TEGRA_PIN_SDMMC4_DAT4_PAA4,
1054 };
1055 
1056 static const unsigned sdmmc4_dat5_paa5_pins[] = {
1057 	TEGRA_PIN_SDMMC4_DAT5_PAA5,
1058 };
1059 
1060 static const unsigned sdmmc4_dat6_paa6_pins[] = {
1061 	TEGRA_PIN_SDMMC4_DAT6_PAA6,
1062 };
1063 
1064 static const unsigned sdmmc4_dat7_paa7_pins[] = {
1065 	TEGRA_PIN_SDMMC4_DAT7_PAA7,
1066 };
1067 
1068 static const unsigned pbb0_pins[] = {
1069 	TEGRA_PIN_PBB0,
1070 };
1071 
1072 static const unsigned cam_i2c_scl_pbb1_pins[] = {
1073 	TEGRA_PIN_CAM_I2C_SCL_PBB1,
1074 };
1075 
1076 static const unsigned cam_i2c_sda_pbb2_pins[] = {
1077 	TEGRA_PIN_CAM_I2C_SDA_PBB2,
1078 };
1079 
1080 static const unsigned pbb3_pins[] = {
1081 	TEGRA_PIN_PBB3,
1082 };
1083 
1084 static const unsigned pbb4_pins[] = {
1085 	TEGRA_PIN_PBB4,
1086 };
1087 
1088 static const unsigned pbb5_pins[] = {
1089 	TEGRA_PIN_PBB5,
1090 };
1091 
1092 static const unsigned pbb6_pins[] = {
1093 	TEGRA_PIN_PBB6,
1094 };
1095 
1096 static const unsigned pbb7_pins[] = {
1097 	TEGRA_PIN_PBB7,
1098 };
1099 
1100 static const unsigned cam_mclk_pcc0_pins[] = {
1101 	TEGRA_PIN_CAM_MCLK_PCC0,
1102 };
1103 
1104 static const unsigned pcc1_pins[] = {
1105 	TEGRA_PIN_PCC1,
1106 };
1107 
1108 static const unsigned pcc2_pins[] = {
1109 	TEGRA_PIN_PCC2,
1110 };
1111 
1112 static const unsigned sdmmc4_clk_pcc4_pins[] = {
1113 	TEGRA_PIN_SDMMC4_CLK_PCC4,
1114 };
1115 
1116 static const unsigned clk2_req_pcc5_pins[] = {
1117 	TEGRA_PIN_CLK2_REQ_PCC5,
1118 };
1119 
1120 static const unsigned pex_l0_rst_n_pdd1_pins[] = {
1121 	TEGRA_PIN_PEX_L0_RST_N_PDD1,
1122 };
1123 
1124 static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
1125 	TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1126 };
1127 
1128 static const unsigned pex_wake_n_pdd3_pins[] = {
1129 	TEGRA_PIN_PEX_WAKE_N_PDD3,
1130 };
1131 
1132 static const unsigned pex_l1_rst_n_pdd5_pins[] = {
1133 	TEGRA_PIN_PEX_L1_RST_N_PDD5,
1134 };
1135 
1136 static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
1137 	TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1138 };
1139 
1140 static const unsigned clk3_out_pee0_pins[] = {
1141 	TEGRA_PIN_CLK3_OUT_PEE0,
1142 };
1143 
1144 static const unsigned clk3_req_pee1_pins[] = {
1145 	TEGRA_PIN_CLK3_REQ_PEE1,
1146 };
1147 
1148 static const unsigned dap_mclk1_req_pee2_pins[] = {
1149 	TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1150 };
1151 
1152 static const unsigned hdmi_cec_pee3_pins[] = {
1153 	TEGRA_PIN_HDMI_CEC_PEE3,
1154 };
1155 
1156 static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1157 	TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1158 };
1159 
1160 static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1161 	TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1162 };
1163 
1164 static const unsigned dp_hpd_pff0_pins[] = {
1165 	TEGRA_PIN_DP_HPD_PFF0,
1166 };
1167 
1168 static const unsigned usb_vbus_en2_pff1_pins[] = {
1169 	TEGRA_PIN_USB_VBUS_EN2_PFF1,
1170 };
1171 
1172 static const unsigned pff2_pins[] = {
1173 	TEGRA_PIN_PFF2,
1174 };
1175 
1176 static const unsigned core_pwr_req_pins[] = {
1177 	TEGRA_PIN_CORE_PWR_REQ,
1178 };
1179 
1180 static const unsigned cpu_pwr_req_pins[] = {
1181 	TEGRA_PIN_CPU_PWR_REQ,
1182 };
1183 
1184 static const unsigned pwr_int_n_pins[] = {
1185 	TEGRA_PIN_PWR_INT_N,
1186 };
1187 
1188 static const unsigned gmi_clk_lb_pins[] = {
1189 	TEGRA_PIN_GMI_CLK_LB,
1190 };
1191 
1192 static const unsigned reset_out_n_pins[] = {
1193 	TEGRA_PIN_RESET_OUT_N,
1194 };
1195 
1196 static const unsigned owr_pins[] = {
1197 	TEGRA_PIN_OWR,
1198 };
1199 
1200 static const unsigned clk_32k_in_pins[] = {
1201 	TEGRA_PIN_CLK_32K_IN,
1202 };
1203 
1204 static const unsigned jtag_rtck_pins[] = {
1205 	TEGRA_PIN_JTAG_RTCK,
1206 };
1207 
1208 static const unsigned drive_ao1_pins[] = {
1209 	TEGRA_PIN_KB_ROW0_PR0,
1210 	TEGRA_PIN_KB_ROW1_PR1,
1211 	TEGRA_PIN_KB_ROW2_PR2,
1212 	TEGRA_PIN_KB_ROW3_PR3,
1213 	TEGRA_PIN_KB_ROW4_PR4,
1214 	TEGRA_PIN_KB_ROW5_PR5,
1215 	TEGRA_PIN_KB_ROW6_PR6,
1216 	TEGRA_PIN_KB_ROW7_PR7,
1217 	TEGRA_PIN_PWR_I2C_SCL_PZ6,
1218 	TEGRA_PIN_PWR_I2C_SDA_PZ7,
1219 };
1220 
1221 static const unsigned drive_ao2_pins[] = {
1222 	TEGRA_PIN_CLK_32K_OUT_PA0,
1223 	TEGRA_PIN_CLK_32K_IN,
1224 	TEGRA_PIN_KB_COL0_PQ0,
1225 	TEGRA_PIN_KB_COL1_PQ1,
1226 	TEGRA_PIN_KB_COL2_PQ2,
1227 	TEGRA_PIN_KB_COL3_PQ3,
1228 	TEGRA_PIN_KB_COL4_PQ4,
1229 	TEGRA_PIN_KB_COL5_PQ5,
1230 	TEGRA_PIN_KB_COL6_PQ6,
1231 	TEGRA_PIN_KB_COL7_PQ7,
1232 	TEGRA_PIN_KB_ROW8_PS0,
1233 	TEGRA_PIN_KB_ROW9_PS1,
1234 	TEGRA_PIN_KB_ROW10_PS2,
1235 	TEGRA_PIN_KB_ROW11_PS3,
1236 	TEGRA_PIN_KB_ROW12_PS4,
1237 	TEGRA_PIN_KB_ROW13_PS5,
1238 	TEGRA_PIN_KB_ROW14_PS6,
1239 	TEGRA_PIN_KB_ROW15_PS7,
1240 	TEGRA_PIN_KB_ROW16_PT0,
1241 	TEGRA_PIN_KB_ROW17_PT1,
1242 	TEGRA_PIN_SDMMC3_CD_N_PV2,
1243 	TEGRA_PIN_CORE_PWR_REQ,
1244 	TEGRA_PIN_CPU_PWR_REQ,
1245 	TEGRA_PIN_PWR_INT_N,
1246 };
1247 
1248 static const unsigned drive_at1_pins[] = {
1249 	TEGRA_PIN_PH0,
1250 	TEGRA_PIN_PH1,
1251 	TEGRA_PIN_PH2,
1252 	TEGRA_PIN_PH3,
1253 };
1254 
1255 static const unsigned drive_at2_pins[] = {
1256 	TEGRA_PIN_PG0,
1257 	TEGRA_PIN_PG1,
1258 	TEGRA_PIN_PG2,
1259 	TEGRA_PIN_PG3,
1260 	TEGRA_PIN_PG4,
1261 	TEGRA_PIN_PG5,
1262 	TEGRA_PIN_PG6,
1263 	TEGRA_PIN_PG7,
1264 	TEGRA_PIN_PI0,
1265 	TEGRA_PIN_PI1,
1266 	TEGRA_PIN_PI3,
1267 	TEGRA_PIN_PI4,
1268 	TEGRA_PIN_PI7,
1269 	TEGRA_PIN_PK0,
1270 	TEGRA_PIN_PK2,
1271 };
1272 
1273 static const unsigned drive_at3_pins[] = {
1274 	TEGRA_PIN_PC7,
1275 	TEGRA_PIN_PJ0,
1276 };
1277 
1278 static const unsigned drive_at4_pins[] = {
1279 	TEGRA_PIN_PB0,
1280 	TEGRA_PIN_PB1,
1281 	TEGRA_PIN_PJ0,
1282 	TEGRA_PIN_PJ7,
1283 	TEGRA_PIN_PK7,
1284 };
1285 
1286 static const unsigned drive_at5_pins[] = {
1287 	TEGRA_PIN_GEN2_I2C_SCL_PT5,
1288 	TEGRA_PIN_GEN2_I2C_SDA_PT6,
1289 };
1290 
1291 static const unsigned drive_cdev1_pins[] = {
1292 	TEGRA_PIN_DAP_MCLK1_PW4,
1293 	TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1294 };
1295 
1296 static const unsigned drive_cdev2_pins[] = {
1297 	TEGRA_PIN_CLK2_OUT_PW5,
1298 	TEGRA_PIN_CLK2_REQ_PCC5,
1299 };
1300 
1301 static const unsigned drive_dap1_pins[] = {
1302 	TEGRA_PIN_DAP1_FS_PN0,
1303 	TEGRA_PIN_DAP1_DIN_PN1,
1304 	TEGRA_PIN_DAP1_DOUT_PN2,
1305 	TEGRA_PIN_DAP1_SCLK_PN3,
1306 };
1307 
1308 static const unsigned drive_dap2_pins[] = {
1309 	TEGRA_PIN_DAP2_FS_PA2,
1310 	TEGRA_PIN_DAP2_SCLK_PA3,
1311 	TEGRA_PIN_DAP2_DIN_PA4,
1312 	TEGRA_PIN_DAP2_DOUT_PA5,
1313 };
1314 
1315 static const unsigned drive_dap3_pins[] = {
1316 	TEGRA_PIN_DAP3_FS_PP0,
1317 	TEGRA_PIN_DAP3_DIN_PP1,
1318 	TEGRA_PIN_DAP3_DOUT_PP2,
1319 	TEGRA_PIN_DAP3_SCLK_PP3,
1320 };
1321 
1322 static const unsigned drive_dap4_pins[] = {
1323 	TEGRA_PIN_DAP4_FS_PP4,
1324 	TEGRA_PIN_DAP4_DIN_PP5,
1325 	TEGRA_PIN_DAP4_DOUT_PP6,
1326 	TEGRA_PIN_DAP4_SCLK_PP7,
1327 };
1328 
1329 static const unsigned drive_dbg_pins[] = {
1330 	TEGRA_PIN_GEN1_I2C_SCL_PC4,
1331 	TEGRA_PIN_GEN1_I2C_SDA_PC5,
1332 	TEGRA_PIN_PU0,
1333 	TEGRA_PIN_PU1,
1334 	TEGRA_PIN_PU2,
1335 	TEGRA_PIN_PU3,
1336 	TEGRA_PIN_PU4,
1337 	TEGRA_PIN_PU5,
1338 	TEGRA_PIN_PU6,
1339 };
1340 
1341 static const unsigned drive_sdio3_pins[] = {
1342 	TEGRA_PIN_SDMMC3_CLK_PA6,
1343 	TEGRA_PIN_SDMMC3_CMD_PA7,
1344 	TEGRA_PIN_SDMMC3_DAT3_PB4,
1345 	TEGRA_PIN_SDMMC3_DAT2_PB5,
1346 	TEGRA_PIN_SDMMC3_DAT1_PB6,
1347 	TEGRA_PIN_SDMMC3_DAT0_PB7,
1348 	TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1349 	TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1350 };
1351 
1352 static const unsigned drive_spi_pins[] = {
1353 	TEGRA_PIN_DVFS_PWM_PX0,
1354 	TEGRA_PIN_GPIO_X1_AUD_PX1,
1355 	TEGRA_PIN_DVFS_CLK_PX2,
1356 	TEGRA_PIN_GPIO_X3_AUD_PX3,
1357 	TEGRA_PIN_GPIO_X4_AUD_PX4,
1358 	TEGRA_PIN_GPIO_X5_AUD_PX5,
1359 	TEGRA_PIN_GPIO_X6_AUD_PX6,
1360 	TEGRA_PIN_GPIO_X7_AUD_PX7,
1361 	TEGRA_PIN_GPIO_W2_AUD_PW2,
1362 	TEGRA_PIN_GPIO_W3_AUD_PW3,
1363 };
1364 
1365 static const unsigned drive_uaa_pins[] = {
1366 	TEGRA_PIN_ULPI_DATA0_PO1,
1367 	TEGRA_PIN_ULPI_DATA1_PO2,
1368 	TEGRA_PIN_ULPI_DATA2_PO3,
1369 	TEGRA_PIN_ULPI_DATA3_PO4,
1370 };
1371 
1372 static const unsigned drive_uab_pins[] = {
1373 	TEGRA_PIN_ULPI_DATA7_PO0,
1374 	TEGRA_PIN_ULPI_DATA4_PO5,
1375 	TEGRA_PIN_ULPI_DATA5_PO6,
1376 	TEGRA_PIN_ULPI_DATA6_PO7,
1377 	TEGRA_PIN_PV0,
1378 	TEGRA_PIN_PV1,
1379 };
1380 
1381 static const unsigned drive_uart2_pins[] = {
1382 	TEGRA_PIN_UART2_TXD_PC2,
1383 	TEGRA_PIN_UART2_RXD_PC3,
1384 	TEGRA_PIN_UART2_CTS_N_PJ5,
1385 	TEGRA_PIN_UART2_RTS_N_PJ6,
1386 };
1387 
1388 static const unsigned drive_uart3_pins[] = {
1389 	TEGRA_PIN_UART3_CTS_N_PA1,
1390 	TEGRA_PIN_UART3_RTS_N_PC0,
1391 	TEGRA_PIN_UART3_TXD_PW6,
1392 	TEGRA_PIN_UART3_RXD_PW7,
1393 };
1394 
1395 static const unsigned drive_sdio1_pins[] = {
1396 	TEGRA_PIN_SDMMC1_DAT3_PY4,
1397 	TEGRA_PIN_SDMMC1_DAT2_PY5,
1398 	TEGRA_PIN_SDMMC1_DAT1_PY6,
1399 	TEGRA_PIN_SDMMC1_DAT0_PY7,
1400 	TEGRA_PIN_SDMMC1_CLK_PZ0,
1401 	TEGRA_PIN_SDMMC1_CMD_PZ1,
1402 };
1403 
1404 static const unsigned drive_ddc_pins[] = {
1405 	TEGRA_PIN_DDC_SCL_PV4,
1406 	TEGRA_PIN_DDC_SDA_PV5,
1407 };
1408 
1409 static const unsigned drive_gma_pins[] = {
1410 	TEGRA_PIN_SDMMC4_CLK_PCC4,
1411 	TEGRA_PIN_SDMMC4_CMD_PT7,
1412 	TEGRA_PIN_SDMMC4_DAT0_PAA0,
1413 	TEGRA_PIN_SDMMC4_DAT1_PAA1,
1414 	TEGRA_PIN_SDMMC4_DAT2_PAA2,
1415 	TEGRA_PIN_SDMMC4_DAT3_PAA3,
1416 	TEGRA_PIN_SDMMC4_DAT4_PAA4,
1417 	TEGRA_PIN_SDMMC4_DAT5_PAA5,
1418 	TEGRA_PIN_SDMMC4_DAT6_PAA6,
1419 	TEGRA_PIN_SDMMC4_DAT7_PAA7,
1420 };
1421 
1422 static const unsigned drive_gme_pins[] = {
1423 	TEGRA_PIN_PBB0,
1424 	TEGRA_PIN_CAM_I2C_SCL_PBB1,
1425 	TEGRA_PIN_CAM_I2C_SDA_PBB2,
1426 	TEGRA_PIN_PBB3,
1427 	TEGRA_PIN_PCC2,
1428 };
1429 
1430 static const unsigned drive_gmf_pins[] = {
1431 	TEGRA_PIN_PBB4,
1432 	TEGRA_PIN_PBB5,
1433 	TEGRA_PIN_PBB6,
1434 	TEGRA_PIN_PBB7,
1435 };
1436 
1437 static const unsigned drive_gmg_pins[] = {
1438 	TEGRA_PIN_CAM_MCLK_PCC0,
1439 };
1440 
1441 static const unsigned drive_gmh_pins[] = {
1442 	TEGRA_PIN_PCC1,
1443 };
1444 
1445 static const unsigned drive_owr_pins[] = {
1446 	TEGRA_PIN_SDMMC3_CD_N_PV2,
1447 	TEGRA_PIN_OWR,
1448 };
1449 
1450 static const unsigned drive_uda_pins[] = {
1451 	TEGRA_PIN_ULPI_CLK_PY0,
1452 	TEGRA_PIN_ULPI_DIR_PY1,
1453 	TEGRA_PIN_ULPI_NXT_PY2,
1454 	TEGRA_PIN_ULPI_STP_PY3,
1455 };
1456 
1457 static const unsigned drive_gpv_pins[] = {
1458 	TEGRA_PIN_PEX_L0_RST_N_PDD1,
1459 	TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1460 	TEGRA_PIN_PEX_WAKE_N_PDD3,
1461 	TEGRA_PIN_PEX_L1_RST_N_PDD5,
1462 	TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1463 	TEGRA_PIN_USB_VBUS_EN2_PFF1,
1464 	TEGRA_PIN_PFF2,
1465 };
1466 
1467 static const unsigned drive_dev3_pins[] = {
1468 	TEGRA_PIN_CLK3_OUT_PEE0,
1469 	TEGRA_PIN_CLK3_REQ_PEE1,
1470 };
1471 
1472 static const unsigned drive_cec_pins[] = {
1473 	TEGRA_PIN_HDMI_CEC_PEE3,
1474 };
1475 
1476 static const unsigned drive_at6_pins[] = {
1477 	TEGRA_PIN_PK1,
1478 	TEGRA_PIN_PK3,
1479 	TEGRA_PIN_PK4,
1480 	TEGRA_PIN_PI2,
1481 	TEGRA_PIN_PI5,
1482 	TEGRA_PIN_PI6,
1483 	TEGRA_PIN_PH4,
1484 	TEGRA_PIN_PH5,
1485 	TEGRA_PIN_PH6,
1486 	TEGRA_PIN_PH7,
1487 };
1488 
1489 static const unsigned drive_dap5_pins[] = {
1490 	TEGRA_PIN_SPDIF_IN_PK6,
1491 	TEGRA_PIN_SPDIF_OUT_PK5,
1492 	TEGRA_PIN_DP_HPD_PFF0,
1493 };
1494 
1495 static const unsigned drive_usb_vbus_en_pins[] = {
1496 	TEGRA_PIN_USB_VBUS_EN0_PN4,
1497 	TEGRA_PIN_USB_VBUS_EN1_PN5,
1498 };
1499 
1500 static const unsigned drive_ao3_pins[] = {
1501 	TEGRA_PIN_RESET_OUT_N,
1502 };
1503 
1504 static const unsigned drive_ao0_pins[] = {
1505 	TEGRA_PIN_JTAG_RTCK,
1506 };
1507 
1508 static const unsigned drive_hv0_pins[] = {
1509 	TEGRA_PIN_HDMI_INT_PN7,
1510 };
1511 
1512 static const unsigned drive_sdio4_pins[] = {
1513 	TEGRA_PIN_SDMMC1_WP_N_PV3,
1514 };
1515 
1516 static const unsigned drive_ao4_pins[] = {
1517 	TEGRA_PIN_JTAG_RTCK,
1518 };
1519 
1520 static const unsigned mipi_pad_ctrl_dsi_b_pins[] = {
1521 	TEGRA_PIN_DSI_B_CLK_P,
1522 	TEGRA_PIN_DSI_B_CLK_N,
1523 	TEGRA_PIN_DSI_B_D0_P,
1524 	TEGRA_PIN_DSI_B_D0_N,
1525 	TEGRA_PIN_DSI_B_D1_P,
1526 	TEGRA_PIN_DSI_B_D1_N,
1527 	TEGRA_PIN_DSI_B_D2_P,
1528 	TEGRA_PIN_DSI_B_D2_N,
1529 	TEGRA_PIN_DSI_B_D3_P,
1530 	TEGRA_PIN_DSI_B_D3_N,
1531 };
1532 
1533 enum tegra_mux {
1534 	TEGRA_MUX_BLINK,
1535 	TEGRA_MUX_CCLA,
1536 	TEGRA_MUX_CEC,
1537 	TEGRA_MUX_CLDVFS,
1538 	TEGRA_MUX_CLK,
1539 	TEGRA_MUX_CLK12,
1540 	TEGRA_MUX_CPU,
1541 	TEGRA_MUX_CSI,
1542 	TEGRA_MUX_DAP,
1543 	TEGRA_MUX_DAP1,
1544 	TEGRA_MUX_DAP2,
1545 	TEGRA_MUX_DEV3,
1546 	TEGRA_MUX_DISPLAYA,
1547 	TEGRA_MUX_DISPLAYA_ALT,
1548 	TEGRA_MUX_DISPLAYB,
1549 	TEGRA_MUX_DP,
1550 	TEGRA_MUX_DSI_B,
1551 	TEGRA_MUX_DTV,
1552 	TEGRA_MUX_EXTPERIPH1,
1553 	TEGRA_MUX_EXTPERIPH2,
1554 	TEGRA_MUX_EXTPERIPH3,
1555 	TEGRA_MUX_GMI,
1556 	TEGRA_MUX_GMI_ALT,
1557 	TEGRA_MUX_HDA,
1558 	TEGRA_MUX_HSI,
1559 	TEGRA_MUX_I2C1,
1560 	TEGRA_MUX_I2C2,
1561 	TEGRA_MUX_I2C3,
1562 	TEGRA_MUX_I2C4,
1563 	TEGRA_MUX_I2CPWR,
1564 	TEGRA_MUX_I2S0,
1565 	TEGRA_MUX_I2S1,
1566 	TEGRA_MUX_I2S2,
1567 	TEGRA_MUX_I2S3,
1568 	TEGRA_MUX_I2S4,
1569 	TEGRA_MUX_IRDA,
1570 	TEGRA_MUX_KBC,
1571 	TEGRA_MUX_OWR,
1572 	TEGRA_MUX_PE,
1573 	TEGRA_MUX_PE0,
1574 	TEGRA_MUX_PE1,
1575 	TEGRA_MUX_PMI,
1576 	TEGRA_MUX_PWM0,
1577 	TEGRA_MUX_PWM1,
1578 	TEGRA_MUX_PWM2,
1579 	TEGRA_MUX_PWM3,
1580 	TEGRA_MUX_PWRON,
1581 	TEGRA_MUX_RESET_OUT_N,
1582 	TEGRA_MUX_RSVD1,
1583 	TEGRA_MUX_RSVD2,
1584 	TEGRA_MUX_RSVD3,
1585 	TEGRA_MUX_RSVD4,
1586 	TEGRA_MUX_RTCK,
1587 	TEGRA_MUX_SATA,
1588 	TEGRA_MUX_SDMMC1,
1589 	TEGRA_MUX_SDMMC2,
1590 	TEGRA_MUX_SDMMC3,
1591 	TEGRA_MUX_SDMMC4,
1592 	TEGRA_MUX_SOC,
1593 	TEGRA_MUX_SPDIF,
1594 	TEGRA_MUX_SPI1,
1595 	TEGRA_MUX_SPI2,
1596 	TEGRA_MUX_SPI3,
1597 	TEGRA_MUX_SPI4,
1598 	TEGRA_MUX_SPI5,
1599 	TEGRA_MUX_SPI6,
1600 	TEGRA_MUX_SYS,
1601 	TEGRA_MUX_TMDS,
1602 	TEGRA_MUX_TRACE,
1603 	TEGRA_MUX_UARTA,
1604 	TEGRA_MUX_UARTB,
1605 	TEGRA_MUX_UARTC,
1606 	TEGRA_MUX_UARTD,
1607 	TEGRA_MUX_ULPI,
1608 	TEGRA_MUX_USB,
1609 	TEGRA_MUX_VGP1,
1610 	TEGRA_MUX_VGP2,
1611 	TEGRA_MUX_VGP3,
1612 	TEGRA_MUX_VGP4,
1613 	TEGRA_MUX_VGP5,
1614 	TEGRA_MUX_VGP6,
1615 	TEGRA_MUX_VI,
1616 	TEGRA_MUX_VI_ALT1,
1617 	TEGRA_MUX_VI_ALT3,
1618 	TEGRA_MUX_VIMCLK2,
1619 	TEGRA_MUX_VIMCLK2_ALT,
1620 };
1621 
1622 #define FUNCTION(fname)					\
1623 	{						\
1624 		.name = #fname,				\
1625 	}
1626 
1627 static struct tegra_function tegra124_functions[] = {
1628 	FUNCTION(blink),
1629 	FUNCTION(ccla),
1630 	FUNCTION(cec),
1631 	FUNCTION(cldvfs),
1632 	FUNCTION(clk),
1633 	FUNCTION(clk12),
1634 	FUNCTION(cpu),
1635 	FUNCTION(csi),
1636 	FUNCTION(dap),
1637 	FUNCTION(dap1),
1638 	FUNCTION(dap2),
1639 	FUNCTION(dev3),
1640 	FUNCTION(displaya),
1641 	FUNCTION(displaya_alt),
1642 	FUNCTION(displayb),
1643 	FUNCTION(dp),
1644 	FUNCTION(dsi_b),
1645 	FUNCTION(dtv),
1646 	FUNCTION(extperiph1),
1647 	FUNCTION(extperiph2),
1648 	FUNCTION(extperiph3),
1649 	FUNCTION(gmi),
1650 	FUNCTION(gmi_alt),
1651 	FUNCTION(hda),
1652 	FUNCTION(hsi),
1653 	FUNCTION(i2c1),
1654 	FUNCTION(i2c2),
1655 	FUNCTION(i2c3),
1656 	FUNCTION(i2c4),
1657 	FUNCTION(i2cpwr),
1658 	FUNCTION(i2s0),
1659 	FUNCTION(i2s1),
1660 	FUNCTION(i2s2),
1661 	FUNCTION(i2s3),
1662 	FUNCTION(i2s4),
1663 	FUNCTION(irda),
1664 	FUNCTION(kbc),
1665 	FUNCTION(owr),
1666 	FUNCTION(pe),
1667 	FUNCTION(pe0),
1668 	FUNCTION(pe1),
1669 	FUNCTION(pmi),
1670 	FUNCTION(pwm0),
1671 	FUNCTION(pwm1),
1672 	FUNCTION(pwm2),
1673 	FUNCTION(pwm3),
1674 	FUNCTION(pwron),
1675 	FUNCTION(reset_out_n),
1676 	FUNCTION(rsvd1),
1677 	FUNCTION(rsvd2),
1678 	FUNCTION(rsvd3),
1679 	FUNCTION(rsvd4),
1680 	FUNCTION(rtck),
1681 	FUNCTION(sata),
1682 	FUNCTION(sdmmc1),
1683 	FUNCTION(sdmmc2),
1684 	FUNCTION(sdmmc3),
1685 	FUNCTION(sdmmc4),
1686 	FUNCTION(soc),
1687 	FUNCTION(spdif),
1688 	FUNCTION(spi1),
1689 	FUNCTION(spi2),
1690 	FUNCTION(spi3),
1691 	FUNCTION(spi4),
1692 	FUNCTION(spi5),
1693 	FUNCTION(spi6),
1694 	FUNCTION(sys),
1695 	FUNCTION(tmds),
1696 	FUNCTION(trace),
1697 	FUNCTION(uarta),
1698 	FUNCTION(uartb),
1699 	FUNCTION(uartc),
1700 	FUNCTION(uartd),
1701 	FUNCTION(ulpi),
1702 	FUNCTION(usb),
1703 	FUNCTION(vgp1),
1704 	FUNCTION(vgp2),
1705 	FUNCTION(vgp3),
1706 	FUNCTION(vgp4),
1707 	FUNCTION(vgp5),
1708 	FUNCTION(vgp6),
1709 	FUNCTION(vi),
1710 	FUNCTION(vi_alt1),
1711 	FUNCTION(vi_alt3),
1712 	FUNCTION(vimclk2),
1713 	FUNCTION(vimclk2_alt),
1714 };
1715 
1716 #define DRV_PINGROUP_REG_A		0x868	/* bank 0 */
1717 #define PINGROUP_REG_A			0x3000	/* bank 1 */
1718 #define MIPI_PAD_CTRL_PINGROUP_REG_A	0x820	/* bank 2 */
1719 
1720 #define DRV_PINGROUP_REG(r)		((r) - DRV_PINGROUP_REG_A)
1721 #define PINGROUP_REG(r)			((r) - PINGROUP_REG_A)
1722 #define MIPI_PAD_CTRL_PINGROUP_REG_Y(r)	((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
1723 
1724 #define PINGROUP_BIT_Y(b)		(b)
1725 #define PINGROUP_BIT_N(b)		(-1)
1726 
1727 #define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel)		\
1728 	{								\
1729 		.name = #pg_name,					\
1730 		.pins = pg_name##_pins,					\
1731 		.npins = ARRAY_SIZE(pg_name##_pins),			\
1732 		.funcs = {						\
1733 			TEGRA_MUX_##f0,					\
1734 			TEGRA_MUX_##f1,					\
1735 			TEGRA_MUX_##f2,					\
1736 			TEGRA_MUX_##f3,					\
1737 		},							\
1738 		.mux_reg = PINGROUP_REG(r),				\
1739 		.mux_bank = 1,						\
1740 		.mux_bit = 0,						\
1741 		.pupd_reg = PINGROUP_REG(r),				\
1742 		.pupd_bank = 1,						\
1743 		.pupd_bit = 2,						\
1744 		.tri_reg = PINGROUP_REG(r),				\
1745 		.tri_bank = 1,						\
1746 		.tri_bit = 4,						\
1747 		.einput_bit = 5,					\
1748 		.odrain_bit = PINGROUP_BIT_##od(6),			\
1749 		.lock_bit = 7,						\
1750 		.ioreset_bit = PINGROUP_BIT_##ior(8),			\
1751 		.rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9),		\
1752 		.parked_bit = -1,					\
1753 		.drv_reg = -1,						\
1754 	}
1755 
1756 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b,	\
1757 		     drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w,		\
1758 		     slwf_b, slwf_w, drvtype)				\
1759 	{								\
1760 		.name = "drive_" #pg_name,				\
1761 		.pins = drive_##pg_name##_pins,				\
1762 		.npins = ARRAY_SIZE(drive_##pg_name##_pins),		\
1763 		.mux_reg = -1,						\
1764 		.pupd_reg = -1,						\
1765 		.tri_reg = -1,						\
1766 		.einput_bit = -1,					\
1767 		.odrain_bit = -1,					\
1768 		.lock_bit = -1,						\
1769 		.ioreset_bit = -1,					\
1770 		.rcv_sel_bit = -1,					\
1771 		.drv_reg = DRV_PINGROUP_REG(r),				\
1772 		.drv_bank = 0,						\
1773 		.parked_bit = -1,					\
1774 		.hsm_bit = hsm_b,					\
1775 		.schmitt_bit = schmitt_b,				\
1776 		.lpmd_bit = lpmd_b,					\
1777 		.drvdn_bit = drvdn_b,					\
1778 		.drvdn_width = drvdn_w,					\
1779 		.drvup_bit = drvup_b,					\
1780 		.drvup_width = drvup_w,					\
1781 		.slwr_bit = slwr_b,					\
1782 		.slwr_width = slwr_w,					\
1783 		.slwf_bit = slwf_b,					\
1784 		.slwf_width = slwf_w,					\
1785 		.drvtype_bit = PINGROUP_BIT_##drvtype(6),		\
1786 	}
1787 
1788 #define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1)			\
1789 	{								\
1790 		.name = "mipi_pad_ctrl_" #pg_name,			\
1791 		.pins = mipi_pad_ctrl_##pg_name##_pins,			\
1792 		.npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins),	\
1793 		.funcs = {						\
1794 			TEGRA_MUX_ ## f0,				\
1795 			TEGRA_MUX_ ## f1,				\
1796 			TEGRA_MUX_RSVD3,				\
1797 			TEGRA_MUX_RSVD4,				\
1798 		},							\
1799 		.mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r),		\
1800 		.mux_bank = 2,						\
1801 		.mux_bit = b,						\
1802 		.pupd_reg = -1,						\
1803 		.tri_reg = -1,						\
1804 		.einput_bit = -1,					\
1805 		.odrain_bit = -1,					\
1806 		.lock_bit = -1,						\
1807 		.ioreset_bit = -1,					\
1808 		.rcv_sel_bit = -1,					\
1809 		.drv_reg = -1,						\
1810 	}
1811 
1812 static const struct tegra_pingroup tegra124_groups[] = {
1813 	/*       pg_name,                f0,         f1,         f2,           f3,          r,      od, ior, rcv_sel */
1814 	PINGROUP(ulpi_data0_po1,         SPI3,       HSI,        UARTA,        ULPI,        0x3000, N,   N,  N),
1815 	PINGROUP(ulpi_data1_po2,         SPI3,       HSI,        UARTA,        ULPI,        0x3004, N,   N,  N),
1816 	PINGROUP(ulpi_data2_po3,         SPI3,       HSI,        UARTA,        ULPI,        0x3008, N,   N,  N),
1817 	PINGROUP(ulpi_data3_po4,         SPI3,       HSI,        UARTA,        ULPI,        0x300c, N,   N,  N),
1818 	PINGROUP(ulpi_data4_po5,         SPI2,       HSI,        UARTA,        ULPI,        0x3010, N,   N,  N),
1819 	PINGROUP(ulpi_data5_po6,         SPI2,       HSI,        UARTA,        ULPI,        0x3014, N,   N,  N),
1820 	PINGROUP(ulpi_data6_po7,         SPI2,       HSI,        UARTA,        ULPI,        0x3018, N,   N,  N),
1821 	PINGROUP(ulpi_data7_po0,         SPI2,       HSI,        UARTA,        ULPI,        0x301c, N,   N,  N),
1822 	PINGROUP(ulpi_clk_py0,           SPI1,       SPI5,       UARTD,        ULPI,        0x3020, N,   N,  N),
1823 	PINGROUP(ulpi_dir_py1,           SPI1,       SPI5,       UARTD,        ULPI,        0x3024, N,   N,  N),
1824 	PINGROUP(ulpi_nxt_py2,           SPI1,       SPI5,       UARTD,        ULPI,        0x3028, N,   N,  N),
1825 	PINGROUP(ulpi_stp_py3,           SPI1,       SPI5,       UARTD,        ULPI,        0x302c, N,   N,  N),
1826 	PINGROUP(dap3_fs_pp0,            I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    0x3030, N,   N,  N),
1827 	PINGROUP(dap3_din_pp1,           I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    0x3034, N,   N,  N),
1828 	PINGROUP(dap3_dout_pp2,          I2S2,       SPI5,       DISPLAYA,     RSVD4,       0x3038, N,   N,  N),
1829 	PINGROUP(dap3_sclk_pp3,          I2S2,       SPI5,       RSVD3,        DISPLAYB,    0x303c, N,   N,  N),
1830 	PINGROUP(pv0,                    RSVD1,      RSVD2,      RSVD3,        RSVD4,       0x3040, N,   N,  N),
1831 	PINGROUP(pv1,                    RSVD1,      RSVD2,      RSVD3,        RSVD4,       0x3044, N,   N,  N),
1832 	PINGROUP(sdmmc1_clk_pz0,         SDMMC1,     CLK12,      RSVD3,        RSVD4,       0x3048, N,   N,  N),
1833 	PINGROUP(sdmmc1_cmd_pz1,         SDMMC1,     SPDIF,      SPI4,         UARTA,       0x304c, N,   N,  N),
1834 	PINGROUP(sdmmc1_dat3_py4,        SDMMC1,     SPDIF,      SPI4,         UARTA,       0x3050, N,   N,  N),
1835 	PINGROUP(sdmmc1_dat2_py5,        SDMMC1,     PWM0,       SPI4,         UARTA,       0x3054, N,   N,  N),
1836 	PINGROUP(sdmmc1_dat1_py6,        SDMMC1,     PWM1,       SPI4,         UARTA,       0x3058, N,   N,  N),
1837 	PINGROUP(sdmmc1_dat0_py7,        SDMMC1,     RSVD2,      SPI4,         UARTA,       0x305c, N,   N,  N),
1838 	PINGROUP(clk2_out_pw5,           EXTPERIPH2, RSVD2,      RSVD3,        RSVD4,       0x3068, N,   N,  N),
1839 	PINGROUP(clk2_req_pcc5,          DAP,        RSVD2,      RSVD3,        RSVD4,       0x306c, N,   N,  N),
1840 	PINGROUP(hdmi_int_pn7,           RSVD1,      RSVD2,      RSVD3,        RSVD4,       0x3110, N,   N,  Y),
1841 	PINGROUP(ddc_scl_pv4,            I2C4,       RSVD2,      RSVD3,        RSVD4,       0x3114, N,   N,  Y),
1842 	PINGROUP(ddc_sda_pv5,            I2C4,       RSVD2,      RSVD3,        RSVD4,       0x3118, N,   N,  Y),
1843 	PINGROUP(uart2_rxd_pc3,          IRDA,       SPDIF,      UARTA,        SPI4,        0x3164, N,   N,  N),
1844 	PINGROUP(uart2_txd_pc2,          IRDA,       SPDIF,      UARTA,        SPI4,        0x3168, N,   N,  N),
1845 	PINGROUP(uart2_rts_n_pj6,        UARTA,      UARTB,      GMI,          SPI4,        0x316c, N,   N,  N),
1846 	PINGROUP(uart2_cts_n_pj5,        UARTA,      UARTB,      GMI,          SPI4,        0x3170, N,   N,  N),
1847 	PINGROUP(uart3_txd_pw6,          UARTC,      RSVD2,      GMI,          SPI4,        0x3174, N,   N,  N),
1848 	PINGROUP(uart3_rxd_pw7,          UARTC,      RSVD2,      GMI,          SPI4,        0x3178, N,   N,  N),
1849 	PINGROUP(uart3_cts_n_pa1,        UARTC,      SDMMC1,     DTV,          GMI,         0x317c, N,   N,  N),
1850 	PINGROUP(uart3_rts_n_pc0,        UARTC,      PWM0,       DTV,          GMI,         0x3180, N,   N,  N),
1851 	PINGROUP(pu0,                    OWR,        UARTA,      GMI,          RSVD4,       0x3184, N,   N,  N),
1852 	PINGROUP(pu1,                    RSVD1,      UARTA,      GMI,          RSVD4,       0x3188, N,   N,  N),
1853 	PINGROUP(pu2,                    RSVD1,      UARTA,      GMI,          RSVD4,       0x318c, N,   N,  N),
1854 	PINGROUP(pu3,                    PWM0,       UARTA,      GMI,          DISPLAYB,    0x3190, N,   N,  N),
1855 	PINGROUP(pu4,                    PWM1,       UARTA,      GMI,          DISPLAYB,    0x3194, N,   N,  N),
1856 	PINGROUP(pu5,                    PWM2,       UARTA,      GMI,          DISPLAYB,    0x3198, N,   N,  N),
1857 	PINGROUP(pu6,                    PWM3,       UARTA,      RSVD3,        GMI,         0x319c, N,   N,  N),
1858 	PINGROUP(gen1_i2c_sda_pc5,       I2C1,       RSVD2,      RSVD3,        RSVD4,       0x31a0, Y,   N,  N),
1859 	PINGROUP(gen1_i2c_scl_pc4,       I2C1,       RSVD2,      RSVD3,        RSVD4,       0x31a4, Y,   N,  N),
1860 	PINGROUP(dap4_fs_pp4,            I2S3,       GMI,        DTV,          RSVD4,       0x31a8, N,   N,  N),
1861 	PINGROUP(dap4_din_pp5,           I2S3,       GMI,        RSVD3,        RSVD4,       0x31ac, N,   N,  N),
1862 	PINGROUP(dap4_dout_pp6,          I2S3,       GMI,        DTV,          RSVD4,       0x31b0, N,   N,  N),
1863 	PINGROUP(dap4_sclk_pp7,          I2S3,       GMI,        RSVD3,        RSVD4,       0x31b4, N,   N,  N),
1864 	PINGROUP(clk3_out_pee0,          EXTPERIPH3, RSVD2,      RSVD3,        RSVD4,       0x31b8, N,   N,  N),
1865 	PINGROUP(clk3_req_pee1,          DEV3,       RSVD2,      RSVD3,        RSVD4,       0x31bc, N,   N,  N),
1866 	PINGROUP(pc7,                    RSVD1,      RSVD2,      GMI,          GMI_ALT,     0x31c0, N,   N,  N),
1867 	PINGROUP(pi5,                    SDMMC2,     RSVD2,      GMI,          RSVD4,       0x31c4, N,   N,  N),
1868 	PINGROUP(pi7,                    RSVD1,      TRACE,      GMI,          DTV,         0x31c8, N,   N,  N),
1869 	PINGROUP(pk0,                    RSVD1,      SDMMC3,     GMI,          SOC,         0x31cc, N,   N,  N),
1870 	PINGROUP(pk1,                    SDMMC2,     TRACE,      GMI,          RSVD4,       0x31d0, N,   N,  N),
1871 	PINGROUP(pj0,                    RSVD1,      RSVD2,      GMI,          USB,         0x31d4, N,   N,  N),
1872 	PINGROUP(pj2,                    RSVD1,      RSVD2,      GMI,          SOC,         0x31d8, N,   N,  N),
1873 	PINGROUP(pk3,                    SDMMC2,     TRACE,      GMI,          CCLA,        0x31dc, N,   N,  N),
1874 	PINGROUP(pk4,                    SDMMC2,     RSVD2,      GMI,          GMI_ALT,     0x31e0, N,   N,  N),
1875 	PINGROUP(pk2,                    RSVD1,      RSVD2,      GMI,          RSVD4,       0x31e4, N,   N,  N),
1876 	PINGROUP(pi3,                    RSVD1,      RSVD2,      GMI,          SPI4,        0x31e8, N,   N,  N),
1877 	PINGROUP(pi6,                    RSVD1,      RSVD2,      GMI,          SDMMC2,      0x31ec, N,   N,  N),
1878 	PINGROUP(pg0,                    RSVD1,      RSVD2,      GMI,          RSVD4,       0x31f0, N,   N,  N),
1879 	PINGROUP(pg1,                    RSVD1,      RSVD2,      GMI,          RSVD4,       0x31f4, N,   N,  N),
1880 	PINGROUP(pg2,                    RSVD1,      TRACE,      GMI,          RSVD4,       0x31f8, N,   N,  N),
1881 	PINGROUP(pg3,                    RSVD1,      TRACE,      GMI,          RSVD4,       0x31fc, N,   N,  N),
1882 	PINGROUP(pg4,                    RSVD1,      TMDS,       GMI,          SPI4,        0x3200, N,   N,  N),
1883 	PINGROUP(pg5,                    RSVD1,      RSVD2,      GMI,          SPI4,        0x3204, N,   N,  N),
1884 	PINGROUP(pg6,                    RSVD1,      RSVD2,      GMI,          SPI4,        0x3208, N,   N,  N),
1885 	PINGROUP(pg7,                    RSVD1,      RSVD2,      GMI,          SPI4,        0x320c, N,   N,  N),
1886 	PINGROUP(ph0,                    PWM0,       TRACE,      GMI,          DTV,         0x3210, N,   N,  N),
1887 	PINGROUP(ph1,                    PWM1,       TMDS,       GMI,          DISPLAYA,    0x3214, N,   N,  N),
1888 	PINGROUP(ph2,                    PWM2,       TMDS,       GMI,          CLDVFS,      0x3218, N,   N,  N),
1889 	PINGROUP(ph3,                    PWM3,       SPI4,       GMI,          CLDVFS,      0x321c, N,   N,  N),
1890 	PINGROUP(ph4,                    SDMMC2,     RSVD2,      GMI,          RSVD4,       0x3220, N,   N,  N),
1891 	PINGROUP(ph5,                    SDMMC2,     RSVD2,      GMI,          RSVD4,       0x3224, N,   N,  N),
1892 	PINGROUP(ph6,                    SDMMC2,     TRACE,      GMI,          DTV,         0x3228, N,   N,  N),
1893 	PINGROUP(ph7,                    SDMMC2,     TRACE,      GMI,          DTV,         0x322c, N,   N,  N),
1894 	PINGROUP(pj7,                    UARTD,      RSVD2,      GMI,          GMI_ALT,     0x3230, N,   N,  N),
1895 	PINGROUP(pb0,                    UARTD,      RSVD2,      GMI,          RSVD4,       0x3234, N,   N,  N),
1896 	PINGROUP(pb1,                    UARTD,      RSVD2,      GMI,          RSVD4,       0x3238, N,   N,  N),
1897 	PINGROUP(pk7,                    UARTD,      RSVD2,      GMI,          RSVD4,       0x323c, N,   N,  N),
1898 	PINGROUP(pi0,                    RSVD1,      RSVD2,      GMI,          RSVD4,       0x3240, N,   N,  N),
1899 	PINGROUP(pi1,                    RSVD1,      RSVD2,      GMI,          RSVD4,       0x3244, N,   N,  N),
1900 	PINGROUP(pi2,                    SDMMC2,     TRACE,      GMI,          RSVD4,       0x3248, N,   N,  N),
1901 	PINGROUP(pi4,                    SPI4,       TRACE,      GMI,          DISPLAYA,    0x324c, N,   N,  N),
1902 	PINGROUP(gen2_i2c_scl_pt5,       I2C2,       RSVD2,      GMI,          RSVD4,       0x3250, Y,   N,  N),
1903 	PINGROUP(gen2_i2c_sda_pt6,       I2C2,       RSVD2,      GMI,          RSVD4,       0x3254, Y,   N,  N),
1904 	PINGROUP(sdmmc4_clk_pcc4,        SDMMC4,     RSVD2,      GMI,          RSVD4,       0x3258, N,   Y,  N),
1905 	PINGROUP(sdmmc4_cmd_pt7,         SDMMC4,     RSVD2,      GMI,          RSVD4,       0x325c, N,   Y,  N),
1906 	PINGROUP(sdmmc4_dat0_paa0,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3260, N,   Y,  N),
1907 	PINGROUP(sdmmc4_dat1_paa1,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3264, N,   Y,  N),
1908 	PINGROUP(sdmmc4_dat2_paa2,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3268, N,   Y,  N),
1909 	PINGROUP(sdmmc4_dat3_paa3,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x326c, N,   Y,  N),
1910 	PINGROUP(sdmmc4_dat4_paa4,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3270, N,   Y,  N),
1911 	PINGROUP(sdmmc4_dat5_paa5,       SDMMC4,     SPI3,       RSVD3,        RSVD4,       0x3274, N,   Y,  N),
1912 	PINGROUP(sdmmc4_dat6_paa6,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3278, N,   Y,  N),
1913 	PINGROUP(sdmmc4_dat7_paa7,       SDMMC4,     RSVD2,      GMI,          RSVD4,       0x327c, N,   Y,  N),
1914 	PINGROUP(cam_mclk_pcc0,          VI,         VI_ALT1,    VI_ALT3,      SDMMC2,      0x3284, N,   N,  N),
1915 	PINGROUP(pcc1,                   I2S4,       RSVD2,      RSVD3,        SDMMC2,      0x3288, N,   N,  N),
1916 	PINGROUP(pbb0,                   VGP6,       VIMCLK2,    SDMMC2,       VIMCLK2_ALT, 0x328c, N,   N,  N),
1917 	PINGROUP(cam_i2c_scl_pbb1,       VGP1,       I2C3,       RSVD3,        SDMMC2,      0x3290, Y,   N,  N),
1918 	PINGROUP(cam_i2c_sda_pbb2,       VGP2,       I2C3,       RSVD3,        SDMMC2,      0x3294, Y,   N,  N),
1919 	PINGROUP(pbb3,                   VGP3,       DISPLAYA,   DISPLAYB,     SDMMC2,      0x3298, N,   N,  N),
1920 	PINGROUP(pbb4,                   VGP4,       DISPLAYA,   DISPLAYB,     SDMMC2,      0x329c, N,   N,  N),
1921 	PINGROUP(pbb5,                   VGP5,       DISPLAYA,   RSVD3,        SDMMC2,      0x32a0, N,   N,  N),
1922 	PINGROUP(pbb6,                   I2S4,       RSVD2,      DISPLAYB,     SDMMC2,      0x32a4, N,   N,  N),
1923 	PINGROUP(pbb7,                   I2S4,       RSVD2,      RSVD3,        SDMMC2,      0x32a8, N,   N,  N),
1924 	PINGROUP(pcc2,                   I2S4,       RSVD2,      SDMMC3,       SDMMC2,      0x32ac, N,   N,  N),
1925 	PINGROUP(jtag_rtck,              RTCK,       RSVD2,      RSVD3,        RSVD4,       0x32b0, N,   N,  N),
1926 	PINGROUP(pwr_i2c_scl_pz6,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       0x32b4, Y,   N,  N),
1927 	PINGROUP(pwr_i2c_sda_pz7,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       0x32b8, Y,   N,  N),
1928 	PINGROUP(kb_row0_pr0,            KBC,        RSVD2,      RSVD3,        RSVD4,       0x32bc, N,   N,  N),
1929 	PINGROUP(kb_row1_pr1,            KBC,        RSVD2,      RSVD3,        RSVD4,       0x32c0, N,   N,  N),
1930 	PINGROUP(kb_row2_pr2,            KBC,        RSVD2,      RSVD3,        RSVD4,       0x32c4, N,   N,  N),
1931 	PINGROUP(kb_row3_pr3,            KBC,        DISPLAYA,   SYS,          DISPLAYB,    0x32c8, N,   N,  N),
1932 	PINGROUP(kb_row4_pr4,            KBC,        DISPLAYA,   RSVD3,        DISPLAYB,    0x32cc, N,   N,  N),
1933 	PINGROUP(kb_row5_pr5,            KBC,        DISPLAYA,   RSVD3,        DISPLAYB,    0x32d0, N,   N,  N),
1934 	PINGROUP(kb_row6_pr6,            KBC,        DISPLAYA,   DISPLAYA_ALT, DISPLAYB,    0x32d4, N,   N,  N),
1935 	PINGROUP(kb_row7_pr7,            KBC,        RSVD2,      CLDVFS,       UARTA,       0x32d8, N,   N,  N),
1936 	PINGROUP(kb_row8_ps0,            KBC,        RSVD2,      CLDVFS,       UARTA,       0x32dc, N,   N,  N),
1937 	PINGROUP(kb_row9_ps1,            KBC,        RSVD2,      RSVD3,        UARTA,       0x32e0, N,   N,  N),
1938 	PINGROUP(kb_row10_ps2,           KBC,        RSVD2,      RSVD3,        UARTA,       0x32e4, N,   N,  N),
1939 	PINGROUP(kb_row11_ps3,           KBC,        RSVD2,      RSVD3,        IRDA,        0x32e8, N,   N,  N),
1940 	PINGROUP(kb_row12_ps4,           KBC,        RSVD2,      RSVD3,        IRDA,        0x32ec, N,   N,  N),
1941 	PINGROUP(kb_row13_ps5,           KBC,        RSVD2,      SPI2,         RSVD4,       0x32f0, N,   N,  N),
1942 	PINGROUP(kb_row14_ps6,           KBC,        RSVD2,      SPI2,         RSVD4,       0x32f4, N,   N,  N),
1943 	PINGROUP(kb_row15_ps7,           KBC,        SOC,        RSVD3,        RSVD4,       0x32f8, N,   N,  N),
1944 	PINGROUP(kb_col0_pq0,            KBC,        RSVD2,      SPI2,         RSVD4,       0x32fc, N,   N,  N),
1945 	PINGROUP(kb_col1_pq1,            KBC,        RSVD2,      SPI2,         RSVD4,       0x3300, N,   N,  N),
1946 	PINGROUP(kb_col2_pq2,            KBC,        RSVD2,      SPI2,         RSVD4,       0x3304, N,   N,  N),
1947 	PINGROUP(kb_col3_pq3,            KBC,        DISPLAYA,   PWM2,         UARTA,       0x3308, N,   N,  N),
1948 	PINGROUP(kb_col4_pq4,            KBC,        OWR,        SDMMC3,       UARTA,       0x330c, N,   N,  N),
1949 	PINGROUP(kb_col5_pq5,            KBC,        RSVD2,      SDMMC3,       RSVD4,       0x3310, N,   N,  N),
1950 	PINGROUP(kb_col6_pq6,            KBC,        RSVD2,      SPI2,         UARTD,       0x3314, N,   N,  N),
1951 	PINGROUP(kb_col7_pq7,            KBC,        RSVD2,      SPI2,         UARTD,       0x3318, N,   N,  N),
1952 	PINGROUP(clk_32k_out_pa0,        BLINK,      SOC,        RSVD3,        RSVD4,       0x331c, N,   N,  N),
1953 	PINGROUP(core_pwr_req,           PWRON,      RSVD2,      RSVD3,        RSVD4,       0x3324, N,   N,  N),
1954 	PINGROUP(cpu_pwr_req,            CPU,        RSVD2,      RSVD3,        RSVD4,       0x3328, N,   N,  N),
1955 	PINGROUP(pwr_int_n,              PMI,        RSVD2,      RSVD3,        RSVD4,       0x332c, N,   N,  N),
1956 	PINGROUP(clk_32k_in,             CLK,        RSVD2,      RSVD3,        RSVD4,       0x3330, N,   N,  N),
1957 	PINGROUP(owr,                    OWR,        RSVD2,      RSVD3,        RSVD4,       0x3334, N,   N,  Y),
1958 	PINGROUP(dap1_fs_pn0,            I2S0,       HDA,        GMI,          RSVD4,       0x3338, N,   N,  N),
1959 	PINGROUP(dap1_din_pn1,           I2S0,       HDA,        GMI,          RSVD4,       0x333c, N,   N,  N),
1960 	PINGROUP(dap1_dout_pn2,          I2S0,       HDA,        GMI,          SATA,        0x3340, N,   N,  N),
1961 	PINGROUP(dap1_sclk_pn3,          I2S0,       HDA,        GMI,          RSVD4,       0x3344, N,   N,  N),
1962 	PINGROUP(dap_mclk1_req_pee2,     DAP,        DAP1,       SATA,         RSVD4,       0x3348, N,   N,  N),
1963 	PINGROUP(dap_mclk1_pw4,          EXTPERIPH1, DAP2,       RSVD3,        RSVD4,       0x334c, N,   N,  N),
1964 	PINGROUP(spdif_in_pk6,           SPDIF,      RSVD2,      RSVD3,        I2C3,        0x3350, N,   N,  N),
1965 	PINGROUP(spdif_out_pk5,          SPDIF,      RSVD2,      RSVD3,        I2C3,        0x3354, N,   N,  N),
1966 	PINGROUP(dap2_fs_pa2,            I2S1,       HDA,        GMI,          RSVD4,       0x3358, N,   N,  N),
1967 	PINGROUP(dap2_din_pa4,           I2S1,       HDA,        GMI,          RSVD4,       0x335c, N,   N,  N),
1968 	PINGROUP(dap2_dout_pa5,          I2S1,       HDA,        GMI,          RSVD4,       0x3360, N,   N,  N),
1969 	PINGROUP(dap2_sclk_pa3,          I2S1,       HDA,        GMI,          RSVD4,       0x3364, N,   N,  N),
1970 	PINGROUP(dvfs_pwm_px0,           SPI6,       CLDVFS,     GMI,          RSVD4,       0x3368, N,   N,  N),
1971 	PINGROUP(gpio_x1_aud_px1,        SPI6,       RSVD2,      GMI,          RSVD4,       0x336c, N,   N,  N),
1972 	PINGROUP(gpio_x3_aud_px3,        SPI6,       SPI1,       GMI,          RSVD4,       0x3370, N,   N,  N),
1973 	PINGROUP(dvfs_clk_px2,           SPI6,       CLDVFS,     GMI,          RSVD4,       0x3374, N,   N,  N),
1974 	PINGROUP(gpio_x4_aud_px4,        GMI,        SPI1,       SPI2,         DAP2,        0x3378, N,   N,  N),
1975 	PINGROUP(gpio_x5_aud_px5,        GMI,        SPI1,       SPI2,         RSVD4,       0x337c, N,   N,  N),
1976 	PINGROUP(gpio_x6_aud_px6,        SPI6,       SPI1,       SPI2,         GMI,         0x3380, N,   N,  N),
1977 	PINGROUP(gpio_x7_aud_px7,        RSVD1,      SPI1,       SPI2,         RSVD4,       0x3384, N,   N,  N),
1978 	PINGROUP(sdmmc3_clk_pa6,         SDMMC3,     RSVD2,      RSVD3,        SPI3,        0x3390, N,   N,  N),
1979 	PINGROUP(sdmmc3_cmd_pa7,         SDMMC3,     PWM3,       UARTA,        SPI3,        0x3394, N,   N,  N),
1980 	PINGROUP(sdmmc3_dat0_pb7,        SDMMC3,     RSVD2,      RSVD3,        SPI3,        0x3398, N,   N,  N),
1981 	PINGROUP(sdmmc3_dat1_pb6,        SDMMC3,     PWM2,       UARTA,        SPI3,        0x339c, N,   N,  N),
1982 	PINGROUP(sdmmc3_dat2_pb5,        SDMMC3,     PWM1,       DISPLAYA,     SPI3,        0x33a0, N,   N,  N),
1983 	PINGROUP(sdmmc3_dat3_pb4,        SDMMC3,     PWM0,       DISPLAYB,     SPI3,        0x33a4, N,   N,  N),
1984 	PINGROUP(pex_l0_rst_n_pdd1,      PE0,        RSVD2,      RSVD3,        RSVD4,       0x33bc, N,   N,  N),
1985 	PINGROUP(pex_l0_clkreq_n_pdd2,   PE0,        RSVD2,      RSVD3,        RSVD4,       0x33c0, N,   N,  N),
1986 	PINGROUP(pex_wake_n_pdd3,        PE,         RSVD2,      RSVD3,        RSVD4,       0x33c4, N,   N,  N),
1987 	PINGROUP(pex_l1_rst_n_pdd5,      PE1,        RSVD2,      RSVD3,        RSVD4,       0x33cc, N,   N,  N),
1988 	PINGROUP(pex_l1_clkreq_n_pdd6,   PE1,        RSVD2,      RSVD3,        RSVD4,       0x33d0, N,   N,  N),
1989 	PINGROUP(hdmi_cec_pee3,          CEC,        RSVD2,      RSVD3,        RSVD4,       0x33e0, Y,   N,  N),
1990 	PINGROUP(sdmmc1_wp_n_pv3,        SDMMC1,     CLK12,      SPI4,         UARTA,       0x33e4, N,   N,  N),
1991 	PINGROUP(sdmmc3_cd_n_pv2,        SDMMC3,     OWR,        RSVD3,        RSVD4,       0x33e8, N,   N,  N),
1992 	PINGROUP(gpio_w2_aud_pw2,        SPI6,       RSVD2,      SPI2,         I2C1,        0x33ec, N,   N,  N),
1993 	PINGROUP(gpio_w3_aud_pw3,        SPI6,       SPI1,       SPI2,         I2C1,        0x33f0, N,   N,  N),
1994 	PINGROUP(usb_vbus_en0_pn4,       USB,        RSVD2,      RSVD3,        RSVD4,       0x33f4, Y,   N,  N),
1995 	PINGROUP(usb_vbus_en1_pn5,       USB,        RSVD2,      RSVD3,        RSVD4,       0x33f8, Y,   N,  N),
1996 	PINGROUP(sdmmc3_clk_lb_in_pee5,  SDMMC3,     RSVD2,      RSVD3,        RSVD4,       0x33fc, N,   N,  N),
1997 	PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3,     RSVD2,      RSVD3,        RSVD4,       0x3400, N,   N,  N),
1998 	PINGROUP(gmi_clk_lb,             SDMMC2,     RSVD2,      GMI,          RSVD4,       0x3404, N,   N,  N),
1999 	PINGROUP(reset_out_n,            RSVD1,      RSVD2,      RSVD3,        RESET_OUT_N, 0x3408, N,   N,  N),
2000 	PINGROUP(kb_row16_pt0,           KBC,        RSVD2,      RSVD3,        UARTC,       0x340c, N,   N,  N),
2001 	PINGROUP(kb_row17_pt1,           KBC,        RSVD2,      RSVD3,        UARTC,       0x3410, N,   N,  N),
2002 	PINGROUP(usb_vbus_en2_pff1,      USB,        RSVD2,      RSVD3,        RSVD4,       0x3414, Y,   N,  N),
2003 	PINGROUP(pff2,                   SATA,       RSVD2,      RSVD3,        RSVD4,       0x3418, Y,   N,  N),
2004 	PINGROUP(dp_hpd_pff0,            DP,         RSVD2,      RSVD3,        RSVD4,       0x3430, N,   N,  N),
2005 
2006 	/* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
2007 	DRV_PINGROUP(ao1,         0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2008 	DRV_PINGROUP(ao2,         0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2009 	DRV_PINGROUP(at1,         0x870,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
2010 	DRV_PINGROUP(at2,         0x874,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
2011 	DRV_PINGROUP(at3,         0x878,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
2012 	DRV_PINGROUP(at4,         0x87c,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
2013 	DRV_PINGROUP(at5,         0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
2014 	DRV_PINGROUP(cdev1,       0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2015 	DRV_PINGROUP(cdev2,       0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2016 	DRV_PINGROUP(dap1,        0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2017 	DRV_PINGROUP(dap2,        0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2018 	DRV_PINGROUP(dap3,        0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2019 	DRV_PINGROUP(dap4,        0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2020 	DRV_PINGROUP(dbg,         0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2021 	DRV_PINGROUP(sdio3,       0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
2022 	DRV_PINGROUP(spi,         0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2023 	DRV_PINGROUP(uaa,         0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2024 	DRV_PINGROUP(uab,         0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2025 	DRV_PINGROUP(uart2,       0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2026 	DRV_PINGROUP(uart3,       0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2027 	DRV_PINGROUP(sdio1,       0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
2028 	DRV_PINGROUP(ddc,         0x8fc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2029 	DRV_PINGROUP(gma,         0x900,  2,  3,  4,  14,  5,  20,  5,  28,  2,  30,  2,  Y),
2030 	DRV_PINGROUP(gme,         0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
2031 	DRV_PINGROUP(gmf,         0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
2032 	DRV_PINGROUP(gmg,         0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
2033 	DRV_PINGROUP(gmh,         0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
2034 	DRV_PINGROUP(owr,         0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2035 	DRV_PINGROUP(uda,         0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2036 	DRV_PINGROUP(gpv,         0x928,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2037 	DRV_PINGROUP(dev3,        0x92c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2038 	DRV_PINGROUP(cec,         0x938,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2039 	DRV_PINGROUP(at6,         0x994,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
2040 	DRV_PINGROUP(dap5,        0x998,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2041 	DRV_PINGROUP(usb_vbus_en, 0x99c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2042 	DRV_PINGROUP(ao3,         0x9a8,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
2043 	DRV_PINGROUP(ao0,         0x9b0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2044 	DRV_PINGROUP(hv0,         0x9b4,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
2045 	DRV_PINGROUP(sdio4,       0x9c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2046 	DRV_PINGROUP(ao4,         0x9c8,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
2047 
2048 	/*                     pg_name, r,     b, f0,  f1 */
2049 	MIPI_PAD_CTRL_PINGROUP(dsi_b,   0x820, 1, CSI, DSI_B),
2050 };
2051 
2052 static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
2053 	.ngpios = NUM_GPIOS,
2054 	.gpio_compatible = "nvidia,tegra30-gpio",
2055 	.pins = tegra124_pins,
2056 	.npins = ARRAY_SIZE(tegra124_pins),
2057 	.functions = tegra124_functions,
2058 	.nfunctions = ARRAY_SIZE(tegra124_functions),
2059 	.groups = tegra124_groups,
2060 	.ngroups = ARRAY_SIZE(tegra124_groups),
2061 	.hsm_in_mux = false,
2062 	.schmitt_in_mux = false,
2063 	.drvtype_in_mux = false,
2064 };
2065 
2066 static int tegra124_pinctrl_probe(struct platform_device *pdev)
2067 {
2068 	return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
2069 }
2070 
2071 static const struct of_device_id tegra124_pinctrl_of_match[] = {
2072 	{ .compatible = "nvidia,tegra124-pinmux", },
2073 	{ },
2074 };
2075 
2076 static struct platform_driver tegra124_pinctrl_driver = {
2077 	.driver = {
2078 		.name = "tegra124-pinctrl",
2079 		.of_match_table = tegra124_pinctrl_of_match,
2080 	},
2081 	.probe = tegra124_pinctrl_probe,
2082 };
2083 
2084 static int __init tegra124_pinctrl_init(void)
2085 {
2086 	return platform_driver_register(&tegra124_pinctrl_driver);
2087 }
2088 arch_initcall(tegra124_pinctrl_init);
2089