1 /* 2 * Pinctrl data for the NVIDIA Tegra114 pinmux 3 * 4 * Author: Pritesh Raithatha <praithatha@nvidia.com> 5 * 6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 */ 17 18 #include <linux/init.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 24 #include "pinctrl-tegra.h" 25 26 /* 27 * Most pins affected by the pinmux can also be GPIOs. Define these first. 28 * These must match how the GPIO driver names/numbers its pins. 29 */ 30 #define _GPIO(offset) (offset) 31 32 #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0) 33 #define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1) 34 #define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2) 35 #define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3) 36 #define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4) 37 #define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5) 38 #define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6) 39 #define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7) 40 #define TEGRA_PIN_GMI_A17_PB0 _GPIO(8) 41 #define TEGRA_PIN_GMI_A18_PB1 _GPIO(9) 42 #define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12) 43 #define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13) 44 #define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14) 45 #define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15) 46 #define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16) 47 #define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18) 48 #define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19) 49 #define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20) 50 #define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21) 51 #define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23) 52 #define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48) 53 #define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49) 54 #define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50) 55 #define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51) 56 #define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52) 57 #define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53) 58 #define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54) 59 #define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55) 60 #define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56) 61 #define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57) 62 #define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58) 63 #define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59) 64 #define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60) 65 #define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61) 66 #define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62) 67 #define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63) 68 #define TEGRA_PIN_GMI_WR_N_PI0 _GPIO(64) 69 #define TEGRA_PIN_GMI_OE_N_PI1 _GPIO(65) 70 #define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67) 71 #define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68) 72 #define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69) 73 #define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70) 74 #define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71) 75 #define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72) 76 #define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74) 77 #define TEGRA_PIN_GMI_DQS_P_PJ3 _GPIO(75) 78 #define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77) 79 #define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78) 80 #define TEGRA_PIN_GMI_A16_PJ7 _GPIO(79) 81 #define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80) 82 #define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81) 83 #define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82) 84 #define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83) 85 #define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84) 86 #define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85) 87 #define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86) 88 #define TEGRA_PIN_GMI_A19_PK7 _GPIO(87) 89 #define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104) 90 #define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105) 91 #define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106) 92 #define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107) 93 #define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108) 94 #define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109) 95 #define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111) 96 #define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112) 97 #define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113) 98 #define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114) 99 #define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115) 100 #define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116) 101 #define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117) 102 #define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118) 103 #define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119) 104 #define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120) 105 #define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121) 106 #define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122) 107 #define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123) 108 #define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124) 109 #define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125) 110 #define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126) 111 #define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127) 112 #define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128) 113 #define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129) 114 #define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130) 115 #define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131) 116 #define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132) 117 #define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133) 118 #define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134) 119 #define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135) 120 #define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136) 121 #define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137) 122 #define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138) 123 #define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139) 124 #define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140) 125 #define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141) 126 #define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142) 127 #define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143) 128 #define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144) 129 #define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145) 130 #define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146) 131 #define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157) 132 #define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158) 133 #define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159) 134 #define TEGRA_PIN_PU0 _GPIO(160) 135 #define TEGRA_PIN_PU1 _GPIO(161) 136 #define TEGRA_PIN_PU2 _GPIO(162) 137 #define TEGRA_PIN_PU3 _GPIO(163) 138 #define TEGRA_PIN_PU4 _GPIO(164) 139 #define TEGRA_PIN_PU5 _GPIO(165) 140 #define TEGRA_PIN_PU6 _GPIO(166) 141 #define TEGRA_PIN_PV0 _GPIO(168) 142 #define TEGRA_PIN_PV1 _GPIO(169) 143 #define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170) 144 #define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171) 145 #define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172) 146 #define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173) 147 #define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178) 148 #define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179) 149 #define TEGRA_PIN_CLK1_OUT_PW4 _GPIO(180) 150 #define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181) 151 #define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182) 152 #define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183) 153 #define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184) 154 #define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185) 155 #define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186) 156 #define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187) 157 #define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188) 158 #define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189) 159 #define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190) 160 #define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191) 161 #define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192) 162 #define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193) 163 #define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194) 164 #define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195) 165 #define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196) 166 #define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197) 167 #define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198) 168 #define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199) 169 #define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200) 170 #define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201) 171 #define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205) 172 #define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206) 173 #define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207) 174 #define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208) 175 #define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209) 176 #define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210) 177 #define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211) 178 #define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212) 179 #define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213) 180 #define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214) 181 #define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215) 182 #define TEGRA_PIN_PBB0 _GPIO(216) 183 #define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217) 184 #define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218) 185 #define TEGRA_PIN_PBB3 _GPIO(219) 186 #define TEGRA_PIN_PBB4 _GPIO(220) 187 #define TEGRA_PIN_PBB5 _GPIO(221) 188 #define TEGRA_PIN_PBB6 _GPIO(222) 189 #define TEGRA_PIN_PBB7 _GPIO(223) 190 #define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224) 191 #define TEGRA_PIN_PCC1 _GPIO(225) 192 #define TEGRA_PIN_PCC2 _GPIO(226) 193 #define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228) 194 #define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229) 195 #define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240) 196 #define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241) 197 #define TEGRA_PIN_CLK1_REQ_PEE2 _GPIO(242) 198 #define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243) 199 #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244) 200 #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245) 201 202 /* All non-GPIO pins follow */ 203 #define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1) 204 #define _PIN(offset) (NUM_GPIOS + (offset)) 205 206 /* Non-GPIO pins */ 207 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0) 208 #define TEGRA_PIN_CPU_PWR_REQ _PIN(1) 209 #define TEGRA_PIN_PWR_INT_N _PIN(2) 210 #define TEGRA_PIN_RESET_OUT_N _PIN(3) 211 #define TEGRA_PIN_OWR _PIN(4) 212 #define TEGRA_PIN_JTAG_RTCK _PIN(5) 213 #define TEGRA_PIN_CLK_32K_IN _PIN(6) 214 #define TEGRA_PIN_GMI_CLK_LB _PIN(7) 215 216 static const struct pinctrl_pin_desc tegra114_pins[] = { 217 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"), 218 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"), 219 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"), 220 PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"), 221 PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"), 222 PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"), 223 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"), 224 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"), 225 PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"), 226 PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"), 227 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"), 228 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"), 229 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"), 230 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"), 231 PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"), 232 PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"), 233 PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"), 234 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"), 235 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"), 236 PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"), 237 PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"), 238 PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"), 239 PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"), 240 PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"), 241 PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"), 242 PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"), 243 PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"), 244 PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"), 245 PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"), 246 PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"), 247 PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"), 248 PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"), 249 PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"), 250 PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"), 251 PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"), 252 PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"), 253 PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"), 254 PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"), 255 PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"), 256 PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"), 257 PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"), 258 PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"), 259 PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"), 260 PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"), 261 PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"), 262 PINCTRL_PIN(TEGRA_PIN_GMI_DQS_P_PJ3, "GMI_DQS_P PJ3"), 263 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"), 264 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"), 265 PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"), 266 PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"), 267 PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"), 268 PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"), 269 PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"), 270 PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"), 271 PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"), 272 PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"), 273 PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"), 274 PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"), 275 PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"), 276 PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"), 277 PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"), 278 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"), 279 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"), 280 PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"), 281 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"), 282 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"), 283 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"), 284 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"), 285 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"), 286 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"), 287 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"), 288 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"), 289 PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"), 290 PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"), 291 PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"), 292 PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"), 293 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"), 294 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"), 295 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"), 296 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"), 297 PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"), 298 PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"), 299 PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"), 300 PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"), 301 PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"), 302 PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"), 303 PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"), 304 PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"), 305 PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"), 306 PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"), 307 PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"), 308 PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"), 309 PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"), 310 PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"), 311 PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"), 312 PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"), 313 PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"), 314 PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"), 315 PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"), 316 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"), 317 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"), 318 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"), 319 PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"), 320 PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"), 321 PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"), 322 PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"), 323 PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"), 324 PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"), 325 PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"), 326 PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"), 327 PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"), 328 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"), 329 PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"), 330 PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"), 331 PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"), 332 PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"), 333 PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"), 334 PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"), 335 PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"), 336 PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"), 337 PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"), 338 PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"), 339 PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"), 340 PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"), 341 PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"), 342 PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"), 343 PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"), 344 PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"), 345 PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"), 346 PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"), 347 PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"), 348 PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"), 349 PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"), 350 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"), 351 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"), 352 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"), 353 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"), 354 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"), 355 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"), 356 PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"), 357 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"), 358 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"), 359 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"), 360 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"), 361 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"), 362 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"), 363 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"), 364 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"), 365 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"), 366 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"), 367 PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"), 368 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"), 369 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"), 370 PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"), 371 PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"), 372 PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"), 373 PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"), 374 PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"), 375 PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"), 376 PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"), 377 PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"), 378 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"), 379 PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"), 380 PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"), 381 PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"), 382 PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"), 383 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"), 384 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"), 385 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"), 386 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"), 387 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"), 388 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"), 389 PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"), 390 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"), 391 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"), 392 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), 393 PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"), 394 }; 395 396 static const unsigned clk_32k_out_pa0_pins[] = { 397 TEGRA_PIN_CLK_32K_OUT_PA0, 398 }; 399 400 static const unsigned uart3_cts_n_pa1_pins[] = { 401 TEGRA_PIN_UART3_CTS_N_PA1, 402 }; 403 404 static const unsigned dap2_fs_pa2_pins[] = { 405 TEGRA_PIN_DAP2_FS_PA2, 406 }; 407 408 static const unsigned dap2_sclk_pa3_pins[] = { 409 TEGRA_PIN_DAP2_SCLK_PA3, 410 }; 411 412 static const unsigned dap2_din_pa4_pins[] = { 413 TEGRA_PIN_DAP2_DIN_PA4, 414 }; 415 416 static const unsigned dap2_dout_pa5_pins[] = { 417 TEGRA_PIN_DAP2_DOUT_PA5, 418 }; 419 420 static const unsigned sdmmc3_clk_pa6_pins[] = { 421 TEGRA_PIN_SDMMC3_CLK_PA6, 422 }; 423 424 static const unsigned sdmmc3_cmd_pa7_pins[] = { 425 TEGRA_PIN_SDMMC3_CMD_PA7, 426 }; 427 428 static const unsigned gmi_a17_pb0_pins[] = { 429 TEGRA_PIN_GMI_A17_PB0, 430 }; 431 432 static const unsigned gmi_a18_pb1_pins[] = { 433 TEGRA_PIN_GMI_A18_PB1, 434 }; 435 436 static const unsigned sdmmc3_dat3_pb4_pins[] = { 437 TEGRA_PIN_SDMMC3_DAT3_PB4, 438 }; 439 440 static const unsigned sdmmc3_dat2_pb5_pins[] = { 441 TEGRA_PIN_SDMMC3_DAT2_PB5, 442 }; 443 444 static const unsigned sdmmc3_dat1_pb6_pins[] = { 445 TEGRA_PIN_SDMMC3_DAT1_PB6, 446 }; 447 448 static const unsigned sdmmc3_dat0_pb7_pins[] = { 449 TEGRA_PIN_SDMMC3_DAT0_PB7, 450 }; 451 452 static const unsigned uart3_rts_n_pc0_pins[] = { 453 TEGRA_PIN_UART3_RTS_N_PC0, 454 }; 455 456 static const unsigned uart2_txd_pc2_pins[] = { 457 TEGRA_PIN_UART2_TXD_PC2, 458 }; 459 460 static const unsigned uart2_rxd_pc3_pins[] = { 461 TEGRA_PIN_UART2_RXD_PC3, 462 }; 463 464 static const unsigned gen1_i2c_scl_pc4_pins[] = { 465 TEGRA_PIN_GEN1_I2C_SCL_PC4, 466 }; 467 468 static const unsigned gen1_i2c_sda_pc5_pins[] = { 469 TEGRA_PIN_GEN1_I2C_SDA_PC5, 470 }; 471 472 static const unsigned gmi_wp_n_pc7_pins[] = { 473 TEGRA_PIN_GMI_WP_N_PC7, 474 }; 475 476 static const unsigned gmi_ad0_pg0_pins[] = { 477 TEGRA_PIN_GMI_AD0_PG0, 478 }; 479 480 static const unsigned gmi_ad1_pg1_pins[] = { 481 TEGRA_PIN_GMI_AD1_PG1, 482 }; 483 484 static const unsigned gmi_ad2_pg2_pins[] = { 485 TEGRA_PIN_GMI_AD2_PG2, 486 }; 487 488 static const unsigned gmi_ad3_pg3_pins[] = { 489 TEGRA_PIN_GMI_AD3_PG3, 490 }; 491 492 static const unsigned gmi_ad4_pg4_pins[] = { 493 TEGRA_PIN_GMI_AD4_PG4, 494 }; 495 496 static const unsigned gmi_ad5_pg5_pins[] = { 497 TEGRA_PIN_GMI_AD5_PG5, 498 }; 499 500 static const unsigned gmi_ad6_pg6_pins[] = { 501 TEGRA_PIN_GMI_AD6_PG6, 502 }; 503 504 static const unsigned gmi_ad7_pg7_pins[] = { 505 TEGRA_PIN_GMI_AD7_PG7, 506 }; 507 508 static const unsigned gmi_ad8_ph0_pins[] = { 509 TEGRA_PIN_GMI_AD8_PH0, 510 }; 511 512 static const unsigned gmi_ad9_ph1_pins[] = { 513 TEGRA_PIN_GMI_AD9_PH1, 514 }; 515 516 static const unsigned gmi_ad10_ph2_pins[] = { 517 TEGRA_PIN_GMI_AD10_PH2, 518 }; 519 520 static const unsigned gmi_ad11_ph3_pins[] = { 521 TEGRA_PIN_GMI_AD11_PH3, 522 }; 523 524 static const unsigned gmi_ad12_ph4_pins[] = { 525 TEGRA_PIN_GMI_AD12_PH4, 526 }; 527 528 static const unsigned gmi_ad13_ph5_pins[] = { 529 TEGRA_PIN_GMI_AD13_PH5, 530 }; 531 532 static const unsigned gmi_ad14_ph6_pins[] = { 533 TEGRA_PIN_GMI_AD14_PH6, 534 }; 535 536 static const unsigned gmi_ad15_ph7_pins[] = { 537 TEGRA_PIN_GMI_AD15_PH7, 538 }; 539 540 static const unsigned gmi_wr_n_pi0_pins[] = { 541 TEGRA_PIN_GMI_WR_N_PI0, 542 }; 543 544 static const unsigned gmi_oe_n_pi1_pins[] = { 545 TEGRA_PIN_GMI_OE_N_PI1, 546 }; 547 548 static const unsigned gmi_cs6_n_pi3_pins[] = { 549 TEGRA_PIN_GMI_CS6_N_PI3, 550 }; 551 552 static const unsigned gmi_rst_n_pi4_pins[] = { 553 TEGRA_PIN_GMI_RST_N_PI4, 554 }; 555 556 static const unsigned gmi_iordy_pi5_pins[] = { 557 TEGRA_PIN_GMI_IORDY_PI5, 558 }; 559 560 static const unsigned gmi_cs7_n_pi6_pins[] = { 561 TEGRA_PIN_GMI_CS7_N_PI6, 562 }; 563 564 static const unsigned gmi_wait_pi7_pins[] = { 565 TEGRA_PIN_GMI_WAIT_PI7, 566 }; 567 568 static const unsigned gmi_cs0_n_pj0_pins[] = { 569 TEGRA_PIN_GMI_CS0_N_PJ0, 570 }; 571 572 static const unsigned gmi_cs1_n_pj2_pins[] = { 573 TEGRA_PIN_GMI_CS1_N_PJ2, 574 }; 575 576 static const unsigned gmi_dqs_p_pj3_pins[] = { 577 TEGRA_PIN_GMI_DQS_P_PJ3, 578 }; 579 580 static const unsigned uart2_cts_n_pj5_pins[] = { 581 TEGRA_PIN_UART2_CTS_N_PJ5, 582 }; 583 584 static const unsigned uart2_rts_n_pj6_pins[] = { 585 TEGRA_PIN_UART2_RTS_N_PJ6, 586 }; 587 588 static const unsigned gmi_a16_pj7_pins[] = { 589 TEGRA_PIN_GMI_A16_PJ7, 590 }; 591 592 static const unsigned gmi_adv_n_pk0_pins[] = { 593 TEGRA_PIN_GMI_ADV_N_PK0, 594 }; 595 596 static const unsigned gmi_clk_pk1_pins[] = { 597 TEGRA_PIN_GMI_CLK_PK1, 598 }; 599 600 static const unsigned gmi_cs4_n_pk2_pins[] = { 601 TEGRA_PIN_GMI_CS4_N_PK2, 602 }; 603 604 static const unsigned gmi_cs2_n_pk3_pins[] = { 605 TEGRA_PIN_GMI_CS2_N_PK3, 606 }; 607 608 static const unsigned gmi_cs3_n_pk4_pins[] = { 609 TEGRA_PIN_GMI_CS3_N_PK4, 610 }; 611 612 static const unsigned spdif_out_pk5_pins[] = { 613 TEGRA_PIN_SPDIF_OUT_PK5, 614 }; 615 616 static const unsigned spdif_in_pk6_pins[] = { 617 TEGRA_PIN_SPDIF_IN_PK6, 618 }; 619 620 static const unsigned gmi_a19_pk7_pins[] = { 621 TEGRA_PIN_GMI_A19_PK7, 622 }; 623 624 static const unsigned dap1_fs_pn0_pins[] = { 625 TEGRA_PIN_DAP1_FS_PN0, 626 }; 627 628 static const unsigned dap1_din_pn1_pins[] = { 629 TEGRA_PIN_DAP1_DIN_PN1, 630 }; 631 632 static const unsigned dap1_dout_pn2_pins[] = { 633 TEGRA_PIN_DAP1_DOUT_PN2, 634 }; 635 636 static const unsigned dap1_sclk_pn3_pins[] = { 637 TEGRA_PIN_DAP1_SCLK_PN3, 638 }; 639 640 static const unsigned usb_vbus_en0_pn4_pins[] = { 641 TEGRA_PIN_USB_VBUS_EN0_PN4, 642 }; 643 644 static const unsigned usb_vbus_en1_pn5_pins[] = { 645 TEGRA_PIN_USB_VBUS_EN1_PN5, 646 }; 647 648 static const unsigned hdmi_int_pn7_pins[] = { 649 TEGRA_PIN_HDMI_INT_PN7, 650 }; 651 652 static const unsigned ulpi_data7_po0_pins[] = { 653 TEGRA_PIN_ULPI_DATA7_PO0, 654 }; 655 656 static const unsigned ulpi_data0_po1_pins[] = { 657 TEGRA_PIN_ULPI_DATA0_PO1, 658 }; 659 660 static const unsigned ulpi_data1_po2_pins[] = { 661 TEGRA_PIN_ULPI_DATA1_PO2, 662 }; 663 664 static const unsigned ulpi_data2_po3_pins[] = { 665 TEGRA_PIN_ULPI_DATA2_PO3, 666 }; 667 668 static const unsigned ulpi_data3_po4_pins[] = { 669 TEGRA_PIN_ULPI_DATA3_PO4, 670 }; 671 672 static const unsigned ulpi_data4_po5_pins[] = { 673 TEGRA_PIN_ULPI_DATA4_PO5, 674 }; 675 676 static const unsigned ulpi_data5_po6_pins[] = { 677 TEGRA_PIN_ULPI_DATA5_PO6, 678 }; 679 680 static const unsigned ulpi_data6_po7_pins[] = { 681 TEGRA_PIN_ULPI_DATA6_PO7, 682 }; 683 684 static const unsigned dap3_fs_pp0_pins[] = { 685 TEGRA_PIN_DAP3_FS_PP0, 686 }; 687 688 static const unsigned dap3_din_pp1_pins[] = { 689 TEGRA_PIN_DAP3_DIN_PP1, 690 }; 691 692 static const unsigned dap3_dout_pp2_pins[] = { 693 TEGRA_PIN_DAP3_DOUT_PP2, 694 }; 695 696 static const unsigned dap3_sclk_pp3_pins[] = { 697 TEGRA_PIN_DAP3_SCLK_PP3, 698 }; 699 700 static const unsigned dap4_fs_pp4_pins[] = { 701 TEGRA_PIN_DAP4_FS_PP4, 702 }; 703 704 static const unsigned dap4_din_pp5_pins[] = { 705 TEGRA_PIN_DAP4_DIN_PP5, 706 }; 707 708 static const unsigned dap4_dout_pp6_pins[] = { 709 TEGRA_PIN_DAP4_DOUT_PP6, 710 }; 711 712 static const unsigned dap4_sclk_pp7_pins[] = { 713 TEGRA_PIN_DAP4_SCLK_PP7, 714 }; 715 716 static const unsigned kb_col0_pq0_pins[] = { 717 TEGRA_PIN_KB_COL0_PQ0, 718 }; 719 720 static const unsigned kb_col1_pq1_pins[] = { 721 TEGRA_PIN_KB_COL1_PQ1, 722 }; 723 724 static const unsigned kb_col2_pq2_pins[] = { 725 TEGRA_PIN_KB_COL2_PQ2, 726 }; 727 728 static const unsigned kb_col3_pq3_pins[] = { 729 TEGRA_PIN_KB_COL3_PQ3, 730 }; 731 732 static const unsigned kb_col4_pq4_pins[] = { 733 TEGRA_PIN_KB_COL4_PQ4, 734 }; 735 736 static const unsigned kb_col5_pq5_pins[] = { 737 TEGRA_PIN_KB_COL5_PQ5, 738 }; 739 740 static const unsigned kb_col6_pq6_pins[] = { 741 TEGRA_PIN_KB_COL6_PQ6, 742 }; 743 744 static const unsigned kb_col7_pq7_pins[] = { 745 TEGRA_PIN_KB_COL7_PQ7, 746 }; 747 748 static const unsigned kb_row0_pr0_pins[] = { 749 TEGRA_PIN_KB_ROW0_PR0, 750 }; 751 752 static const unsigned kb_row1_pr1_pins[] = { 753 TEGRA_PIN_KB_ROW1_PR1, 754 }; 755 756 static const unsigned kb_row2_pr2_pins[] = { 757 TEGRA_PIN_KB_ROW2_PR2, 758 }; 759 760 static const unsigned kb_row3_pr3_pins[] = { 761 TEGRA_PIN_KB_ROW3_PR3, 762 }; 763 764 static const unsigned kb_row4_pr4_pins[] = { 765 TEGRA_PIN_KB_ROW4_PR4, 766 }; 767 768 static const unsigned kb_row5_pr5_pins[] = { 769 TEGRA_PIN_KB_ROW5_PR5, 770 }; 771 772 static const unsigned kb_row6_pr6_pins[] = { 773 TEGRA_PIN_KB_ROW6_PR6, 774 }; 775 776 static const unsigned kb_row7_pr7_pins[] = { 777 TEGRA_PIN_KB_ROW7_PR7, 778 }; 779 780 static const unsigned kb_row8_ps0_pins[] = { 781 TEGRA_PIN_KB_ROW8_PS0, 782 }; 783 784 static const unsigned kb_row9_ps1_pins[] = { 785 TEGRA_PIN_KB_ROW9_PS1, 786 }; 787 788 static const unsigned kb_row10_ps2_pins[] = { 789 TEGRA_PIN_KB_ROW10_PS2, 790 }; 791 792 static const unsigned gen2_i2c_scl_pt5_pins[] = { 793 TEGRA_PIN_GEN2_I2C_SCL_PT5, 794 }; 795 796 static const unsigned gen2_i2c_sda_pt6_pins[] = { 797 TEGRA_PIN_GEN2_I2C_SDA_PT6, 798 }; 799 800 static const unsigned sdmmc4_cmd_pt7_pins[] = { 801 TEGRA_PIN_SDMMC4_CMD_PT7, 802 }; 803 804 static const unsigned pu0_pins[] = { 805 TEGRA_PIN_PU0, 806 }; 807 808 static const unsigned pu1_pins[] = { 809 TEGRA_PIN_PU1, 810 }; 811 812 static const unsigned pu2_pins[] = { 813 TEGRA_PIN_PU2, 814 }; 815 816 static const unsigned pu3_pins[] = { 817 TEGRA_PIN_PU3, 818 }; 819 820 static const unsigned pu4_pins[] = { 821 TEGRA_PIN_PU4, 822 }; 823 824 static const unsigned pu5_pins[] = { 825 TEGRA_PIN_PU5, 826 }; 827 828 static const unsigned pu6_pins[] = { 829 TEGRA_PIN_PU6, 830 }; 831 832 static const unsigned pv0_pins[] = { 833 TEGRA_PIN_PV0, 834 }; 835 836 static const unsigned pv1_pins[] = { 837 TEGRA_PIN_PV1, 838 }; 839 840 static const unsigned sdmmc3_cd_n_pv2_pins[] = { 841 TEGRA_PIN_SDMMC3_CD_N_PV2, 842 }; 843 844 static const unsigned sdmmc1_wp_n_pv3_pins[] = { 845 TEGRA_PIN_SDMMC1_WP_N_PV3, 846 }; 847 848 static const unsigned ddc_scl_pv4_pins[] = { 849 TEGRA_PIN_DDC_SCL_PV4, 850 }; 851 852 static const unsigned ddc_sda_pv5_pins[] = { 853 TEGRA_PIN_DDC_SDA_PV5, 854 }; 855 856 static const unsigned gpio_w2_aud_pw2_pins[] = { 857 TEGRA_PIN_GPIO_W2_AUD_PW2, 858 }; 859 860 static const unsigned gpio_w3_aud_pw3_pins[] = { 861 TEGRA_PIN_GPIO_W3_AUD_PW3, 862 }; 863 864 static const unsigned clk1_out_pw4_pins[] = { 865 TEGRA_PIN_CLK1_OUT_PW4, 866 }; 867 868 static const unsigned clk2_out_pw5_pins[] = { 869 TEGRA_PIN_CLK2_OUT_PW5, 870 }; 871 872 static const unsigned uart3_txd_pw6_pins[] = { 873 TEGRA_PIN_UART3_TXD_PW6, 874 }; 875 876 static const unsigned uart3_rxd_pw7_pins[] = { 877 TEGRA_PIN_UART3_RXD_PW7, 878 }; 879 880 static const unsigned dvfs_pwm_px0_pins[] = { 881 TEGRA_PIN_DVFS_PWM_PX0, 882 }; 883 884 static const unsigned gpio_x1_aud_px1_pins[] = { 885 TEGRA_PIN_GPIO_X1_AUD_PX1, 886 }; 887 888 static const unsigned dvfs_clk_px2_pins[] = { 889 TEGRA_PIN_DVFS_CLK_PX2, 890 }; 891 892 static const unsigned gpio_x3_aud_px3_pins[] = { 893 TEGRA_PIN_GPIO_X3_AUD_PX3, 894 }; 895 896 static const unsigned gpio_x4_aud_px4_pins[] = { 897 TEGRA_PIN_GPIO_X4_AUD_PX4, 898 }; 899 900 static const unsigned gpio_x5_aud_px5_pins[] = { 901 TEGRA_PIN_GPIO_X5_AUD_PX5, 902 }; 903 904 static const unsigned gpio_x6_aud_px6_pins[] = { 905 TEGRA_PIN_GPIO_X6_AUD_PX6, 906 }; 907 908 static const unsigned gpio_x7_aud_px7_pins[] = { 909 TEGRA_PIN_GPIO_X7_AUD_PX7, 910 }; 911 912 static const unsigned ulpi_clk_py0_pins[] = { 913 TEGRA_PIN_ULPI_CLK_PY0, 914 }; 915 916 static const unsigned ulpi_dir_py1_pins[] = { 917 TEGRA_PIN_ULPI_DIR_PY1, 918 }; 919 920 static const unsigned ulpi_nxt_py2_pins[] = { 921 TEGRA_PIN_ULPI_NXT_PY2, 922 }; 923 924 static const unsigned ulpi_stp_py3_pins[] = { 925 TEGRA_PIN_ULPI_STP_PY3, 926 }; 927 928 static const unsigned sdmmc1_dat3_py4_pins[] = { 929 TEGRA_PIN_SDMMC1_DAT3_PY4, 930 }; 931 932 static const unsigned sdmmc1_dat2_py5_pins[] = { 933 TEGRA_PIN_SDMMC1_DAT2_PY5, 934 }; 935 936 static const unsigned sdmmc1_dat1_py6_pins[] = { 937 TEGRA_PIN_SDMMC1_DAT1_PY6, 938 }; 939 940 static const unsigned sdmmc1_dat0_py7_pins[] = { 941 TEGRA_PIN_SDMMC1_DAT0_PY7, 942 }; 943 944 static const unsigned sdmmc1_clk_pz0_pins[] = { 945 TEGRA_PIN_SDMMC1_CLK_PZ0, 946 }; 947 948 static const unsigned sdmmc1_cmd_pz1_pins[] = { 949 TEGRA_PIN_SDMMC1_CMD_PZ1, 950 }; 951 952 static const unsigned sys_clk_req_pz5_pins[] = { 953 TEGRA_PIN_SYS_CLK_REQ_PZ5, 954 }; 955 956 static const unsigned pwr_i2c_scl_pz6_pins[] = { 957 TEGRA_PIN_PWR_I2C_SCL_PZ6, 958 }; 959 960 static const unsigned pwr_i2c_sda_pz7_pins[] = { 961 TEGRA_PIN_PWR_I2C_SDA_PZ7, 962 }; 963 964 static const unsigned sdmmc4_dat0_paa0_pins[] = { 965 TEGRA_PIN_SDMMC4_DAT0_PAA0, 966 }; 967 968 static const unsigned sdmmc4_dat1_paa1_pins[] = { 969 TEGRA_PIN_SDMMC4_DAT1_PAA1, 970 }; 971 972 static const unsigned sdmmc4_dat2_paa2_pins[] = { 973 TEGRA_PIN_SDMMC4_DAT2_PAA2, 974 }; 975 976 static const unsigned sdmmc4_dat3_paa3_pins[] = { 977 TEGRA_PIN_SDMMC4_DAT3_PAA3, 978 }; 979 980 static const unsigned sdmmc4_dat4_paa4_pins[] = { 981 TEGRA_PIN_SDMMC4_DAT4_PAA4, 982 }; 983 984 static const unsigned sdmmc4_dat5_paa5_pins[] = { 985 TEGRA_PIN_SDMMC4_DAT5_PAA5, 986 }; 987 988 static const unsigned sdmmc4_dat6_paa6_pins[] = { 989 TEGRA_PIN_SDMMC4_DAT6_PAA6, 990 }; 991 992 static const unsigned sdmmc4_dat7_paa7_pins[] = { 993 TEGRA_PIN_SDMMC4_DAT7_PAA7, 994 }; 995 996 static const unsigned pbb0_pins[] = { 997 TEGRA_PIN_PBB0, 998 }; 999 1000 static const unsigned cam_i2c_scl_pbb1_pins[] = { 1001 TEGRA_PIN_CAM_I2C_SCL_PBB1, 1002 }; 1003 1004 static const unsigned cam_i2c_sda_pbb2_pins[] = { 1005 TEGRA_PIN_CAM_I2C_SDA_PBB2, 1006 }; 1007 1008 static const unsigned pbb3_pins[] = { 1009 TEGRA_PIN_PBB3, 1010 }; 1011 1012 static const unsigned pbb4_pins[] = { 1013 TEGRA_PIN_PBB4, 1014 }; 1015 1016 static const unsigned pbb5_pins[] = { 1017 TEGRA_PIN_PBB5, 1018 }; 1019 1020 static const unsigned pbb6_pins[] = { 1021 TEGRA_PIN_PBB6, 1022 }; 1023 1024 static const unsigned pbb7_pins[] = { 1025 TEGRA_PIN_PBB7, 1026 }; 1027 1028 static const unsigned cam_mclk_pcc0_pins[] = { 1029 TEGRA_PIN_CAM_MCLK_PCC0, 1030 }; 1031 1032 static const unsigned pcc1_pins[] = { 1033 TEGRA_PIN_PCC1, 1034 }; 1035 1036 static const unsigned pcc2_pins[] = { 1037 TEGRA_PIN_PCC2, 1038 }; 1039 1040 static const unsigned sdmmc4_clk_pcc4_pins[] = { 1041 TEGRA_PIN_SDMMC4_CLK_PCC4, 1042 }; 1043 1044 static const unsigned clk2_req_pcc5_pins[] = { 1045 TEGRA_PIN_CLK2_REQ_PCC5, 1046 }; 1047 1048 static const unsigned clk3_out_pee0_pins[] = { 1049 TEGRA_PIN_CLK3_OUT_PEE0, 1050 }; 1051 1052 static const unsigned clk3_req_pee1_pins[] = { 1053 TEGRA_PIN_CLK3_REQ_PEE1, 1054 }; 1055 1056 static const unsigned clk1_req_pee2_pins[] = { 1057 TEGRA_PIN_CLK1_REQ_PEE2, 1058 }; 1059 1060 static const unsigned hdmi_cec_pee3_pins[] = { 1061 TEGRA_PIN_HDMI_CEC_PEE3, 1062 }; 1063 1064 static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = { 1065 TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, 1066 }; 1067 1068 static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = { 1069 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, 1070 }; 1071 1072 static const unsigned core_pwr_req_pins[] = { 1073 TEGRA_PIN_CORE_PWR_REQ, 1074 }; 1075 1076 static const unsigned cpu_pwr_req_pins[] = { 1077 TEGRA_PIN_CPU_PWR_REQ, 1078 }; 1079 1080 static const unsigned pwr_int_n_pins[] = { 1081 TEGRA_PIN_PWR_INT_N, 1082 }; 1083 1084 static const unsigned reset_out_n_pins[] = { 1085 TEGRA_PIN_RESET_OUT_N, 1086 }; 1087 1088 static const unsigned owr_pins[] = { 1089 TEGRA_PIN_OWR, 1090 }; 1091 1092 static const unsigned jtag_rtck_pins[] = { 1093 TEGRA_PIN_JTAG_RTCK, 1094 }; 1095 1096 static const unsigned clk_32k_in_pins[] = { 1097 TEGRA_PIN_CLK_32K_IN, 1098 }; 1099 1100 static const unsigned gmi_clk_lb_pins[] = { 1101 TEGRA_PIN_GMI_CLK_LB, 1102 }; 1103 1104 static const unsigned drive_ao1_pins[] = { 1105 TEGRA_PIN_KB_ROW0_PR0, 1106 TEGRA_PIN_KB_ROW1_PR1, 1107 TEGRA_PIN_KB_ROW2_PR2, 1108 TEGRA_PIN_KB_ROW3_PR3, 1109 TEGRA_PIN_KB_ROW4_PR4, 1110 TEGRA_PIN_KB_ROW5_PR5, 1111 TEGRA_PIN_KB_ROW6_PR6, 1112 TEGRA_PIN_KB_ROW7_PR7, 1113 TEGRA_PIN_PWR_I2C_SCL_PZ6, 1114 TEGRA_PIN_PWR_I2C_SDA_PZ7, 1115 }; 1116 1117 static const unsigned drive_ao2_pins[] = { 1118 TEGRA_PIN_CLK_32K_OUT_PA0, 1119 TEGRA_PIN_KB_COL0_PQ0, 1120 TEGRA_PIN_KB_COL1_PQ1, 1121 TEGRA_PIN_KB_COL2_PQ2, 1122 TEGRA_PIN_KB_COL3_PQ3, 1123 TEGRA_PIN_KB_COL4_PQ4, 1124 TEGRA_PIN_KB_COL5_PQ5, 1125 TEGRA_PIN_KB_COL6_PQ6, 1126 TEGRA_PIN_KB_COL7_PQ7, 1127 TEGRA_PIN_KB_ROW8_PS0, 1128 TEGRA_PIN_KB_ROW9_PS1, 1129 TEGRA_PIN_KB_ROW10_PS2, 1130 TEGRA_PIN_SYS_CLK_REQ_PZ5, 1131 TEGRA_PIN_CORE_PWR_REQ, 1132 TEGRA_PIN_CPU_PWR_REQ, 1133 TEGRA_PIN_RESET_OUT_N, 1134 }; 1135 1136 static const unsigned drive_at1_pins[] = { 1137 TEGRA_PIN_GMI_AD8_PH0, 1138 TEGRA_PIN_GMI_AD9_PH1, 1139 TEGRA_PIN_GMI_AD10_PH2, 1140 TEGRA_PIN_GMI_AD11_PH3, 1141 TEGRA_PIN_GMI_AD12_PH4, 1142 TEGRA_PIN_GMI_AD13_PH5, 1143 TEGRA_PIN_GMI_AD14_PH6, 1144 TEGRA_PIN_GMI_AD15_PH7, 1145 TEGRA_PIN_GMI_IORDY_PI5, 1146 TEGRA_PIN_GMI_CS7_N_PI6, 1147 }; 1148 1149 static const unsigned drive_at2_pins[] = { 1150 TEGRA_PIN_GMI_AD0_PG0, 1151 TEGRA_PIN_GMI_AD1_PG1, 1152 TEGRA_PIN_GMI_AD2_PG2, 1153 TEGRA_PIN_GMI_AD3_PG3, 1154 TEGRA_PIN_GMI_AD4_PG4, 1155 TEGRA_PIN_GMI_AD5_PG5, 1156 TEGRA_PIN_GMI_AD6_PG6, 1157 TEGRA_PIN_GMI_AD7_PG7, 1158 TEGRA_PIN_GMI_WR_N_PI0, 1159 TEGRA_PIN_GMI_OE_N_PI1, 1160 TEGRA_PIN_GMI_CS6_N_PI3, 1161 TEGRA_PIN_GMI_RST_N_PI4, 1162 TEGRA_PIN_GMI_WAIT_PI7, 1163 TEGRA_PIN_GMI_DQS_P_PJ3, 1164 TEGRA_PIN_GMI_ADV_N_PK0, 1165 TEGRA_PIN_GMI_CLK_PK1, 1166 TEGRA_PIN_GMI_CS4_N_PK2, 1167 TEGRA_PIN_GMI_CS2_N_PK3, 1168 TEGRA_PIN_GMI_CS3_N_PK4, 1169 }; 1170 1171 static const unsigned drive_at3_pins[] = { 1172 TEGRA_PIN_GMI_WP_N_PC7, 1173 TEGRA_PIN_GMI_CS0_N_PJ0, 1174 }; 1175 1176 static const unsigned drive_at4_pins[] = { 1177 TEGRA_PIN_GMI_A17_PB0, 1178 TEGRA_PIN_GMI_A18_PB1, 1179 TEGRA_PIN_GMI_CS1_N_PJ2, 1180 TEGRA_PIN_GMI_A16_PJ7, 1181 TEGRA_PIN_GMI_A19_PK7, 1182 }; 1183 1184 static const unsigned drive_at5_pins[] = { 1185 TEGRA_PIN_GEN2_I2C_SCL_PT5, 1186 TEGRA_PIN_GEN2_I2C_SDA_PT6, 1187 }; 1188 1189 static const unsigned drive_cdev1_pins[] = { 1190 TEGRA_PIN_CLK1_OUT_PW4, 1191 TEGRA_PIN_CLK1_REQ_PEE2, 1192 }; 1193 1194 static const unsigned drive_cdev2_pins[] = { 1195 TEGRA_PIN_CLK2_OUT_PW5, 1196 TEGRA_PIN_CLK2_REQ_PCC5, 1197 TEGRA_PIN_SDMMC1_WP_N_PV3, 1198 }; 1199 1200 static const unsigned drive_dap1_pins[] = { 1201 TEGRA_PIN_DAP1_FS_PN0, 1202 TEGRA_PIN_DAP1_DIN_PN1, 1203 TEGRA_PIN_DAP1_DOUT_PN2, 1204 TEGRA_PIN_DAP1_SCLK_PN3, 1205 }; 1206 1207 static const unsigned drive_dap2_pins[] = { 1208 TEGRA_PIN_DAP2_FS_PA2, 1209 TEGRA_PIN_DAP2_SCLK_PA3, 1210 TEGRA_PIN_DAP2_DIN_PA4, 1211 TEGRA_PIN_DAP2_DOUT_PA5, 1212 }; 1213 1214 static const unsigned drive_dap3_pins[] = { 1215 TEGRA_PIN_DAP3_FS_PP0, 1216 TEGRA_PIN_DAP3_DIN_PP1, 1217 TEGRA_PIN_DAP3_DOUT_PP2, 1218 TEGRA_PIN_DAP3_SCLK_PP3, 1219 }; 1220 1221 static const unsigned drive_dap4_pins[] = { 1222 TEGRA_PIN_DAP4_FS_PP4, 1223 TEGRA_PIN_DAP4_DIN_PP5, 1224 TEGRA_PIN_DAP4_DOUT_PP6, 1225 TEGRA_PIN_DAP4_SCLK_PP7, 1226 }; 1227 1228 static const unsigned drive_dbg_pins[] = { 1229 TEGRA_PIN_GEN1_I2C_SCL_PC4, 1230 TEGRA_PIN_GEN1_I2C_SDA_PC5, 1231 TEGRA_PIN_PU0, 1232 TEGRA_PIN_PU1, 1233 TEGRA_PIN_PU2, 1234 TEGRA_PIN_PU3, 1235 TEGRA_PIN_PU4, 1236 TEGRA_PIN_PU5, 1237 TEGRA_PIN_PU6, 1238 }; 1239 1240 static const unsigned drive_sdio3_pins[] = { 1241 TEGRA_PIN_SDMMC3_CLK_PA6, 1242 TEGRA_PIN_SDMMC3_CMD_PA7, 1243 TEGRA_PIN_SDMMC3_DAT3_PB4, 1244 TEGRA_PIN_SDMMC3_DAT2_PB5, 1245 TEGRA_PIN_SDMMC3_DAT1_PB6, 1246 TEGRA_PIN_SDMMC3_DAT0_PB7, 1247 TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, 1248 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, 1249 }; 1250 1251 static const unsigned drive_spi_pins[] = { 1252 TEGRA_PIN_DVFS_PWM_PX0, 1253 TEGRA_PIN_GPIO_X1_AUD_PX1, 1254 TEGRA_PIN_DVFS_CLK_PX2, 1255 TEGRA_PIN_GPIO_X3_AUD_PX3, 1256 TEGRA_PIN_GPIO_X4_AUD_PX4, 1257 TEGRA_PIN_GPIO_X5_AUD_PX5, 1258 TEGRA_PIN_GPIO_X6_AUD_PX6, 1259 TEGRA_PIN_GPIO_X7_AUD_PX7, 1260 TEGRA_PIN_GPIO_W2_AUD_PW2, 1261 TEGRA_PIN_GPIO_W3_AUD_PW3, 1262 }; 1263 1264 static const unsigned drive_uaa_pins[] = { 1265 TEGRA_PIN_ULPI_DATA0_PO1, 1266 TEGRA_PIN_ULPI_DATA1_PO2, 1267 TEGRA_PIN_ULPI_DATA2_PO3, 1268 TEGRA_PIN_ULPI_DATA3_PO4, 1269 }; 1270 1271 static const unsigned drive_uab_pins[] = { 1272 TEGRA_PIN_ULPI_DATA7_PO0, 1273 TEGRA_PIN_ULPI_DATA4_PO5, 1274 TEGRA_PIN_ULPI_DATA5_PO6, 1275 TEGRA_PIN_ULPI_DATA6_PO7, 1276 TEGRA_PIN_PV0, 1277 TEGRA_PIN_PV1, 1278 }; 1279 1280 static const unsigned drive_uart2_pins[] = { 1281 TEGRA_PIN_UART2_TXD_PC2, 1282 TEGRA_PIN_UART2_RXD_PC3, 1283 TEGRA_PIN_UART2_CTS_N_PJ5, 1284 TEGRA_PIN_UART2_RTS_N_PJ6, 1285 }; 1286 1287 static const unsigned drive_uart3_pins[] = { 1288 TEGRA_PIN_UART3_CTS_N_PA1, 1289 TEGRA_PIN_UART3_RTS_N_PC0, 1290 TEGRA_PIN_UART3_TXD_PW6, 1291 TEGRA_PIN_UART3_RXD_PW7, 1292 }; 1293 1294 static const unsigned drive_sdio1_pins[] = { 1295 TEGRA_PIN_SDMMC1_DAT3_PY4, 1296 TEGRA_PIN_SDMMC1_DAT2_PY5, 1297 TEGRA_PIN_SDMMC1_DAT1_PY6, 1298 TEGRA_PIN_SDMMC1_DAT0_PY7, 1299 TEGRA_PIN_SDMMC1_CLK_PZ0, 1300 TEGRA_PIN_SDMMC1_CMD_PZ1, 1301 }; 1302 1303 static const unsigned drive_ddc_pins[] = { 1304 TEGRA_PIN_DDC_SCL_PV4, 1305 TEGRA_PIN_DDC_SDA_PV5, 1306 }; 1307 1308 static const unsigned drive_gma_pins[] = { 1309 TEGRA_PIN_SDMMC4_CLK_PCC4, 1310 TEGRA_PIN_SDMMC4_CMD_PT7, 1311 TEGRA_PIN_SDMMC4_DAT0_PAA0, 1312 TEGRA_PIN_SDMMC4_DAT1_PAA1, 1313 TEGRA_PIN_SDMMC4_DAT2_PAA2, 1314 TEGRA_PIN_SDMMC4_DAT3_PAA3, 1315 TEGRA_PIN_SDMMC4_DAT4_PAA4, 1316 TEGRA_PIN_SDMMC4_DAT5_PAA5, 1317 TEGRA_PIN_SDMMC4_DAT6_PAA6, 1318 TEGRA_PIN_SDMMC4_DAT7_PAA7, 1319 }; 1320 1321 static const unsigned drive_gme_pins[] = { 1322 TEGRA_PIN_PBB0, 1323 TEGRA_PIN_CAM_I2C_SCL_PBB1, 1324 TEGRA_PIN_CAM_I2C_SDA_PBB2, 1325 TEGRA_PIN_PBB3, 1326 TEGRA_PIN_PCC2, 1327 }; 1328 1329 static const unsigned drive_gmf_pins[] = { 1330 TEGRA_PIN_PBB4, 1331 TEGRA_PIN_PBB5, 1332 TEGRA_PIN_PBB6, 1333 TEGRA_PIN_PBB7, 1334 }; 1335 1336 static const unsigned drive_gmg_pins[] = { 1337 TEGRA_PIN_CAM_MCLK_PCC0, 1338 }; 1339 1340 static const unsigned drive_gmh_pins[] = { 1341 TEGRA_PIN_PCC1, 1342 }; 1343 1344 static const unsigned drive_owr_pins[] = { 1345 TEGRA_PIN_SDMMC3_CD_N_PV2, 1346 }; 1347 1348 static const unsigned drive_uda_pins[] = { 1349 TEGRA_PIN_ULPI_CLK_PY0, 1350 TEGRA_PIN_ULPI_DIR_PY1, 1351 TEGRA_PIN_ULPI_NXT_PY2, 1352 TEGRA_PIN_ULPI_STP_PY3, 1353 }; 1354 1355 static const unsigned drive_dev3_pins[] = { 1356 }; 1357 1358 static const unsigned drive_cec_pins[] = { 1359 }; 1360 1361 static const unsigned drive_at6_pins[] = { 1362 }; 1363 1364 static const unsigned drive_dap5_pins[] = { 1365 }; 1366 1367 static const unsigned drive_usb_vbus_en_pins[] = { 1368 }; 1369 1370 static const unsigned drive_ao3_pins[] = { 1371 }; 1372 1373 static const unsigned drive_hv0_pins[] = { 1374 }; 1375 1376 static const unsigned drive_sdio4_pins[] = { 1377 }; 1378 1379 static const unsigned drive_ao0_pins[] = { 1380 }; 1381 1382 enum tegra_mux { 1383 TEGRA_MUX_BLINK, 1384 TEGRA_MUX_CEC, 1385 TEGRA_MUX_CLDVFS, 1386 TEGRA_MUX_CLK, 1387 TEGRA_MUX_CLK12, 1388 TEGRA_MUX_CPU, 1389 TEGRA_MUX_DAP, 1390 TEGRA_MUX_DAP1, 1391 TEGRA_MUX_DAP2, 1392 TEGRA_MUX_DEV3, 1393 TEGRA_MUX_DISPLAYA, 1394 TEGRA_MUX_DISPLAYA_ALT, 1395 TEGRA_MUX_DISPLAYB, 1396 TEGRA_MUX_DTV, 1397 TEGRA_MUX_EMC_DLL, 1398 TEGRA_MUX_EXTPERIPH1, 1399 TEGRA_MUX_EXTPERIPH2, 1400 TEGRA_MUX_EXTPERIPH3, 1401 TEGRA_MUX_GMI, 1402 TEGRA_MUX_GMI_ALT, 1403 TEGRA_MUX_HDA, 1404 TEGRA_MUX_HSI, 1405 TEGRA_MUX_I2C1, 1406 TEGRA_MUX_I2C2, 1407 TEGRA_MUX_I2C3, 1408 TEGRA_MUX_I2C4, 1409 TEGRA_MUX_I2CPWR, 1410 TEGRA_MUX_I2S0, 1411 TEGRA_MUX_I2S1, 1412 TEGRA_MUX_I2S2, 1413 TEGRA_MUX_I2S3, 1414 TEGRA_MUX_I2S4, 1415 TEGRA_MUX_IRDA, 1416 TEGRA_MUX_KBC, 1417 TEGRA_MUX_NAND, 1418 TEGRA_MUX_NAND_ALT, 1419 TEGRA_MUX_OWR, 1420 TEGRA_MUX_PMI, 1421 TEGRA_MUX_PWM0, 1422 TEGRA_MUX_PWM1, 1423 TEGRA_MUX_PWM2, 1424 TEGRA_MUX_PWM3, 1425 TEGRA_MUX_PWRON, 1426 TEGRA_MUX_RESET_OUT_N, 1427 TEGRA_MUX_RSVD1, 1428 TEGRA_MUX_RSVD2, 1429 TEGRA_MUX_RSVD3, 1430 TEGRA_MUX_RSVD4, 1431 TEGRA_MUX_RTCK, 1432 TEGRA_MUX_SDMMC1, 1433 TEGRA_MUX_SDMMC2, 1434 TEGRA_MUX_SDMMC3, 1435 TEGRA_MUX_SDMMC4, 1436 TEGRA_MUX_SOC, 1437 TEGRA_MUX_SPDIF, 1438 TEGRA_MUX_SPI1, 1439 TEGRA_MUX_SPI2, 1440 TEGRA_MUX_SPI3, 1441 TEGRA_MUX_SPI4, 1442 TEGRA_MUX_SPI5, 1443 TEGRA_MUX_SPI6, 1444 TEGRA_MUX_SYSCLK, 1445 TEGRA_MUX_TRACE, 1446 TEGRA_MUX_UARTA, 1447 TEGRA_MUX_UARTB, 1448 TEGRA_MUX_UARTC, 1449 TEGRA_MUX_UARTD, 1450 TEGRA_MUX_ULPI, 1451 TEGRA_MUX_USB, 1452 TEGRA_MUX_VGP1, 1453 TEGRA_MUX_VGP2, 1454 TEGRA_MUX_VGP3, 1455 TEGRA_MUX_VGP4, 1456 TEGRA_MUX_VGP5, 1457 TEGRA_MUX_VGP6, 1458 TEGRA_MUX_VI, 1459 TEGRA_MUX_VI_ALT1, 1460 TEGRA_MUX_VI_ALT3, 1461 }; 1462 1463 #define FUNCTION(fname) \ 1464 { \ 1465 .name = #fname, \ 1466 } 1467 1468 static struct tegra_function tegra114_functions[] = { 1469 FUNCTION(blink), 1470 FUNCTION(cec), 1471 FUNCTION(cldvfs), 1472 FUNCTION(clk), 1473 FUNCTION(clk12), 1474 FUNCTION(cpu), 1475 FUNCTION(dap), 1476 FUNCTION(dap1), 1477 FUNCTION(dap2), 1478 FUNCTION(dev3), 1479 FUNCTION(displaya), 1480 FUNCTION(displaya_alt), 1481 FUNCTION(displayb), 1482 FUNCTION(dtv), 1483 FUNCTION(emc_dll), 1484 FUNCTION(extperiph1), 1485 FUNCTION(extperiph2), 1486 FUNCTION(extperiph3), 1487 FUNCTION(gmi), 1488 FUNCTION(gmi_alt), 1489 FUNCTION(hda), 1490 FUNCTION(hsi), 1491 FUNCTION(i2c1), 1492 FUNCTION(i2c2), 1493 FUNCTION(i2c3), 1494 FUNCTION(i2c4), 1495 FUNCTION(i2cpwr), 1496 FUNCTION(i2s0), 1497 FUNCTION(i2s1), 1498 FUNCTION(i2s2), 1499 FUNCTION(i2s3), 1500 FUNCTION(i2s4), 1501 FUNCTION(irda), 1502 FUNCTION(kbc), 1503 FUNCTION(nand), 1504 FUNCTION(nand_alt), 1505 FUNCTION(owr), 1506 FUNCTION(pmi), 1507 FUNCTION(pwm0), 1508 FUNCTION(pwm1), 1509 FUNCTION(pwm2), 1510 FUNCTION(pwm3), 1511 FUNCTION(pwron), 1512 FUNCTION(reset_out_n), 1513 FUNCTION(rsvd1), 1514 FUNCTION(rsvd2), 1515 FUNCTION(rsvd3), 1516 FUNCTION(rsvd4), 1517 FUNCTION(rtck), 1518 FUNCTION(sdmmc1), 1519 FUNCTION(sdmmc2), 1520 FUNCTION(sdmmc3), 1521 FUNCTION(sdmmc4), 1522 FUNCTION(soc), 1523 FUNCTION(spdif), 1524 FUNCTION(spi1), 1525 FUNCTION(spi2), 1526 FUNCTION(spi3), 1527 FUNCTION(spi4), 1528 FUNCTION(spi5), 1529 FUNCTION(spi6), 1530 FUNCTION(sysclk), 1531 FUNCTION(trace), 1532 FUNCTION(uarta), 1533 FUNCTION(uartb), 1534 FUNCTION(uartc), 1535 FUNCTION(uartd), 1536 FUNCTION(ulpi), 1537 FUNCTION(usb), 1538 FUNCTION(vgp1), 1539 FUNCTION(vgp2), 1540 FUNCTION(vgp3), 1541 FUNCTION(vgp4), 1542 FUNCTION(vgp5), 1543 FUNCTION(vgp6), 1544 FUNCTION(vi), 1545 FUNCTION(vi_alt1), 1546 FUNCTION(vi_alt3), 1547 }; 1548 1549 #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 1550 #define PINGROUP_REG_A 0x3000 /* bank 1 */ 1551 1552 #define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) 1553 #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) 1554 1555 #define PINGROUP_BIT_Y(b) (b) 1556 #define PINGROUP_BIT_N(b) (-1) 1557 1558 #define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \ 1559 { \ 1560 .name = #pg_name, \ 1561 .pins = pg_name##_pins, \ 1562 .npins = ARRAY_SIZE(pg_name##_pins), \ 1563 .funcs = { \ 1564 TEGRA_MUX_##f0, \ 1565 TEGRA_MUX_##f1, \ 1566 TEGRA_MUX_##f2, \ 1567 TEGRA_MUX_##f3, \ 1568 }, \ 1569 .mux_reg = PINGROUP_REG(r), \ 1570 .mux_bank = 1, \ 1571 .mux_bit = 0, \ 1572 .pupd_reg = PINGROUP_REG(r), \ 1573 .pupd_bank = 1, \ 1574 .pupd_bit = 2, \ 1575 .tri_reg = PINGROUP_REG(r), \ 1576 .tri_bank = 1, \ 1577 .tri_bit = 4, \ 1578 .einput_bit = 5, \ 1579 .odrain_bit = PINGROUP_BIT_##od(6), \ 1580 .lock_bit = 7, \ 1581 .ioreset_bit = PINGROUP_BIT_##ior(8), \ 1582 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \ 1583 .parked_bit = -1, \ 1584 .drv_reg = -1, \ 1585 } 1586 1587 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \ 1588 drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \ 1589 slwf_b, slwf_w, drvtype) \ 1590 { \ 1591 .name = "drive_" #pg_name, \ 1592 .pins = drive_##pg_name##_pins, \ 1593 .npins = ARRAY_SIZE(drive_##pg_name##_pins), \ 1594 .mux_reg = -1, \ 1595 .pupd_reg = -1, \ 1596 .tri_reg = -1, \ 1597 .einput_bit = -1, \ 1598 .odrain_bit = -1, \ 1599 .lock_bit = -1, \ 1600 .ioreset_bit = -1, \ 1601 .rcv_sel_bit = -1, \ 1602 .drv_reg = DRV_PINGROUP_REG(r), \ 1603 .drv_bank = 0, \ 1604 .parked_bit = -1, \ 1605 .hsm_bit = hsm_b, \ 1606 .schmitt_bit = schmitt_b, \ 1607 .lpmd_bit = lpmd_b, \ 1608 .drvdn_bit = drvdn_b, \ 1609 .drvdn_width = drvdn_w, \ 1610 .drvup_bit = drvup_b, \ 1611 .drvup_width = drvup_w, \ 1612 .slwr_bit = slwr_b, \ 1613 .slwr_width = slwr_w, \ 1614 .slwf_bit = slwf_b, \ 1615 .slwf_width = slwf_w, \ 1616 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \ 1617 } 1618 1619 static const struct tegra_pingroup tegra114_groups[] = { 1620 /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */ 1621 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N), 1622 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N), 1623 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N), 1624 PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N), 1625 PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N), 1626 PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N), 1627 PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N), 1628 PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N), 1629 PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N), 1630 PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N), 1631 PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N), 1632 PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N), 1633 PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N), 1634 PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N), 1635 PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3038, N, N, N), 1636 PINGROUP(dap3_sclk_pp3, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x303c, N, N, N), 1637 PINGROUP(pv0, USB, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N), 1638 PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N), 1639 PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N), 1640 PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N), 1641 PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N), 1642 PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N), 1643 PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N), 1644 PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N), 1645 PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N), 1646 PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N), 1647 PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y), 1648 PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y), 1649 PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y), 1650 PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N), 1651 PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N), 1652 PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, RSVD3, SPI4, 0x316c, N, N, N), 1653 PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, RSVD3, SPI4, 0x3170, N, N, N), 1654 PINGROUP(uart3_txd_pw6, UARTC, RSVD2, RSVD3, SPI4, 0x3174, N, N, N), 1655 PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, RSVD3, SPI4, 0x3178, N, N, N), 1656 PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, SPI4, 0x317c, N, N, N), 1657 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, DISPLAYA, 0x3180, N, N, N), 1658 PINGROUP(pu0, OWR, UARTA, RSVD3, RSVD4, 0x3184, N, N, N), 1659 PINGROUP(pu1, RSVD1, UARTA, RSVD3, RSVD4, 0x3188, N, N, N), 1660 PINGROUP(pu2, RSVD1, UARTA, RSVD3, RSVD4, 0x318c, N, N, N), 1661 PINGROUP(pu3, PWM0, UARTA, DISPLAYA, DISPLAYB, 0x3190, N, N, N), 1662 PINGROUP(pu4, PWM1, UARTA, DISPLAYA, DISPLAYB, 0x3194, N, N, N), 1663 PINGROUP(pu5, PWM2, UARTA, DISPLAYA, DISPLAYB, 0x3198, N, N, N), 1664 PINGROUP(pu6, PWM3, UARTA, USB, DISPLAYB, 0x319c, N, N, N), 1665 PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N), 1666 PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N), 1667 PINGROUP(dap4_fs_pp4, I2S3, RSVD2, DTV, RSVD4, 0x31a8, N, N, N), 1668 PINGROUP(dap4_din_pp5, I2S3, RSVD2, RSVD3, RSVD4, 0x31ac, N, N, N), 1669 PINGROUP(dap4_dout_pp6, I2S3, RSVD2, DTV, RSVD4, 0x31b0, N, N, N), 1670 PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, RSVD3, RSVD4, 0x31b4, N, N, N), 1671 PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N), 1672 PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N), 1673 PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N, N), 1674 PINGROUP(gmi_iordy_pi5, SDMMC2, RSVD2, GMI, TRACE, 0x31c4, N, N, N), 1675 PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, 0x31c8, N, N, N), 1676 PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, 0x31cc, N, N, N), 1677 PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, 0x31d0, N, N, N), 1678 PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, 0x31d4, N, N, N), 1679 PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, 0x31d8, N, N, N), 1680 PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, 0x31dc, N, N, N), 1681 PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, 0x31e0, N, N, N), 1682 PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, 0x31e4, N, N, N), 1683 PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, 0x31e8, N, N, N), 1684 PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, SDMMC2, 0x31ec, N, N, N), 1685 PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, N, N), 1686 PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, N, N), 1687 PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, N, N), 1688 PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, N, N), 1689 PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, N, N), 1690 PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, SPI4, 0x3204, N, N, N), 1691 PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, SPI4, 0x3208, N, N, N), 1692 PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, SPI4, 0x320c, N, N, N), 1693 PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, DTV, 0x3210, N, N, N), 1694 PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, CLDVFS, 0x3214, N, N, N), 1695 PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, CLDVFS, 0x3218, N, N, N), 1696 PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, USB, 0x321c, N, N, N), 1697 PINGROUP(gmi_ad12_ph4, SDMMC2, NAND, GMI, RSVD4, 0x3220, N, N, N), 1698 PINGROUP(gmi_ad13_ph5, SDMMC2, NAND, GMI, RSVD4, 0x3224, N, N, N), 1699 PINGROUP(gmi_ad14_ph6, SDMMC2, NAND, GMI, DTV, 0x3228, N, N, N), 1700 PINGROUP(gmi_ad15_ph7, SDMMC2, NAND, GMI, DTV, 0x322c, N, N, N), 1701 PINGROUP(gmi_a16_pj7, UARTD, TRACE, GMI, GMI_ALT, 0x3230, N, N, N), 1702 PINGROUP(gmi_a17_pb0, UARTD, RSVD2, GMI, TRACE, 0x3234, N, N, N), 1703 PINGROUP(gmi_a18_pb1, UARTD, RSVD2, GMI, TRACE, 0x3238, N, N, N), 1704 PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, TRACE, 0x323c, N, N, N), 1705 PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, SPI4, 0x3240, N, N, N), 1706 PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, SOC, 0x3244, N, N, N), 1707 PINGROUP(gmi_dqs_p_pj3, SDMMC2, NAND, GMI, TRACE, 0x3248, N, N, N), 1708 PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, 0x324c, N, N, N), 1709 PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N), 1710 PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N), 1711 PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N), 1712 PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N), 1713 PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N), 1714 PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N), 1715 PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N), 1716 PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N), 1717 PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N), 1718 PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, GMI, RSVD4, 0x3274, N, Y, N), 1719 PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N), 1720 PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N), 1721 PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, RSVD4, 0x3284, N, N, N), 1722 PINGROUP(pcc1, I2S4, RSVD2, RSVD3, RSVD4, 0x3288, N, N, N), 1723 PINGROUP(pbb0, I2S4, VI, VI_ALT1, VI_ALT3, 0x328c, N, N, N), 1724 PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, RSVD4, 0x3290, Y, N, N), 1725 PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, RSVD4, 0x3294, Y, N, N), 1726 PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, RSVD4, 0x3298, N, N, N), 1727 PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, RSVD4, 0x329c, N, N, N), 1728 PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, RSVD4, 0x32a0, N, N, N), 1729 PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, RSVD4, 0x32a4, N, N, N), 1730 PINGROUP(pbb7, I2S4, RSVD2, RSVD3, RSVD4, 0x32a8, N, N, N), 1731 PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, 0x32ac, N, N, N), 1732 PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N), 1733 PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N), 1734 PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N), 1735 PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N), 1736 PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N), 1737 PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N), 1738 PINGROUP(kb_row3_pr3, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32c8, N, N, N), 1739 PINGROUP(kb_row4_pr4, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32cc, N, N, N), 1740 PINGROUP(kb_row5_pr5, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32d0, N, N, N), 1741 PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N), 1742 PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N), 1743 PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N), 1744 PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N), 1745 PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N), 1746 PINGROUP(kb_col0_pq0, KBC, USB, SPI2, EMC_DLL, 0x32fc, N, N, N), 1747 PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, EMC_DLL, 0x3300, N, N, N), 1748 PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N), 1749 PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N), 1750 PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N), 1751 PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC1, RSVD4, 0x3310, N, N, N), 1752 PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, RSVD4, 0x3314, N, N, N), 1753 PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, RSVD4, 0x3318, N, N, N), 1754 PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N), 1755 PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N, N), 1756 PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N), 1757 PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N), 1758 PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N), 1759 PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N), 1760 PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y), 1761 PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N), 1762 PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N), 1763 PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, RSVD4, 0x3340, N, N, N), 1764 PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N), 1765 PINGROUP(clk1_req_pee2, DAP, DAP1, RSVD3, RSVD4, 0x3348, N, N, N), 1766 PINGROUP(clk1_out_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N), 1767 PINGROUP(spdif_in_pk6, SPDIF, USB, RSVD3, RSVD4, 0x3350, N, N, N), 1768 PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, RSVD4, 0x3354, N, N, N), 1769 PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, RSVD4, 0x3358, N, N, N), 1770 PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, RSVD4, 0x335c, N, N, N), 1771 PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, RSVD4, 0x3360, N, N, N), 1772 PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, RSVD4, 0x3364, N, N, N), 1773 PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, RSVD3, RSVD4, 0x3368, N, N, N), 1774 PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, RSVD3, RSVD4, 0x336c, N, N, N), 1775 PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, RSVD3, RSVD4, 0x3370, N, N, N), 1776 PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, RSVD3, RSVD4, 0x3374, N, N, N), 1777 PINGROUP(gpio_x4_aud_px4, RSVD1, SPI1, SPI2, DAP2, 0x3378, N, N, N), 1778 PINGROUP(gpio_x5_aud_px5, RSVD1, SPI1, SPI2, RSVD4, 0x337c, N, N, N), 1779 PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, RSVD4, 0x3380, N, N, N), 1780 PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N), 1781 PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N), 1782 PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N), 1783 PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N), 1784 PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N), 1785 PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N), 1786 PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N), 1787 PINGROUP(hdmi_cec_pee3, CEC, SDMMC3, RSVD3, SOC, 0x33e0, Y, N, N), 1788 PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N), 1789 PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N), 1790 PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N), 1791 PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N), 1792 PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N), 1793 PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N), 1794 PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N), 1795 PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N), 1796 PINGROUP(gmi_clk_lb, SDMMC2, NAND, GMI, RSVD4, 0x3404, N, N, N), 1797 PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N), 1798 1799 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */ 1800 DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1801 DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1802 DRV_PINGROUP(at1, 0x870, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1803 DRV_PINGROUP(at2, 0x874, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1804 DRV_PINGROUP(at3, 0x878, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1805 DRV_PINGROUP(at4, 0x87c, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y), 1806 DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1807 DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1808 DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1809 DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1810 DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1811 DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1812 DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1813 DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1814 DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), 1815 DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1816 DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1817 DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1818 DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1819 DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1820 DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N), 1821 DRV_PINGROUP(ddc, 0x8fc, 2, 3, -1, 12, 5, 20, 5, 28, 2, 30, 2, N), 1822 DRV_PINGROUP(gma, 0x900, 2, 3, -1, 14, 5, 20, 5, 28, 2, 30, 2, N), 1823 DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1824 DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1825 DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1826 DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N), 1827 DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1828 DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1829 DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1830 DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1831 DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, Y), 1832 DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1833 DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1834 DRV_PINGROUP(ao3, 0x9a0, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N), 1835 DRV_PINGROUP(hv0, 0x9a4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N), 1836 DRV_PINGROUP(sdio4, 0x9a8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1837 DRV_PINGROUP(ao0, 0x9ac, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 1838 }; 1839 1840 static const struct tegra_pinctrl_soc_data tegra114_pinctrl = { 1841 .ngpios = NUM_GPIOS, 1842 .gpio_compatible = "nvidia,tegra30-gpio", 1843 .pins = tegra114_pins, 1844 .npins = ARRAY_SIZE(tegra114_pins), 1845 .functions = tegra114_functions, 1846 .nfunctions = ARRAY_SIZE(tegra114_functions), 1847 .groups = tegra114_groups, 1848 .ngroups = ARRAY_SIZE(tegra114_groups), 1849 .hsm_in_mux = false, 1850 .schmitt_in_mux = false, 1851 .drvtype_in_mux = false, 1852 }; 1853 1854 static int tegra114_pinctrl_probe(struct platform_device *pdev) 1855 { 1856 return tegra_pinctrl_probe(pdev, &tegra114_pinctrl); 1857 } 1858 1859 static const struct of_device_id tegra114_pinctrl_of_match[] = { 1860 { .compatible = "nvidia,tegra114-pinmux", }, 1861 { }, 1862 }; 1863 1864 static struct platform_driver tegra114_pinctrl_driver = { 1865 .driver = { 1866 .name = "tegra114-pinctrl", 1867 .of_match_table = tegra114_pinctrl_of_match, 1868 }, 1869 .probe = tegra114_pinctrl_probe, 1870 }; 1871 1872 static int __init tegra114_pinctrl_init(void) 1873 { 1874 return platform_driver_register(&tegra114_pinctrl_driver); 1875 } 1876 arch_initcall(tegra114_pinctrl_init); 1877