1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Driver for the NVIDIA Tegra pinmux 4 * 5 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #ifndef __PINMUX_TEGRA_H__ 9 #define __PINMUX_TEGRA_H__ 10 11 struct tegra_pmx { 12 struct device *dev; 13 struct pinctrl_dev *pctl; 14 15 const struct tegra_pinctrl_soc_data *soc; 16 const char **group_pins; 17 18 int nbanks; 19 void __iomem **regs; 20 }; 21 22 enum tegra_pinconf_param { 23 /* argument: tegra_pinconf_pull */ 24 TEGRA_PINCONF_PARAM_PULL, 25 /* argument: tegra_pinconf_tristate */ 26 TEGRA_PINCONF_PARAM_TRISTATE, 27 /* argument: Boolean */ 28 TEGRA_PINCONF_PARAM_ENABLE_INPUT, 29 /* argument: Boolean */ 30 TEGRA_PINCONF_PARAM_OPEN_DRAIN, 31 /* argument: Boolean */ 32 TEGRA_PINCONF_PARAM_LOCK, 33 /* argument: Boolean */ 34 TEGRA_PINCONF_PARAM_IORESET, 35 /* argument: Boolean */ 36 TEGRA_PINCONF_PARAM_RCV_SEL, 37 /* argument: Boolean */ 38 TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 39 /* argument: Boolean */ 40 TEGRA_PINCONF_PARAM_SCHMITT, 41 /* argument: Boolean */ 42 TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 43 /* argument: Integer, range is HW-dependant */ 44 TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 45 /* argument: Integer, range is HW-dependant */ 46 TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 47 /* argument: Integer, range is HW-dependant */ 48 TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 49 /* argument: Integer, range is HW-dependant */ 50 TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 51 /* argument: Integer, range is HW-dependant */ 52 TEGRA_PINCONF_PARAM_DRIVE_TYPE, 53 }; 54 55 enum tegra_pinconf_pull { 56 TEGRA_PINCONFIG_PULL_NONE, 57 TEGRA_PINCONFIG_PULL_DOWN, 58 TEGRA_PINCONFIG_PULL_UP, 59 }; 60 61 enum tegra_pinconf_tristate { 62 TEGRA_PINCONFIG_DRIVEN, 63 TEGRA_PINCONFIG_TRISTATE, 64 }; 65 66 #define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_)) 67 #define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16) 68 #define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff) 69 70 /** 71 * struct tegra_function - Tegra pinctrl mux function 72 * @name: The name of the function, exported to pinctrl core. 73 * @groups: An array of pin groups that may select this function. 74 * @ngroups: The number of entries in @groups. 75 */ 76 struct tegra_function { 77 const char *name; 78 const char **groups; 79 unsigned ngroups; 80 }; 81 82 /** 83 * struct tegra_pingroup - Tegra pin group 84 * @name The name of the pin group. 85 * @pins An array of pin IDs included in this pin group. 86 * @npins The number of entries in @pins. 87 * @funcs The mux functions which can be muxed onto this group. 88 * @mux_reg: Mux register offset. 89 * This register contains the mux, einput, odrain, lock, 90 * ioreset, rcv_sel parameters. 91 * @mux_bank: Mux register bank. 92 * @mux_bit: Mux register bit. 93 * @pupd_reg: Pull-up/down register offset. 94 * @pupd_bank: Pull-up/down register bank. 95 * @pupd_bit: Pull-up/down register bit. 96 * @tri_reg: Tri-state register offset. 97 * @tri_bank: Tri-state register bank. 98 * @tri_bit: Tri-state register bit. 99 * @parked_bit: Parked register bit. -1 if unsupported. 100 * @einput_bit: Enable-input register bit. 101 * @odrain_bit: Open-drain register bit. 102 * @lock_bit: Lock register bit. 103 * @ioreset_bit: IO reset register bit. 104 * @rcv_sel_bit: Receiver select bit. 105 * @drv_reg: Drive fields register offset. 106 * This register contains hsm, schmitt, lpmd, drvdn, 107 * drvup, slwr, slwf, and drvtype parameters. 108 * @drv_bank: Drive fields register bank. 109 * @hsm_bit: High Speed Mode register bit. 110 * @schmitt_bit: Scmitt register bit. 111 * @lpmd_bit: Low Power Mode register bit. 112 * @drvdn_bit: Drive Down register bit. 113 * @drvdn_width: Drive Down field width. 114 * @drvup_bit: Drive Up register bit. 115 * @drvup_width: Drive Up field width. 116 * @slwr_bit: Slew Rising register bit. 117 * @slwr_width: Slew Rising field width. 118 * @slwf_bit: Slew Falling register bit. 119 * @slwf_width: Slew Falling field width. 120 * @drvtype_bit: Drive type register bit. 121 * 122 * -1 in a *_reg field means that feature is unsupported for this group. 123 * *_bank and *_reg values are irrelevant when *_reg is -1. 124 * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature. 125 * 126 * A representation of a group of pins (possibly just one pin) in the Tegra 127 * pin controller. Each group allows some parameter or parameters to be 128 * configured. The most common is mux function selection. Many others exist 129 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex; 130 * certain groups may only support configuring certain parameters, hence 131 * each parameter is optional. 132 */ 133 struct tegra_pingroup { 134 const char *name; 135 const unsigned *pins; 136 u8 npins; 137 u8 funcs[4]; 138 s16 mux_reg; 139 s16 pupd_reg; 140 s16 tri_reg; 141 s16 drv_reg; 142 u32 mux_bank:2; 143 u32 pupd_bank:2; 144 u32 tri_bank:2; 145 u32 drv_bank:2; 146 s32 mux_bit:6; 147 s32 pupd_bit:6; 148 s32 tri_bit:6; 149 s32 parked_bit:6; 150 s32 einput_bit:6; 151 s32 odrain_bit:6; 152 s32 lock_bit:6; 153 s32 ioreset_bit:6; 154 s32 rcv_sel_bit:6; 155 s32 hsm_bit:6; 156 s32 schmitt_bit:6; 157 s32 lpmd_bit:6; 158 s32 drvdn_bit:6; 159 s32 drvup_bit:6; 160 s32 slwr_bit:6; 161 s32 slwf_bit:6; 162 s32 drvtype_bit:6; 163 s32 drvdn_width:6; 164 s32 drvup_width:6; 165 s32 slwr_width:6; 166 s32 slwf_width:6; 167 }; 168 169 /** 170 * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration 171 * @ngpios: The number of GPIO pins the pin controller HW affects. 172 * @pins: An array describing all pins the pin controller affects. 173 * All pins which are also GPIOs must be listed first within the 174 * array, and be numbered identically to the GPIO controller's 175 * numbering. 176 * @npins: The numbmer of entries in @pins. 177 * @functions: An array describing all mux functions the SoC supports. 178 * @nfunctions: The numbmer of entries in @functions. 179 * @groups: An array describing all pin groups the pin SoC supports. 180 * @ngroups: The numbmer of entries in @groups. 181 */ 182 struct tegra_pinctrl_soc_data { 183 unsigned ngpios; 184 const char *gpio_compatible; 185 const struct pinctrl_pin_desc *pins; 186 unsigned npins; 187 struct tegra_function *functions; 188 unsigned nfunctions; 189 const struct tegra_pingroup *groups; 190 unsigned ngroups; 191 bool hsm_in_mux; 192 bool schmitt_in_mux; 193 bool drvtype_in_mux; 194 }; 195 196 int tegra_pinctrl_probe(struct platform_device *pdev, 197 const struct tegra_pinctrl_soc_data *soc_data); 198 #endif 199