1 /* 2 * Driver for the NVIDIA Tegra pinmux 3 * 4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef __PINMUX_TEGRA_H__ 17 #define __PINMUX_TEGRA_H__ 18 19 struct tegra_pmx { 20 struct device *dev; 21 struct pinctrl_dev *pctl; 22 23 const struct tegra_pinctrl_soc_data *soc; 24 const char **group_pins; 25 26 int nbanks; 27 void __iomem **regs; 28 }; 29 30 enum tegra_pinconf_param { 31 /* argument: tegra_pinconf_pull */ 32 TEGRA_PINCONF_PARAM_PULL, 33 /* argument: tegra_pinconf_tristate */ 34 TEGRA_PINCONF_PARAM_TRISTATE, 35 /* argument: Boolean */ 36 TEGRA_PINCONF_PARAM_ENABLE_INPUT, 37 /* argument: Boolean */ 38 TEGRA_PINCONF_PARAM_OPEN_DRAIN, 39 /* argument: Boolean */ 40 TEGRA_PINCONF_PARAM_LOCK, 41 /* argument: Boolean */ 42 TEGRA_PINCONF_PARAM_IORESET, 43 /* argument: Boolean */ 44 TEGRA_PINCONF_PARAM_RCV_SEL, 45 /* argument: Boolean */ 46 TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 47 /* argument: Boolean */ 48 TEGRA_PINCONF_PARAM_SCHMITT, 49 /* argument: Boolean */ 50 TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 51 /* argument: Integer, range is HW-dependant */ 52 TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 53 /* argument: Integer, range is HW-dependant */ 54 TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 55 /* argument: Integer, range is HW-dependant */ 56 TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 57 /* argument: Integer, range is HW-dependant */ 58 TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 59 /* argument: Integer, range is HW-dependant */ 60 TEGRA_PINCONF_PARAM_DRIVE_TYPE, 61 }; 62 63 enum tegra_pinconf_pull { 64 TEGRA_PINCONFIG_PULL_NONE, 65 TEGRA_PINCONFIG_PULL_DOWN, 66 TEGRA_PINCONFIG_PULL_UP, 67 }; 68 69 enum tegra_pinconf_tristate { 70 TEGRA_PINCONFIG_DRIVEN, 71 TEGRA_PINCONFIG_TRISTATE, 72 }; 73 74 #define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_)) 75 #define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16) 76 #define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff) 77 78 /** 79 * struct tegra_function - Tegra pinctrl mux function 80 * @name: The name of the function, exported to pinctrl core. 81 * @groups: An array of pin groups that may select this function. 82 * @ngroups: The number of entries in @groups. 83 */ 84 struct tegra_function { 85 const char *name; 86 const char **groups; 87 unsigned ngroups; 88 }; 89 90 /** 91 * struct tegra_pingroup - Tegra pin group 92 * @name The name of the pin group. 93 * @pins An array of pin IDs included in this pin group. 94 * @npins The number of entries in @pins. 95 * @funcs The mux functions which can be muxed onto this group. 96 * @mux_reg: Mux register offset. 97 * This register contains the mux, einput, odrain, lock, 98 * ioreset, rcv_sel parameters. 99 * @mux_bank: Mux register bank. 100 * @mux_bit: Mux register bit. 101 * @pupd_reg: Pull-up/down register offset. 102 * @pupd_bank: Pull-up/down register bank. 103 * @pupd_bit: Pull-up/down register bit. 104 * @tri_reg: Tri-state register offset. 105 * @tri_bank: Tri-state register bank. 106 * @tri_bit: Tri-state register bit. 107 * @parked_bit: Parked register bit. -1 if unsupported. 108 * @einput_bit: Enable-input register bit. 109 * @odrain_bit: Open-drain register bit. 110 * @lock_bit: Lock register bit. 111 * @ioreset_bit: IO reset register bit. 112 * @rcv_sel_bit: Receiver select bit. 113 * @drv_reg: Drive fields register offset. 114 * This register contains hsm, schmitt, lpmd, drvdn, 115 * drvup, slwr, slwf, and drvtype parameters. 116 * @drv_bank: Drive fields register bank. 117 * @hsm_bit: High Speed Mode register bit. 118 * @schmitt_bit: Scmitt register bit. 119 * @lpmd_bit: Low Power Mode register bit. 120 * @drvdn_bit: Drive Down register bit. 121 * @drvdn_width: Drive Down field width. 122 * @drvup_bit: Drive Up register bit. 123 * @drvup_width: Drive Up field width. 124 * @slwr_bit: Slew Rising register bit. 125 * @slwr_width: Slew Rising field width. 126 * @slwf_bit: Slew Falling register bit. 127 * @slwf_width: Slew Falling field width. 128 * @drvtype_bit: Drive type register bit. 129 * 130 * -1 in a *_reg field means that feature is unsupported for this group. 131 * *_bank and *_reg values are irrelevant when *_reg is -1. 132 * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature. 133 * 134 * A representation of a group of pins (possibly just one pin) in the Tegra 135 * pin controller. Each group allows some parameter or parameters to be 136 * configured. The most common is mux function selection. Many others exist 137 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex; 138 * certain groups may only support configuring certain parameters, hence 139 * each parameter is optional. 140 */ 141 struct tegra_pingroup { 142 const char *name; 143 const unsigned *pins; 144 u8 npins; 145 u8 funcs[4]; 146 s16 mux_reg; 147 s16 pupd_reg; 148 s16 tri_reg; 149 s16 drv_reg; 150 u32 mux_bank:2; 151 u32 pupd_bank:2; 152 u32 tri_bank:2; 153 u32 drv_bank:2; 154 s32 mux_bit:6; 155 s32 pupd_bit:6; 156 s32 tri_bit:6; 157 s32 parked_bit:6; 158 s32 einput_bit:6; 159 s32 odrain_bit:6; 160 s32 lock_bit:6; 161 s32 ioreset_bit:6; 162 s32 rcv_sel_bit:6; 163 s32 hsm_bit:6; 164 s32 schmitt_bit:6; 165 s32 lpmd_bit:6; 166 s32 drvdn_bit:6; 167 s32 drvup_bit:6; 168 s32 slwr_bit:6; 169 s32 slwf_bit:6; 170 s32 drvtype_bit:6; 171 s32 drvdn_width:6; 172 s32 drvup_width:6; 173 s32 slwr_width:6; 174 s32 slwf_width:6; 175 }; 176 177 /** 178 * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration 179 * @ngpios: The number of GPIO pins the pin controller HW affects. 180 * @pins: An array describing all pins the pin controller affects. 181 * All pins which are also GPIOs must be listed first within the 182 * array, and be numbered identically to the GPIO controller's 183 * numbering. 184 * @npins: The numbmer of entries in @pins. 185 * @functions: An array describing all mux functions the SoC supports. 186 * @nfunctions: The numbmer of entries in @functions. 187 * @groups: An array describing all pin groups the pin SoC supports. 188 * @ngroups: The numbmer of entries in @groups. 189 */ 190 struct tegra_pinctrl_soc_data { 191 unsigned ngpios; 192 const struct pinctrl_pin_desc *pins; 193 unsigned npins; 194 struct tegra_function *functions; 195 unsigned nfunctions; 196 const struct tegra_pingroup *groups; 197 unsigned ngroups; 198 bool hsm_in_mux; 199 bool schmitt_in_mux; 200 bool drvtype_in_mux; 201 }; 202 203 int tegra_pinctrl_probe(struct platform_device *pdev, 204 const struct tegra_pinctrl_soc_data *soc_data); 205 #endif 206