1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Driver for the NVIDIA Tegra pinmux
4  *
5  * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
6  */
7 
8 #ifndef __PINMUX_TEGRA_H__
9 #define __PINMUX_TEGRA_H__
10 
11 struct tegra_pmx {
12 	struct device *dev;
13 	struct pinctrl_dev *pctl;
14 
15 	const struct tegra_pinctrl_soc_data *soc;
16 	struct tegra_function *functions;
17 	const char **group_pins;
18 
19 	struct pinctrl_gpio_range gpio_range;
20 	struct pinctrl_desc desc;
21 	int nbanks;
22 	void __iomem **regs;
23 	u32 *backup_regs;
24 };
25 
26 enum tegra_pinconf_param {
27 	/* argument: tegra_pinconf_pull */
28 	TEGRA_PINCONF_PARAM_PULL,
29 	/* argument: tegra_pinconf_tristate */
30 	TEGRA_PINCONF_PARAM_TRISTATE,
31 	/* argument: Boolean */
32 	TEGRA_PINCONF_PARAM_ENABLE_INPUT,
33 	/* argument: Boolean */
34 	TEGRA_PINCONF_PARAM_OPEN_DRAIN,
35 	/* argument: Boolean */
36 	TEGRA_PINCONF_PARAM_LOCK,
37 	/* argument: Boolean */
38 	TEGRA_PINCONF_PARAM_IORESET,
39 	/* argument: Boolean */
40 	TEGRA_PINCONF_PARAM_RCV_SEL,
41 	/* argument: Boolean */
42 	TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
43 	/* argument: Boolean */
44 	TEGRA_PINCONF_PARAM_SCHMITT,
45 	/* argument: Boolean */
46 	TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
47 	/* argument: Integer, range is HW-dependant */
48 	TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
49 	/* argument: Integer, range is HW-dependant */
50 	TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
51 	/* argument: Integer, range is HW-dependant */
52 	TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
53 	/* argument: Integer, range is HW-dependant */
54 	TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
55 	/* argument: Integer, range is HW-dependant */
56 	TEGRA_PINCONF_PARAM_DRIVE_TYPE,
57 	/* argument: pinmux settings */
58 	TEGRA_PINCONF_PARAM_FUNCTION,
59 };
60 
61 enum tegra_pinconf_pull {
62 	TEGRA_PINCONFIG_PULL_NONE,
63 	TEGRA_PINCONFIG_PULL_DOWN,
64 	TEGRA_PINCONFIG_PULL_UP,
65 };
66 
67 enum tegra_pinconf_tristate {
68 	TEGRA_PINCONFIG_DRIVEN,
69 	TEGRA_PINCONFIG_TRISTATE,
70 };
71 
72 #define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
73 #define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
74 #define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
75 
76 /**
77  * struct tegra_function - Tegra pinctrl mux function
78  * @name: The name of the function, exported to pinctrl core.
79  * @groups: An array of pin groups that may select this function.
80  * @ngroups: The number of entries in @groups.
81  */
82 struct tegra_function {
83 	const char *name;
84 	const char **groups;
85 	unsigned ngroups;
86 };
87 
88 /**
89  * struct tegra_pingroup - Tegra pin group
90  * @name		The name of the pin group.
91  * @pins		An array of pin IDs included in this pin group.
92  * @npins		The number of entries in @pins.
93  * @funcs		The mux functions which can be muxed onto this group.
94  * @mux_reg:		Mux register offset.
95  *			This register contains the mux, einput, odrain, lock,
96  *			ioreset, rcv_sel parameters.
97  * @mux_bank:		Mux register bank.
98  * @mux_bit:		Mux register bit.
99  * @pupd_reg:		Pull-up/down register offset.
100  * @pupd_bank:		Pull-up/down register bank.
101  * @pupd_bit:		Pull-up/down register bit.
102  * @tri_reg:		Tri-state register offset.
103  * @tri_bank:		Tri-state register bank.
104  * @tri_bit:		Tri-state register bit.
105  * @einput_bit:		Enable-input register bit.
106  * @odrain_bit:		Open-drain register bit.
107  * @lock_bit:		Lock register bit.
108  * @ioreset_bit:	IO reset register bit.
109  * @rcv_sel_bit:	Receiver select bit.
110  * @drv_reg:		Drive fields register offset.
111  *			This register contains hsm, schmitt, lpmd, drvdn,
112  *			drvup, slwr, slwf, and drvtype parameters.
113  * @drv_bank:		Drive fields register bank.
114  * @hsm_bit:		High Speed Mode register bit.
115  * @sfsel_bit:		GPIO/SFIO selection register bit.
116  * @schmitt_bit:	Schmitt register bit.
117  * @lpmd_bit:		Low Power Mode register bit.
118  * @drvdn_bit:		Drive Down register bit.
119  * @drvdn_width:	Drive Down field width.
120  * @drvup_bit:		Drive Up register bit.
121  * @drvup_width:	Drive Up field width.
122  * @slwr_bit:		Slew Rising register bit.
123  * @slwr_width:		Slew Rising field width.
124  * @slwf_bit:		Slew Falling register bit.
125  * @slwf_width:		Slew Falling field width.
126  * @lpdr_bit:		Base driver enabling bit.
127  * @drvtype_bit:	Drive type register bit.
128  * @parked_bitmask:	Parked register mask. 0 if unsupported.
129  *
130  * -1 in a *_reg field means that feature is unsupported for this group.
131  * *_bank and *_reg values are irrelevant when *_reg is -1.
132  * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
133  *
134  * A representation of a group of pins (possibly just one pin) in the Tegra
135  * pin controller. Each group allows some parameter or parameters to be
136  * configured. The most common is mux function selection. Many others exist
137  * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
138  * certain groups may only support configuring certain parameters, hence
139  * each parameter is optional.
140  */
141 struct tegra_pingroup {
142 	const char *name;
143 	const unsigned *pins;
144 	u8 npins;
145 	u8 funcs[4];
146 	s32 mux_reg;
147 	s32 pupd_reg;
148 	s32 tri_reg;
149 	s32 drv_reg;
150 	u32 mux_bank:2;
151 	u32 pupd_bank:2;
152 	u32 tri_bank:2;
153 	u32 drv_bank:2;
154 	s32 mux_bit:6;
155 	s32 pupd_bit:6;
156 	s32 tri_bit:6;
157 	s32 einput_bit:6;
158 	s32 odrain_bit:6;
159 	s32 lock_bit:6;
160 	s32 ioreset_bit:6;
161 	s32 rcv_sel_bit:6;
162 	s32 hsm_bit:6;
163 	s32 sfsel_bit:6;
164 	s32 schmitt_bit:6;
165 	s32 lpmd_bit:6;
166 	s32 drvdn_bit:6;
167 	s32 drvup_bit:6;
168 	s32 slwr_bit:6;
169 	s32 slwf_bit:6;
170 	s32 lpdr_bit:6;
171 	s32 drvtype_bit:6;
172 	s32 drvdn_width:6;
173 	s32 drvup_width:6;
174 	s32 slwr_width:6;
175 	s32 slwf_width:6;
176 	u32 parked_bitmask;
177 };
178 
179 /**
180  * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
181  * @ngpios:	The number of GPIO pins the pin controller HW affects.
182  * @pins:	An array describing all pins the pin controller affects.
183  *		All pins which are also GPIOs must be listed first within the
184  *		array, and be numbered identically to the GPIO controller's
185  *		numbering.
186  * @npins:	The numbmer of entries in @pins.
187  * @functions:	An array describing all mux functions the SoC supports.
188  * @nfunctions:	The numbmer of entries in @functions.
189  * @groups:	An array describing all pin groups the pin SoC supports.
190  * @ngroups:	The numbmer of entries in @groups.
191  */
192 struct tegra_pinctrl_soc_data {
193 	unsigned ngpios;
194 	const char *gpio_compatible;
195 	const struct pinctrl_pin_desc *pins;
196 	unsigned npins;
197 	const char * const *functions;
198 	unsigned nfunctions;
199 	const struct tegra_pingroup *groups;
200 	unsigned ngroups;
201 	bool hsm_in_mux;
202 	bool schmitt_in_mux;
203 	bool drvtype_in_mux;
204 	bool sfsel_in_mux;
205 };
206 
207 extern const struct dev_pm_ops tegra_pinctrl_pm;
208 
209 int tegra_pinctrl_probe(struct platform_device *pdev,
210 			const struct tegra_pinctrl_soc_data *soc_data);
211 #endif
212