1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Driver for the NVIDIA Tegra pinmux
4  *
5  * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
6  */
7 
8 #ifndef __PINMUX_TEGRA_H__
9 #define __PINMUX_TEGRA_H__
10 
11 struct tegra_pmx {
12 	struct device *dev;
13 	struct pinctrl_dev *pctl;
14 
15 	const struct tegra_pinctrl_soc_data *soc;
16 	const char **group_pins;
17 
18 	struct pinctrl_gpio_range gpio_range;
19 	struct pinctrl_desc desc;
20 	int nbanks;
21 	void __iomem **regs;
22 	u32 *backup_regs;
23 };
24 
25 enum tegra_pinconf_param {
26 	/* argument: tegra_pinconf_pull */
27 	TEGRA_PINCONF_PARAM_PULL,
28 	/* argument: tegra_pinconf_tristate */
29 	TEGRA_PINCONF_PARAM_TRISTATE,
30 	/* argument: Boolean */
31 	TEGRA_PINCONF_PARAM_ENABLE_INPUT,
32 	/* argument: Boolean */
33 	TEGRA_PINCONF_PARAM_OPEN_DRAIN,
34 	/* argument: Boolean */
35 	TEGRA_PINCONF_PARAM_LOCK,
36 	/* argument: Boolean */
37 	TEGRA_PINCONF_PARAM_IORESET,
38 	/* argument: Boolean */
39 	TEGRA_PINCONF_PARAM_RCV_SEL,
40 	/* argument: Boolean */
41 	TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
42 	/* argument: Boolean */
43 	TEGRA_PINCONF_PARAM_SCHMITT,
44 	/* argument: Boolean */
45 	TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
46 	/* argument: Integer, range is HW-dependant */
47 	TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
48 	/* argument: Integer, range is HW-dependant */
49 	TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
50 	/* argument: Integer, range is HW-dependant */
51 	TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
52 	/* argument: Integer, range is HW-dependant */
53 	TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
54 	/* argument: Integer, range is HW-dependant */
55 	TEGRA_PINCONF_PARAM_DRIVE_TYPE,
56 };
57 
58 enum tegra_pinconf_pull {
59 	TEGRA_PINCONFIG_PULL_NONE,
60 	TEGRA_PINCONFIG_PULL_DOWN,
61 	TEGRA_PINCONFIG_PULL_UP,
62 };
63 
64 enum tegra_pinconf_tristate {
65 	TEGRA_PINCONFIG_DRIVEN,
66 	TEGRA_PINCONFIG_TRISTATE,
67 };
68 
69 #define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
70 #define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
71 #define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
72 
73 /**
74  * struct tegra_function - Tegra pinctrl mux function
75  * @name: The name of the function, exported to pinctrl core.
76  * @groups: An array of pin groups that may select this function.
77  * @ngroups: The number of entries in @groups.
78  */
79 struct tegra_function {
80 	const char *name;
81 	const char **groups;
82 	unsigned ngroups;
83 };
84 
85 /**
86  * struct tegra_pingroup - Tegra pin group
87  * @name		The name of the pin group.
88  * @pins		An array of pin IDs included in this pin group.
89  * @npins		The number of entries in @pins.
90  * @funcs		The mux functions which can be muxed onto this group.
91  * @mux_reg:		Mux register offset.
92  *			This register contains the mux, einput, odrain, lock,
93  *			ioreset, rcv_sel parameters.
94  * @mux_bank:		Mux register bank.
95  * @mux_bit:		Mux register bit.
96  * @pupd_reg:		Pull-up/down register offset.
97  * @pupd_bank:		Pull-up/down register bank.
98  * @pupd_bit:		Pull-up/down register bit.
99  * @tri_reg:		Tri-state register offset.
100  * @tri_bank:		Tri-state register bank.
101  * @tri_bit:		Tri-state register bit.
102  * @einput_bit:		Enable-input register bit.
103  * @odrain_bit:		Open-drain register bit.
104  * @lock_bit:		Lock register bit.
105  * @ioreset_bit:	IO reset register bit.
106  * @rcv_sel_bit:	Receiver select bit.
107  * @drv_reg:		Drive fields register offset.
108  *			This register contains hsm, schmitt, lpmd, drvdn,
109  *			drvup, slwr, slwf, and drvtype parameters.
110  * @drv_bank:		Drive fields register bank.
111  * @hsm_bit:		High Speed Mode register bit.
112  * @sfsel_bit:		GPIO/SFIO selection register bit.
113  * @schmitt_bit:	Schmitt register bit.
114  * @lpmd_bit:		Low Power Mode register bit.
115  * @drvdn_bit:		Drive Down register bit.
116  * @drvdn_width:	Drive Down field width.
117  * @drvup_bit:		Drive Up register bit.
118  * @drvup_width:	Drive Up field width.
119  * @slwr_bit:		Slew Rising register bit.
120  * @slwr_width:		Slew Rising field width.
121  * @slwf_bit:		Slew Falling register bit.
122  * @slwf_width:		Slew Falling field width.
123  * @lpdr_bit:		Base driver enabling bit.
124  * @drvtype_bit:	Drive type register bit.
125  * @parked_bitmask:	Parked register mask. 0 if unsupported.
126  *
127  * -1 in a *_reg field means that feature is unsupported for this group.
128  * *_bank and *_reg values are irrelevant when *_reg is -1.
129  * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
130  *
131  * A representation of a group of pins (possibly just one pin) in the Tegra
132  * pin controller. Each group allows some parameter or parameters to be
133  * configured. The most common is mux function selection. Many others exist
134  * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
135  * certain groups may only support configuring certain parameters, hence
136  * each parameter is optional.
137  */
138 struct tegra_pingroup {
139 	const char *name;
140 	const unsigned *pins;
141 	u8 npins;
142 	u8 funcs[4];
143 	s32 mux_reg;
144 	s32 pupd_reg;
145 	s32 tri_reg;
146 	s32 drv_reg;
147 	u32 mux_bank:2;
148 	u32 pupd_bank:2;
149 	u32 tri_bank:2;
150 	u32 drv_bank:2;
151 	s32 mux_bit:6;
152 	s32 pupd_bit:6;
153 	s32 tri_bit:6;
154 	s32 einput_bit:6;
155 	s32 odrain_bit:6;
156 	s32 lock_bit:6;
157 	s32 ioreset_bit:6;
158 	s32 rcv_sel_bit:6;
159 	s32 hsm_bit:6;
160 	s32 sfsel_bit:6;
161 	s32 schmitt_bit:6;
162 	s32 lpmd_bit:6;
163 	s32 drvdn_bit:6;
164 	s32 drvup_bit:6;
165 	s32 slwr_bit:6;
166 	s32 slwf_bit:6;
167 	s32 lpdr_bit:6;
168 	s32 drvtype_bit:6;
169 	s32 drvdn_width:6;
170 	s32 drvup_width:6;
171 	s32 slwr_width:6;
172 	s32 slwf_width:6;
173 	u32 parked_bitmask;
174 };
175 
176 /**
177  * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
178  * @ngpios:	The number of GPIO pins the pin controller HW affects.
179  * @pins:	An array describing all pins the pin controller affects.
180  *		All pins which are also GPIOs must be listed first within the
181  *		array, and be numbered identically to the GPIO controller's
182  *		numbering.
183  * @npins:	The numbmer of entries in @pins.
184  * @functions:	An array describing all mux functions the SoC supports.
185  * @nfunctions:	The numbmer of entries in @functions.
186  * @groups:	An array describing all pin groups the pin SoC supports.
187  * @ngroups:	The numbmer of entries in @groups.
188  */
189 struct tegra_pinctrl_soc_data {
190 	unsigned ngpios;
191 	const char *gpio_compatible;
192 	const struct pinctrl_pin_desc *pins;
193 	unsigned npins;
194 	struct tegra_function *functions;
195 	unsigned nfunctions;
196 	const struct tegra_pingroup *groups;
197 	unsigned ngroups;
198 	bool hsm_in_mux;
199 	bool schmitt_in_mux;
200 	bool drvtype_in_mux;
201 	bool sfsel_in_mux;
202 };
203 
204 extern const struct dev_pm_ops tegra_pinctrl_pm;
205 
206 int tegra_pinctrl_probe(struct platform_device *pdev,
207 			const struct tegra_pinctrl_soc_data *soc_data);
208 #endif
209