1 /*
2  * Driver for the NVIDIA Tegra pinmux
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * Derived from code:
7  * Copyright (C) 2010 Google, Inc.
8  * Copyright (C) 2010 NVIDIA Corporation
9  * Copyright (C) 2009-2011 ST-Ericsson AB
10  *
11  * This program is free software; you can redistribute it and/or modify it
12  * under the terms and conditions of the GNU General Public License,
13  * version 2, as published by the Free Software Foundation.
14  *
15  * This program is distributed in the hope it will be useful, but WITHOUT
16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18  * more details.
19  */
20 
21 #include <linux/err.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/of.h>
25 #include <linux/platform_device.h>
26 #include <linux/pinctrl/machine.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/slab.h>
31 
32 #include "../core.h"
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-tegra.h"
35 
36 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
37 {
38 	return readl(pmx->regs[bank] + reg);
39 }
40 
41 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
42 {
43 	writel(val, pmx->regs[bank] + reg);
44 }
45 
46 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
47 {
48 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
49 
50 	return pmx->soc->ngroups;
51 }
52 
53 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
54 						unsigned group)
55 {
56 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
57 
58 	return pmx->soc->groups[group].name;
59 }
60 
61 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
62 					unsigned group,
63 					const unsigned **pins,
64 					unsigned *num_pins)
65 {
66 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
67 
68 	*pins = pmx->soc->groups[group].pins;
69 	*num_pins = pmx->soc->groups[group].npins;
70 
71 	return 0;
72 }
73 
74 #ifdef CONFIG_DEBUG_FS
75 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
76 				       struct seq_file *s,
77 				       unsigned offset)
78 {
79 	seq_printf(s, " %s", dev_name(pctldev->dev));
80 }
81 #endif
82 
83 static const struct cfg_param {
84 	const char *property;
85 	enum tegra_pinconf_param param;
86 } cfg_params[] = {
87 	{"nvidia,pull",			TEGRA_PINCONF_PARAM_PULL},
88 	{"nvidia,tristate",		TEGRA_PINCONF_PARAM_TRISTATE},
89 	{"nvidia,enable-input",		TEGRA_PINCONF_PARAM_ENABLE_INPUT},
90 	{"nvidia,open-drain",		TEGRA_PINCONF_PARAM_OPEN_DRAIN},
91 	{"nvidia,lock",			TEGRA_PINCONF_PARAM_LOCK},
92 	{"nvidia,io-reset",		TEGRA_PINCONF_PARAM_IORESET},
93 	{"nvidia,rcv-sel",		TEGRA_PINCONF_PARAM_RCV_SEL},
94 	{"nvidia,io-hv",		TEGRA_PINCONF_PARAM_RCV_SEL},
95 	{"nvidia,high-speed-mode",	TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
96 	{"nvidia,schmitt",		TEGRA_PINCONF_PARAM_SCHMITT},
97 	{"nvidia,low-power-mode",	TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
98 	{"nvidia,pull-down-strength",	TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
99 	{"nvidia,pull-up-strength",	TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
100 	{"nvidia,slew-rate-falling",	TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
101 	{"nvidia,slew-rate-rising",	TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
102 	{"nvidia,drive-type",		TEGRA_PINCONF_PARAM_DRIVE_TYPE},
103 };
104 
105 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
106 					   struct device_node *np,
107 					   struct pinctrl_map **map,
108 					   unsigned *reserved_maps,
109 					   unsigned *num_maps)
110 {
111 	struct device *dev = pctldev->dev;
112 	int ret, i;
113 	const char *function;
114 	u32 val;
115 	unsigned long config;
116 	unsigned long *configs = NULL;
117 	unsigned num_configs = 0;
118 	unsigned reserve;
119 	struct property *prop;
120 	const char *group;
121 
122 	ret = of_property_read_string(np, "nvidia,function", &function);
123 	if (ret < 0) {
124 		/* EINVAL=missing, which is fine since it's optional */
125 		if (ret != -EINVAL)
126 			dev_err(dev,
127 				"could not parse property nvidia,function\n");
128 		function = NULL;
129 	}
130 
131 	for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
132 		ret = of_property_read_u32(np, cfg_params[i].property, &val);
133 		if (!ret) {
134 			config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
135 			ret = pinctrl_utils_add_config(pctldev, &configs,
136 					&num_configs, config);
137 			if (ret < 0)
138 				goto exit;
139 		/* EINVAL=missing, which is fine since it's optional */
140 		} else if (ret != -EINVAL) {
141 			dev_err(dev, "could not parse property %s\n",
142 				cfg_params[i].property);
143 		}
144 	}
145 
146 	reserve = 0;
147 	if (function != NULL)
148 		reserve++;
149 	if (num_configs)
150 		reserve++;
151 	ret = of_property_count_strings(np, "nvidia,pins");
152 	if (ret < 0) {
153 		dev_err(dev, "could not parse property nvidia,pins\n");
154 		goto exit;
155 	}
156 	reserve *= ret;
157 
158 	ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
159 					num_maps, reserve);
160 	if (ret < 0)
161 		goto exit;
162 
163 	of_property_for_each_string(np, "nvidia,pins", prop, group) {
164 		if (function) {
165 			ret = pinctrl_utils_add_map_mux(pctldev, map,
166 					reserved_maps, num_maps, group,
167 					function);
168 			if (ret < 0)
169 				goto exit;
170 		}
171 
172 		if (num_configs) {
173 			ret = pinctrl_utils_add_map_configs(pctldev, map,
174 					reserved_maps, num_maps, group,
175 					configs, num_configs,
176 					PIN_MAP_TYPE_CONFIGS_GROUP);
177 			if (ret < 0)
178 				goto exit;
179 		}
180 	}
181 
182 	ret = 0;
183 
184 exit:
185 	kfree(configs);
186 	return ret;
187 }
188 
189 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
190 					struct device_node *np_config,
191 					struct pinctrl_map **map,
192 					unsigned *num_maps)
193 {
194 	unsigned reserved_maps;
195 	struct device_node *np;
196 	int ret;
197 
198 	reserved_maps = 0;
199 	*map = NULL;
200 	*num_maps = 0;
201 
202 	for_each_child_of_node(np_config, np) {
203 		ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
204 						      &reserved_maps, num_maps);
205 		if (ret < 0) {
206 			pinctrl_utils_free_map(pctldev, *map,
207 				*num_maps);
208 			of_node_put(np);
209 			return ret;
210 		}
211 	}
212 
213 	return 0;
214 }
215 
216 static const struct pinctrl_ops tegra_pinctrl_ops = {
217 	.get_groups_count = tegra_pinctrl_get_groups_count,
218 	.get_group_name = tegra_pinctrl_get_group_name,
219 	.get_group_pins = tegra_pinctrl_get_group_pins,
220 #ifdef CONFIG_DEBUG_FS
221 	.pin_dbg_show = tegra_pinctrl_pin_dbg_show,
222 #endif
223 	.dt_node_to_map = tegra_pinctrl_dt_node_to_map,
224 	.dt_free_map = pinctrl_utils_free_map,
225 };
226 
227 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
228 {
229 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
230 
231 	return pmx->soc->nfunctions;
232 }
233 
234 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
235 					       unsigned function)
236 {
237 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
238 
239 	return pmx->soc->functions[function].name;
240 }
241 
242 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
243 					 unsigned function,
244 					 const char * const **groups,
245 					 unsigned * const num_groups)
246 {
247 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
248 
249 	*groups = pmx->soc->functions[function].groups;
250 	*num_groups = pmx->soc->functions[function].ngroups;
251 
252 	return 0;
253 }
254 
255 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
256 				 unsigned function,
257 				 unsigned group)
258 {
259 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
260 	const struct tegra_pingroup *g;
261 	int i;
262 	u32 val;
263 
264 	g = &pmx->soc->groups[group];
265 
266 	if (WARN_ON(g->mux_reg < 0))
267 		return -EINVAL;
268 
269 	for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
270 		if (g->funcs[i] == function)
271 			break;
272 	}
273 	if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
274 		return -EINVAL;
275 
276 	val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
277 	val &= ~(0x3 << g->mux_bit);
278 	val |= i << g->mux_bit;
279 	pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
280 
281 	return 0;
282 }
283 
284 static const struct pinmux_ops tegra_pinmux_ops = {
285 	.get_functions_count = tegra_pinctrl_get_funcs_count,
286 	.get_function_name = tegra_pinctrl_get_func_name,
287 	.get_function_groups = tegra_pinctrl_get_func_groups,
288 	.set_mux = tegra_pinctrl_set_mux,
289 };
290 
291 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
292 			     const struct tegra_pingroup *g,
293 			     enum tegra_pinconf_param param,
294 			     bool report_err,
295 			     s8 *bank, s16 *reg, s8 *bit, s8 *width)
296 {
297 	switch (param) {
298 	case TEGRA_PINCONF_PARAM_PULL:
299 		*bank = g->pupd_bank;
300 		*reg = g->pupd_reg;
301 		*bit = g->pupd_bit;
302 		*width = 2;
303 		break;
304 	case TEGRA_PINCONF_PARAM_TRISTATE:
305 		*bank = g->tri_bank;
306 		*reg = g->tri_reg;
307 		*bit = g->tri_bit;
308 		*width = 1;
309 		break;
310 	case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
311 		*bank = g->mux_bank;
312 		*reg = g->mux_reg;
313 		*bit = g->einput_bit;
314 		*width = 1;
315 		break;
316 	case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
317 		*bank = g->mux_bank;
318 		*reg = g->mux_reg;
319 		*bit = g->odrain_bit;
320 		*width = 1;
321 		break;
322 	case TEGRA_PINCONF_PARAM_LOCK:
323 		*bank = g->mux_bank;
324 		*reg = g->mux_reg;
325 		*bit = g->lock_bit;
326 		*width = 1;
327 		break;
328 	case TEGRA_PINCONF_PARAM_IORESET:
329 		*bank = g->mux_bank;
330 		*reg = g->mux_reg;
331 		*bit = g->ioreset_bit;
332 		*width = 1;
333 		break;
334 	case TEGRA_PINCONF_PARAM_RCV_SEL:
335 		*bank = g->mux_bank;
336 		*reg = g->mux_reg;
337 		*bit = g->rcv_sel_bit;
338 		*width = 1;
339 		break;
340 	case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
341 		if (pmx->soc->hsm_in_mux) {
342 			*bank = g->mux_bank;
343 			*reg = g->mux_reg;
344 		} else {
345 			*bank = g->drv_bank;
346 			*reg = g->drv_reg;
347 		}
348 		*bit = g->hsm_bit;
349 		*width = 1;
350 		break;
351 	case TEGRA_PINCONF_PARAM_SCHMITT:
352 		if (pmx->soc->schmitt_in_mux) {
353 			*bank = g->mux_bank;
354 			*reg = g->mux_reg;
355 		} else {
356 			*bank = g->drv_bank;
357 			*reg = g->drv_reg;
358 		}
359 		*bit = g->schmitt_bit;
360 		*width = 1;
361 		break;
362 	case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
363 		*bank = g->drv_bank;
364 		*reg = g->drv_reg;
365 		*bit = g->lpmd_bit;
366 		*width = 2;
367 		break;
368 	case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
369 		*bank = g->drv_bank;
370 		*reg = g->drv_reg;
371 		*bit = g->drvdn_bit;
372 		*width = g->drvdn_width;
373 		break;
374 	case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
375 		*bank = g->drv_bank;
376 		*reg = g->drv_reg;
377 		*bit = g->drvup_bit;
378 		*width = g->drvup_width;
379 		break;
380 	case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
381 		*bank = g->drv_bank;
382 		*reg = g->drv_reg;
383 		*bit = g->slwf_bit;
384 		*width = g->slwf_width;
385 		break;
386 	case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
387 		*bank = g->drv_bank;
388 		*reg = g->drv_reg;
389 		*bit = g->slwr_bit;
390 		*width = g->slwr_width;
391 		break;
392 	case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
393 		if (pmx->soc->drvtype_in_mux) {
394 			*bank = g->mux_bank;
395 			*reg = g->mux_reg;
396 		} else {
397 			*bank = g->drv_bank;
398 			*reg = g->drv_reg;
399 		}
400 		*bit = g->drvtype_bit;
401 		*width = 2;
402 		break;
403 	default:
404 		dev_err(pmx->dev, "Invalid config param %04x\n", param);
405 		return -ENOTSUPP;
406 	}
407 
408 	if (*reg < 0 || *bit < 0)  {
409 		if (report_err) {
410 			const char *prop = "unknown";
411 			int i;
412 
413 			for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
414 				if (cfg_params[i].param == param) {
415 					prop = cfg_params[i].property;
416 					break;
417 				}
418 			}
419 
420 			dev_err(pmx->dev,
421 				"Config param %04x (%s) not supported on group %s\n",
422 				param, prop, g->name);
423 		}
424 		return -ENOTSUPP;
425 	}
426 
427 	return 0;
428 }
429 
430 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
431 			     unsigned pin, unsigned long *config)
432 {
433 	dev_err(pctldev->dev, "pin_config_get op not supported\n");
434 	return -ENOTSUPP;
435 }
436 
437 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
438 			     unsigned pin, unsigned long *configs,
439 			     unsigned num_configs)
440 {
441 	dev_err(pctldev->dev, "pin_config_set op not supported\n");
442 	return -ENOTSUPP;
443 }
444 
445 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
446 				   unsigned group, unsigned long *config)
447 {
448 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
449 	enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
450 	u16 arg;
451 	const struct tegra_pingroup *g;
452 	int ret;
453 	s8 bank, bit, width;
454 	s16 reg;
455 	u32 val, mask;
456 
457 	g = &pmx->soc->groups[group];
458 
459 	ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
460 				&width);
461 	if (ret < 0)
462 		return ret;
463 
464 	val = pmx_readl(pmx, bank, reg);
465 	mask = (1 << width) - 1;
466 	arg = (val >> bit) & mask;
467 
468 	*config = TEGRA_PINCONF_PACK(param, arg);
469 
470 	return 0;
471 }
472 
473 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
474 				   unsigned group, unsigned long *configs,
475 				   unsigned num_configs)
476 {
477 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
478 	enum tegra_pinconf_param param;
479 	u16 arg;
480 	const struct tegra_pingroup *g;
481 	int ret, i;
482 	s8 bank, bit, width;
483 	s16 reg;
484 	u32 val, mask;
485 
486 	g = &pmx->soc->groups[group];
487 
488 	for (i = 0; i < num_configs; i++) {
489 		param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
490 		arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
491 
492 		ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
493 					&width);
494 		if (ret < 0)
495 			return ret;
496 
497 		val = pmx_readl(pmx, bank, reg);
498 
499 		/* LOCK can't be cleared */
500 		if (param == TEGRA_PINCONF_PARAM_LOCK) {
501 			if ((val & BIT(bit)) && !arg) {
502 				dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
503 				return -EINVAL;
504 			}
505 		}
506 
507 		/* Special-case Boolean values; allow any non-zero as true */
508 		if (width == 1)
509 			arg = !!arg;
510 
511 		/* Range-check user-supplied value */
512 		mask = (1 << width) - 1;
513 		if (arg & ~mask) {
514 			dev_err(pctldev->dev,
515 				"config %lx: %x too big for %d bit register\n",
516 				configs[i], arg, width);
517 			return -EINVAL;
518 		}
519 
520 		/* Update register */
521 		val &= ~(mask << bit);
522 		val |= arg << bit;
523 		pmx_writel(pmx, val, bank, reg);
524 	} /* for each config */
525 
526 	return 0;
527 }
528 
529 #ifdef CONFIG_DEBUG_FS
530 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
531 				   struct seq_file *s, unsigned offset)
532 {
533 }
534 
535 static const char *strip_prefix(const char *s)
536 {
537 	const char *comma = strchr(s, ',');
538 	if (!comma)
539 		return s;
540 
541 	return comma + 1;
542 }
543 
544 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
545 					 struct seq_file *s, unsigned group)
546 {
547 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
548 	const struct tegra_pingroup *g;
549 	int i, ret;
550 	s8 bank, bit, width;
551 	s16 reg;
552 	u32 val;
553 
554 	g = &pmx->soc->groups[group];
555 
556 	for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
557 		ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
558 					&bank, &reg, &bit, &width);
559 		if (ret < 0)
560 			continue;
561 
562 		val = pmx_readl(pmx, bank, reg);
563 		val >>= bit;
564 		val &= (1 << width) - 1;
565 
566 		seq_printf(s, "\n\t%s=%u",
567 			   strip_prefix(cfg_params[i].property), val);
568 	}
569 }
570 
571 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
572 					  struct seq_file *s,
573 					  unsigned long config)
574 {
575 	enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
576 	u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
577 	const char *pname = "unknown";
578 	int i;
579 
580 	for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
581 		if (cfg_params[i].param == param) {
582 			pname = cfg_params[i].property;
583 			break;
584 		}
585 	}
586 
587 	seq_printf(s, "%s=%d", strip_prefix(pname), arg);
588 }
589 #endif
590 
591 static const struct pinconf_ops tegra_pinconf_ops = {
592 	.pin_config_get = tegra_pinconf_get,
593 	.pin_config_set = tegra_pinconf_set,
594 	.pin_config_group_get = tegra_pinconf_group_get,
595 	.pin_config_group_set = tegra_pinconf_group_set,
596 #ifdef CONFIG_DEBUG_FS
597 	.pin_config_dbg_show = tegra_pinconf_dbg_show,
598 	.pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
599 	.pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
600 #endif
601 };
602 
603 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
604 	.name = "Tegra GPIOs",
605 	.id = 0,
606 	.base = 0,
607 };
608 
609 static struct pinctrl_desc tegra_pinctrl_desc = {
610 	.pctlops = &tegra_pinctrl_ops,
611 	.pmxops = &tegra_pinmux_ops,
612 	.confops = &tegra_pinconf_ops,
613 	.owner = THIS_MODULE,
614 };
615 
616 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
617 {
618 	int i = 0;
619 	const struct tegra_pingroup *g;
620 	u32 val;
621 
622 	for (i = 0; i < pmx->soc->ngroups; ++i) {
623 		g = &pmx->soc->groups[i];
624 		if (g->parked_bit >= 0) {
625 			val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
626 			val &= ~(1 << g->parked_bit);
627 			pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
628 		}
629 	}
630 }
631 
632 static bool gpio_node_has_range(const char *compatible)
633 {
634 	struct device_node *np;
635 	bool has_prop = false;
636 
637 	np = of_find_compatible_node(NULL, NULL, compatible);
638 	if (!np)
639 		return has_prop;
640 
641 	has_prop = of_find_property(np, "gpio-ranges", NULL);
642 
643 	of_node_put(np);
644 
645 	return has_prop;
646 }
647 
648 int tegra_pinctrl_probe(struct platform_device *pdev,
649 			const struct tegra_pinctrl_soc_data *soc_data)
650 {
651 	struct tegra_pmx *pmx;
652 	struct resource *res;
653 	int i;
654 	const char **group_pins;
655 	int fn, gn, gfn;
656 
657 	pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
658 	if (!pmx)
659 		return -ENOMEM;
660 
661 	pmx->dev = &pdev->dev;
662 	pmx->soc = soc_data;
663 
664 	/*
665 	 * Each mux group will appear in 4 functions' list of groups.
666 	 * This over-allocates slightly, since not all groups are mux groups.
667 	 */
668 	pmx->group_pins = devm_kcalloc(&pdev->dev,
669 		soc_data->ngroups * 4, sizeof(*pmx->group_pins),
670 		GFP_KERNEL);
671 	if (!pmx->group_pins)
672 		return -ENOMEM;
673 
674 	group_pins = pmx->group_pins;
675 	for (fn = 0; fn < soc_data->nfunctions; fn++) {
676 		struct tegra_function *func = &soc_data->functions[fn];
677 
678 		func->groups = group_pins;
679 
680 		for (gn = 0; gn < soc_data->ngroups; gn++) {
681 			const struct tegra_pingroup *g = &soc_data->groups[gn];
682 
683 			if (g->mux_reg == -1)
684 				continue;
685 
686 			for (gfn = 0; gfn < 4; gfn++)
687 				if (g->funcs[gfn] == fn)
688 					break;
689 			if (gfn == 4)
690 				continue;
691 
692 			BUG_ON(group_pins - pmx->group_pins >=
693 				soc_data->ngroups * 4);
694 			*group_pins++ = g->name;
695 			func->ngroups++;
696 		}
697 	}
698 
699 	tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
700 	tegra_pinctrl_desc.name = dev_name(&pdev->dev);
701 	tegra_pinctrl_desc.pins = pmx->soc->pins;
702 	tegra_pinctrl_desc.npins = pmx->soc->npins;
703 
704 	for (i = 0; ; i++) {
705 		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
706 		if (!res)
707 			break;
708 	}
709 	pmx->nbanks = i;
710 
711 	pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
712 				 GFP_KERNEL);
713 	if (!pmx->regs)
714 		return -ENOMEM;
715 
716 	for (i = 0; i < pmx->nbanks; i++) {
717 		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
718 		pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
719 		if (IS_ERR(pmx->regs[i]))
720 			return PTR_ERR(pmx->regs[i]);
721 	}
722 
723 	pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
724 	if (IS_ERR(pmx->pctl)) {
725 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
726 		return PTR_ERR(pmx->pctl);
727 	}
728 
729 	tegra_pinctrl_clear_parked_bits(pmx);
730 
731 	if (!gpio_node_has_range(pmx->soc->gpio_compatible))
732 		pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
733 
734 	platform_set_drvdata(pdev, pmx);
735 
736 	dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
737 
738 	return 0;
739 }
740