1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the NVIDIA Tegra pinmux 4 * 5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. 6 * 7 * Derived from code: 8 * Copyright (C) 2010 Google, Inc. 9 * Copyright (C) 2010 NVIDIA Corporation 10 * Copyright (C) 2009-2011 ST-Ericsson AB 11 */ 12 13 #include <linux/err.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/seq_file.h> 19 #include <linux/slab.h> 20 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 26 #include "../core.h" 27 #include "../pinctrl-utils.h" 28 #include "pinctrl-tegra.h" 29 30 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) 31 { 32 return readl(pmx->regs[bank] + reg); 33 } 34 35 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) 36 { 37 writel_relaxed(val, pmx->regs[bank] + reg); 38 /* make sure pinmux register write completed */ 39 pmx_readl(pmx, bank, reg); 40 } 41 42 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 43 { 44 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 45 46 return pmx->soc->ngroups; 47 } 48 49 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 50 unsigned group) 51 { 52 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 53 54 return pmx->soc->groups[group].name; 55 } 56 57 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 58 unsigned group, 59 const unsigned **pins, 60 unsigned *num_pins) 61 { 62 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 63 64 *pins = pmx->soc->groups[group].pins; 65 *num_pins = pmx->soc->groups[group].npins; 66 67 return 0; 68 } 69 70 #ifdef CONFIG_DEBUG_FS 71 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, 72 struct seq_file *s, 73 unsigned offset) 74 { 75 seq_printf(s, " %s", dev_name(pctldev->dev)); 76 } 77 #endif 78 79 static const struct cfg_param { 80 const char *property; 81 enum tegra_pinconf_param param; 82 } cfg_params[] = { 83 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL}, 84 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE}, 85 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT}, 86 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN}, 87 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, 88 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, 89 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL}, 90 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL}, 91 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, 92 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, 93 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, 94 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH}, 95 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH}, 96 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, 97 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, 98 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE}, 99 }; 100 101 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 102 struct device_node *np, 103 struct pinctrl_map **map, 104 unsigned *reserved_maps, 105 unsigned *num_maps) 106 { 107 struct device *dev = pctldev->dev; 108 int ret, i; 109 const char *function; 110 u32 val; 111 unsigned long config; 112 unsigned long *configs = NULL; 113 unsigned num_configs = 0; 114 unsigned reserve; 115 struct property *prop; 116 const char *group; 117 118 ret = of_property_read_string(np, "nvidia,function", &function); 119 if (ret < 0) { 120 /* EINVAL=missing, which is fine since it's optional */ 121 if (ret != -EINVAL) 122 dev_err(dev, 123 "could not parse property nvidia,function\n"); 124 function = NULL; 125 } 126 127 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 128 ret = of_property_read_u32(np, cfg_params[i].property, &val); 129 if (!ret) { 130 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); 131 ret = pinctrl_utils_add_config(pctldev, &configs, 132 &num_configs, config); 133 if (ret < 0) 134 goto exit; 135 /* EINVAL=missing, which is fine since it's optional */ 136 } else if (ret != -EINVAL) { 137 dev_err(dev, "could not parse property %s\n", 138 cfg_params[i].property); 139 } 140 } 141 142 reserve = 0; 143 if (function != NULL) 144 reserve++; 145 if (num_configs) 146 reserve++; 147 ret = of_property_count_strings(np, "nvidia,pins"); 148 if (ret < 0) { 149 dev_err(dev, "could not parse property nvidia,pins\n"); 150 goto exit; 151 } 152 reserve *= ret; 153 154 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, 155 num_maps, reserve); 156 if (ret < 0) 157 goto exit; 158 159 of_property_for_each_string(np, "nvidia,pins", prop, group) { 160 if (function) { 161 ret = pinctrl_utils_add_map_mux(pctldev, map, 162 reserved_maps, num_maps, group, 163 function); 164 if (ret < 0) 165 goto exit; 166 } 167 168 if (num_configs) { 169 ret = pinctrl_utils_add_map_configs(pctldev, map, 170 reserved_maps, num_maps, group, 171 configs, num_configs, 172 PIN_MAP_TYPE_CONFIGS_GROUP); 173 if (ret < 0) 174 goto exit; 175 } 176 } 177 178 ret = 0; 179 180 exit: 181 kfree(configs); 182 return ret; 183 } 184 185 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 186 struct device_node *np_config, 187 struct pinctrl_map **map, 188 unsigned *num_maps) 189 { 190 unsigned reserved_maps; 191 struct device_node *np; 192 int ret; 193 194 reserved_maps = 0; 195 *map = NULL; 196 *num_maps = 0; 197 198 for_each_child_of_node(np_config, np) { 199 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map, 200 &reserved_maps, num_maps); 201 if (ret < 0) { 202 pinctrl_utils_free_map(pctldev, *map, 203 *num_maps); 204 of_node_put(np); 205 return ret; 206 } 207 } 208 209 return 0; 210 } 211 212 static const struct pinctrl_ops tegra_pinctrl_ops = { 213 .get_groups_count = tegra_pinctrl_get_groups_count, 214 .get_group_name = tegra_pinctrl_get_group_name, 215 .get_group_pins = tegra_pinctrl_get_group_pins, 216 #ifdef CONFIG_DEBUG_FS 217 .pin_dbg_show = tegra_pinctrl_pin_dbg_show, 218 #endif 219 .dt_node_to_map = tegra_pinctrl_dt_node_to_map, 220 .dt_free_map = pinctrl_utils_free_map, 221 }; 222 223 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) 224 { 225 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 226 227 return pmx->soc->nfunctions; 228 } 229 230 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 231 unsigned function) 232 { 233 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 234 235 return pmx->functions[function].name; 236 } 237 238 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, 239 unsigned function, 240 const char * const **groups, 241 unsigned * const num_groups) 242 { 243 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 244 245 *groups = pmx->functions[function].groups; 246 *num_groups = pmx->functions[function].ngroups; 247 248 return 0; 249 } 250 251 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev, 252 unsigned function, 253 unsigned group) 254 { 255 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 256 const struct tegra_pingroup *g; 257 int i; 258 u32 val; 259 260 g = &pmx->soc->groups[group]; 261 262 if (WARN_ON(g->mux_reg < 0)) 263 return -EINVAL; 264 265 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { 266 if (g->funcs[i] == function) 267 break; 268 } 269 if (WARN_ON(i == ARRAY_SIZE(g->funcs))) 270 return -EINVAL; 271 272 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 273 val &= ~(0x3 << g->mux_bit); 274 val |= i << g->mux_bit; 275 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); 276 277 return 0; 278 } 279 280 static const struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctldev, 281 unsigned int offset) 282 { 283 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 284 unsigned int group, num_pins, j; 285 const unsigned int *pins; 286 int ret; 287 288 for (group = 0; group < pmx->soc->ngroups; ++group) { 289 ret = tegra_pinctrl_get_group_pins(pctldev, group, &pins, &num_pins); 290 if (ret < 0) 291 continue; 292 for (j = 0; j < num_pins; j++) { 293 if (offset == pins[j]) 294 return &pmx->soc->groups[group]; 295 } 296 } 297 298 dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset); 299 return NULL; 300 } 301 302 static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, 303 struct pinctrl_gpio_range *range, 304 unsigned int offset) 305 { 306 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 307 const struct tegra_pingroup *group; 308 u32 value; 309 310 if (!pmx->soc->sfsel_in_mux) 311 return 0; 312 313 group = tegra_pinctrl_get_group(pctldev, offset); 314 315 if (!group) 316 return -EINVAL; 317 318 if (group->mux_reg < 0 || group->sfsel_bit < 0) 319 return -EINVAL; 320 321 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); 322 value &= ~BIT(group->sfsel_bit); 323 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); 324 325 return 0; 326 } 327 328 static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, 329 struct pinctrl_gpio_range *range, 330 unsigned int offset) 331 { 332 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 333 const struct tegra_pingroup *group; 334 u32 value; 335 336 if (!pmx->soc->sfsel_in_mux) 337 return; 338 339 group = tegra_pinctrl_get_group(pctldev, offset); 340 341 if (!group) 342 return; 343 344 if (group->mux_reg < 0 || group->sfsel_bit < 0) 345 return; 346 347 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); 348 value |= BIT(group->sfsel_bit); 349 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); 350 } 351 352 static const struct pinmux_ops tegra_pinmux_ops = { 353 .get_functions_count = tegra_pinctrl_get_funcs_count, 354 .get_function_name = tegra_pinctrl_get_func_name, 355 .get_function_groups = tegra_pinctrl_get_func_groups, 356 .set_mux = tegra_pinctrl_set_mux, 357 .gpio_request_enable = tegra_pinctrl_gpio_request_enable, 358 .gpio_disable_free = tegra_pinctrl_gpio_disable_free, 359 }; 360 361 static int tegra_pinconf_reg(struct tegra_pmx *pmx, 362 const struct tegra_pingroup *g, 363 enum tegra_pinconf_param param, 364 bool report_err, 365 s8 *bank, s32 *reg, s8 *bit, s8 *width) 366 { 367 switch (param) { 368 case TEGRA_PINCONF_PARAM_PULL: 369 *bank = g->pupd_bank; 370 *reg = g->pupd_reg; 371 *bit = g->pupd_bit; 372 *width = 2; 373 break; 374 case TEGRA_PINCONF_PARAM_TRISTATE: 375 *bank = g->tri_bank; 376 *reg = g->tri_reg; 377 *bit = g->tri_bit; 378 *width = 1; 379 break; 380 case TEGRA_PINCONF_PARAM_ENABLE_INPUT: 381 *bank = g->mux_bank; 382 *reg = g->mux_reg; 383 *bit = g->einput_bit; 384 *width = 1; 385 break; 386 case TEGRA_PINCONF_PARAM_OPEN_DRAIN: 387 *bank = g->mux_bank; 388 *reg = g->mux_reg; 389 *bit = g->odrain_bit; 390 *width = 1; 391 break; 392 case TEGRA_PINCONF_PARAM_LOCK: 393 *bank = g->mux_bank; 394 *reg = g->mux_reg; 395 *bit = g->lock_bit; 396 *width = 1; 397 break; 398 case TEGRA_PINCONF_PARAM_IORESET: 399 *bank = g->mux_bank; 400 *reg = g->mux_reg; 401 *bit = g->ioreset_bit; 402 *width = 1; 403 break; 404 case TEGRA_PINCONF_PARAM_RCV_SEL: 405 *bank = g->mux_bank; 406 *reg = g->mux_reg; 407 *bit = g->rcv_sel_bit; 408 *width = 1; 409 break; 410 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE: 411 if (pmx->soc->hsm_in_mux) { 412 *bank = g->mux_bank; 413 *reg = g->mux_reg; 414 } else { 415 *bank = g->drv_bank; 416 *reg = g->drv_reg; 417 } 418 *bit = g->hsm_bit; 419 *width = 1; 420 break; 421 case TEGRA_PINCONF_PARAM_SCHMITT: 422 if (pmx->soc->schmitt_in_mux) { 423 *bank = g->mux_bank; 424 *reg = g->mux_reg; 425 } else { 426 *bank = g->drv_bank; 427 *reg = g->drv_reg; 428 } 429 *bit = g->schmitt_bit; 430 *width = 1; 431 break; 432 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE: 433 *bank = g->drv_bank; 434 *reg = g->drv_reg; 435 *bit = g->lpmd_bit; 436 *width = 2; 437 break; 438 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH: 439 *bank = g->drv_bank; 440 *reg = g->drv_reg; 441 *bit = g->drvdn_bit; 442 *width = g->drvdn_width; 443 break; 444 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH: 445 *bank = g->drv_bank; 446 *reg = g->drv_reg; 447 *bit = g->drvup_bit; 448 *width = g->drvup_width; 449 break; 450 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING: 451 *bank = g->drv_bank; 452 *reg = g->drv_reg; 453 *bit = g->slwf_bit; 454 *width = g->slwf_width; 455 break; 456 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING: 457 *bank = g->drv_bank; 458 *reg = g->drv_reg; 459 *bit = g->slwr_bit; 460 *width = g->slwr_width; 461 break; 462 case TEGRA_PINCONF_PARAM_DRIVE_TYPE: 463 if (pmx->soc->drvtype_in_mux) { 464 *bank = g->mux_bank; 465 *reg = g->mux_reg; 466 } else { 467 *bank = g->drv_bank; 468 *reg = g->drv_reg; 469 } 470 *bit = g->drvtype_bit; 471 *width = 2; 472 break; 473 default: 474 dev_err(pmx->dev, "Invalid config param %04x\n", param); 475 return -ENOTSUPP; 476 } 477 478 if (*reg < 0 || *bit < 0) { 479 if (report_err) { 480 const char *prop = "unknown"; 481 int i; 482 483 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 484 if (cfg_params[i].param == param) { 485 prop = cfg_params[i].property; 486 break; 487 } 488 } 489 490 dev_err(pmx->dev, 491 "Config param %04x (%s) not supported on group %s\n", 492 param, prop, g->name); 493 } 494 return -ENOTSUPP; 495 } 496 497 return 0; 498 } 499 500 static int tegra_pinconf_get(struct pinctrl_dev *pctldev, 501 unsigned pin, unsigned long *config) 502 { 503 dev_err(pctldev->dev, "pin_config_get op not supported\n"); 504 return -ENOTSUPP; 505 } 506 507 static int tegra_pinconf_set(struct pinctrl_dev *pctldev, 508 unsigned pin, unsigned long *configs, 509 unsigned num_configs) 510 { 511 dev_err(pctldev->dev, "pin_config_set op not supported\n"); 512 return -ENOTSUPP; 513 } 514 515 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, 516 unsigned group, unsigned long *config) 517 { 518 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 519 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config); 520 u16 arg; 521 const struct tegra_pingroup *g; 522 int ret; 523 s8 bank, bit, width; 524 s32 reg; 525 u32 val, mask; 526 527 g = &pmx->soc->groups[group]; 528 529 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, 530 &width); 531 if (ret < 0) 532 return ret; 533 534 val = pmx_readl(pmx, bank, reg); 535 mask = (1 << width) - 1; 536 arg = (val >> bit) & mask; 537 538 *config = TEGRA_PINCONF_PACK(param, arg); 539 540 return 0; 541 } 542 543 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, 544 unsigned group, unsigned long *configs, 545 unsigned num_configs) 546 { 547 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 548 enum tegra_pinconf_param param; 549 u16 arg; 550 const struct tegra_pingroup *g; 551 int ret, i; 552 s8 bank, bit, width; 553 s32 reg; 554 u32 val, mask; 555 556 g = &pmx->soc->groups[group]; 557 558 for (i = 0; i < num_configs; i++) { 559 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]); 560 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]); 561 562 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, 563 &width); 564 if (ret < 0) 565 return ret; 566 567 val = pmx_readl(pmx, bank, reg); 568 569 /* LOCK can't be cleared */ 570 if (param == TEGRA_PINCONF_PARAM_LOCK) { 571 if ((val & BIT(bit)) && !arg) { 572 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); 573 return -EINVAL; 574 } 575 } 576 577 /* Special-case Boolean values; allow any non-zero as true */ 578 if (width == 1) 579 arg = !!arg; 580 581 /* Range-check user-supplied value */ 582 mask = (1 << width) - 1; 583 if (arg & ~mask) { 584 dev_err(pctldev->dev, 585 "config %lx: %x too big for %d bit register\n", 586 configs[i], arg, width); 587 return -EINVAL; 588 } 589 590 /* Update register */ 591 val &= ~(mask << bit); 592 val |= arg << bit; 593 pmx_writel(pmx, val, bank, reg); 594 } /* for each config */ 595 596 return 0; 597 } 598 599 #ifdef CONFIG_DEBUG_FS 600 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, 601 struct seq_file *s, unsigned offset) 602 { 603 } 604 605 static const char *strip_prefix(const char *s) 606 { 607 const char *comma = strchr(s, ','); 608 if (!comma) 609 return s; 610 611 return comma + 1; 612 } 613 614 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 615 struct seq_file *s, unsigned group) 616 { 617 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 618 const struct tegra_pingroup *g; 619 int i, ret; 620 s8 bank, bit, width; 621 s32 reg; 622 u32 val; 623 624 g = &pmx->soc->groups[group]; 625 626 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 627 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false, 628 &bank, ®, &bit, &width); 629 if (ret < 0) 630 continue; 631 632 val = pmx_readl(pmx, bank, reg); 633 val >>= bit; 634 val &= (1 << width) - 1; 635 636 seq_printf(s, "\n\t%s=%u", 637 strip_prefix(cfg_params[i].property), val); 638 } 639 } 640 641 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, 642 struct seq_file *s, 643 unsigned long config) 644 { 645 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config); 646 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config); 647 const char *pname = "unknown"; 648 int i; 649 650 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 651 if (cfg_params[i].param == param) { 652 pname = cfg_params[i].property; 653 break; 654 } 655 } 656 657 seq_printf(s, "%s=%d", strip_prefix(pname), arg); 658 } 659 #endif 660 661 static const struct pinconf_ops tegra_pinconf_ops = { 662 .pin_config_get = tegra_pinconf_get, 663 .pin_config_set = tegra_pinconf_set, 664 .pin_config_group_get = tegra_pinconf_group_get, 665 .pin_config_group_set = tegra_pinconf_group_set, 666 #ifdef CONFIG_DEBUG_FS 667 .pin_config_dbg_show = tegra_pinconf_dbg_show, 668 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, 669 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show, 670 #endif 671 }; 672 673 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) 674 { 675 int i = 0; 676 const struct tegra_pingroup *g; 677 u32 val; 678 679 for (i = 0; i < pmx->soc->ngroups; ++i) { 680 g = &pmx->soc->groups[i]; 681 if (g->parked_bitmask > 0) { 682 unsigned int bank, reg; 683 684 if (g->mux_reg != -1) { 685 bank = g->mux_bank; 686 reg = g->mux_reg; 687 } else { 688 bank = g->drv_bank; 689 reg = g->drv_reg; 690 } 691 692 val = pmx_readl(pmx, bank, reg); 693 val &= ~g->parked_bitmask; 694 pmx_writel(pmx, val, bank, reg); 695 } 696 } 697 } 698 699 static size_t tegra_pinctrl_get_bank_size(struct device *dev, 700 unsigned int bank_id) 701 { 702 struct platform_device *pdev = to_platform_device(dev); 703 struct resource *res; 704 705 res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id); 706 707 return resource_size(res) / 4; 708 } 709 710 static int tegra_pinctrl_suspend(struct device *dev) 711 { 712 struct tegra_pmx *pmx = dev_get_drvdata(dev); 713 u32 *backup_regs = pmx->backup_regs; 714 u32 __iomem *regs; 715 size_t bank_size; 716 unsigned int i, k; 717 718 for (i = 0; i < pmx->nbanks; i++) { 719 bank_size = tegra_pinctrl_get_bank_size(dev, i); 720 regs = pmx->regs[i]; 721 for (k = 0; k < bank_size; k++) 722 *backup_regs++ = readl_relaxed(regs++); 723 } 724 725 return pinctrl_force_sleep(pmx->pctl); 726 } 727 728 static int tegra_pinctrl_resume(struct device *dev) 729 { 730 struct tegra_pmx *pmx = dev_get_drvdata(dev); 731 u32 *backup_regs = pmx->backup_regs; 732 u32 __iomem *regs; 733 size_t bank_size; 734 unsigned int i, k; 735 736 for (i = 0; i < pmx->nbanks; i++) { 737 bank_size = tegra_pinctrl_get_bank_size(dev, i); 738 regs = pmx->regs[i]; 739 for (k = 0; k < bank_size; k++) 740 writel_relaxed(*backup_regs++, regs++); 741 } 742 743 /* flush all the prior writes */ 744 readl_relaxed(pmx->regs[0]); 745 /* wait for pinctrl register read to complete */ 746 rmb(); 747 return 0; 748 } 749 750 DEFINE_NOIRQ_DEV_PM_OPS(tegra_pinctrl_pm, tegra_pinctrl_suspend, tegra_pinctrl_resume); 751 752 static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx) 753 { 754 struct device_node *np; 755 bool has_prop = false; 756 757 np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible); 758 if (!np) 759 return has_prop; 760 761 has_prop = of_find_property(np, "gpio-ranges", NULL); 762 763 of_node_put(np); 764 765 return has_prop; 766 } 767 768 int tegra_pinctrl_probe(struct platform_device *pdev, 769 const struct tegra_pinctrl_soc_data *soc_data) 770 { 771 struct tegra_pmx *pmx; 772 struct resource *res; 773 int i; 774 const char **group_pins; 775 int fn, gn, gfn; 776 unsigned long backup_regs_size = 0; 777 778 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 779 if (!pmx) 780 return -ENOMEM; 781 782 pmx->dev = &pdev->dev; 783 pmx->soc = soc_data; 784 785 /* 786 * Each mux group will appear in 4 functions' list of groups. 787 * This over-allocates slightly, since not all groups are mux groups. 788 */ 789 pmx->group_pins = devm_kcalloc(&pdev->dev, pmx->soc->ngroups * 4, 790 sizeof(*pmx->group_pins), GFP_KERNEL); 791 if (!pmx->group_pins) 792 return -ENOMEM; 793 794 pmx->functions = devm_kcalloc(&pdev->dev, pmx->soc->nfunctions, 795 sizeof(*pmx->functions), GFP_KERNEL); 796 if (!pmx->functions) 797 return -ENOMEM; 798 799 group_pins = pmx->group_pins; 800 801 for (fn = 0; fn < pmx->soc->nfunctions; fn++) { 802 struct tegra_function *func = &pmx->functions[fn]; 803 804 func->name = pmx->soc->functions[fn]; 805 func->groups = group_pins; 806 807 for (gn = 0; gn < pmx->soc->ngroups; gn++) { 808 const struct tegra_pingroup *g = &pmx->soc->groups[gn]; 809 810 if (g->mux_reg == -1) 811 continue; 812 813 for (gfn = 0; gfn < 4; gfn++) 814 if (g->funcs[gfn] == fn) 815 break; 816 if (gfn == 4) 817 continue; 818 819 BUG_ON(group_pins - pmx->group_pins >= 820 pmx->soc->ngroups * 4); 821 *group_pins++ = g->name; 822 func->ngroups++; 823 } 824 } 825 826 pmx->gpio_range.name = "Tegra GPIOs"; 827 pmx->gpio_range.id = 0; 828 pmx->gpio_range.base = 0; 829 pmx->gpio_range.npins = pmx->soc->ngpios; 830 831 pmx->desc.pctlops = &tegra_pinctrl_ops; 832 pmx->desc.pmxops = &tegra_pinmux_ops; 833 pmx->desc.confops = &tegra_pinconf_ops; 834 pmx->desc.owner = THIS_MODULE; 835 pmx->desc.name = dev_name(&pdev->dev); 836 pmx->desc.pins = pmx->soc->pins; 837 pmx->desc.npins = pmx->soc->npins; 838 839 for (i = 0; ; i++) { 840 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 841 if (!res) 842 break; 843 backup_regs_size += resource_size(res); 844 } 845 pmx->nbanks = i; 846 847 pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs), 848 GFP_KERNEL); 849 if (!pmx->regs) 850 return -ENOMEM; 851 852 pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size, 853 GFP_KERNEL); 854 if (!pmx->backup_regs) 855 return -ENOMEM; 856 857 for (i = 0; i < pmx->nbanks; i++) { 858 pmx->regs[i] = devm_platform_ioremap_resource(pdev, i); 859 if (IS_ERR(pmx->regs[i])) 860 return PTR_ERR(pmx->regs[i]); 861 } 862 863 pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx); 864 if (IS_ERR(pmx->pctl)) { 865 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 866 return PTR_ERR(pmx->pctl); 867 } 868 869 tegra_pinctrl_clear_parked_bits(pmx); 870 871 if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx)) 872 pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range); 873 874 platform_set_drvdata(pdev, pmx); 875 876 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n"); 877 878 return 0; 879 } 880