1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #ifndef __PINCTRL_SUNXI_H 14 #define __PINCTRL_SUNXI_H 15 16 #include <linux/kernel.h> 17 #include <linux/spinlock.h> 18 19 #define PA_BASE 0 20 #define PB_BASE 32 21 #define PC_BASE 64 22 #define PD_BASE 96 23 #define PE_BASE 128 24 #define PF_BASE 160 25 #define PG_BASE 192 26 #define PH_BASE 224 27 #define PI_BASE 256 28 #define PL_BASE 352 29 #define PM_BASE 384 30 #define PN_BASE 416 31 32 #define SUNXI_PINCTRL_PIN(bank, pin) \ 33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin) 34 35 #define SUNXI_PIN_NAME_MAX_LEN 5 36 37 #define BANK_MEM_SIZE 0x24 38 #define MUX_REGS_OFFSET 0x0 39 #define DATA_REGS_OFFSET 0x10 40 #define DLEVEL_REGS_OFFSET 0x14 41 #define PULL_REGS_OFFSET 0x1c 42 43 #define PINS_PER_BANK 32 44 #define MUX_PINS_PER_REG 8 45 #define MUX_PINS_BITS 4 46 #define MUX_PINS_MASK 0x0f 47 #define DATA_PINS_PER_REG 32 48 #define DATA_PINS_BITS 1 49 #define DATA_PINS_MASK 0x01 50 #define DLEVEL_PINS_PER_REG 16 51 #define DLEVEL_PINS_BITS 2 52 #define DLEVEL_PINS_MASK 0x03 53 #define PULL_PINS_PER_REG 16 54 #define PULL_PINS_BITS 2 55 #define PULL_PINS_MASK 0x03 56 57 #define IRQ_PER_BANK 32 58 59 #define IRQ_CFG_REG 0x200 60 #define IRQ_CFG_IRQ_PER_REG 8 61 #define IRQ_CFG_IRQ_BITS 4 62 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1) 63 #define IRQ_CTRL_REG 0x210 64 #define IRQ_CTRL_IRQ_PER_REG 32 65 #define IRQ_CTRL_IRQ_BITS 1 66 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1) 67 #define IRQ_STATUS_REG 0x214 68 #define IRQ_STATUS_IRQ_PER_REG 32 69 #define IRQ_STATUS_IRQ_BITS 1 70 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) 71 72 #define IRQ_DEBOUNCE_REG 0x218 73 74 #define IRQ_MEM_SIZE 0x20 75 76 #define IRQ_EDGE_RISING 0x00 77 #define IRQ_EDGE_FALLING 0x01 78 #define IRQ_LEVEL_HIGH 0x02 79 #define IRQ_LEVEL_LOW 0x03 80 #define IRQ_EDGE_BOTH 0x04 81 82 #define SUN4I_FUNC_INPUT 0 83 #define SUN4I_FUNC_IRQ 6 84 85 struct sunxi_desc_function { 86 const char *name; 87 u8 muxval; 88 u8 irqbank; 89 u8 irqnum; 90 }; 91 92 struct sunxi_desc_pin { 93 struct pinctrl_pin_desc pin; 94 struct sunxi_desc_function *functions; 95 }; 96 97 struct sunxi_pinctrl_desc { 98 const struct sunxi_desc_pin *pins; 99 int npins; 100 unsigned pin_base; 101 unsigned irq_banks; 102 unsigned irq_bank_base; 103 bool irq_read_needs_mux; 104 }; 105 106 struct sunxi_pinctrl_function { 107 const char *name; 108 const char **groups; 109 unsigned ngroups; 110 }; 111 112 struct sunxi_pinctrl_group { 113 const char *name; 114 unsigned pin; 115 }; 116 117 struct sunxi_pinctrl { 118 void __iomem *membase; 119 struct gpio_chip *chip; 120 const struct sunxi_pinctrl_desc *desc; 121 struct device *dev; 122 struct irq_domain *domain; 123 struct sunxi_pinctrl_function *functions; 124 unsigned nfunctions; 125 struct sunxi_pinctrl_group *groups; 126 unsigned ngroups; 127 int *irq; 128 unsigned *irq_array; 129 spinlock_t lock; 130 struct pinctrl_dev *pctl_dev; 131 }; 132 133 #define SUNXI_PIN(_pin, ...) \ 134 { \ 135 .pin = _pin, \ 136 .functions = (struct sunxi_desc_function[]){ \ 137 __VA_ARGS__, { } }, \ 138 } 139 140 #define SUNXI_FUNCTION(_val, _name) \ 141 { \ 142 .name = _name, \ 143 .muxval = _val, \ 144 } 145 146 #define SUNXI_FUNCTION_IRQ(_val, _irq) \ 147 { \ 148 .name = "irq", \ 149 .muxval = _val, \ 150 .irqnum = _irq, \ 151 } 152 153 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ 154 { \ 155 .name = "irq", \ 156 .muxval = _val, \ 157 .irqbank = _bank, \ 158 .irqnum = _irq, \ 159 } 160 161 /* 162 * The sunXi PIO registers are organized as is: 163 * 0x00 - 0x0c Muxing values. 164 * 8 pins per register, each pin having a 4bits value 165 * 0x10 Pin values 166 * 32 bits per register, each pin corresponding to one bit 167 * 0x14 - 0x18 Drive level 168 * 16 pins per register, each pin having a 2bits value 169 * 0x1c - 0x20 Pull-Up values 170 * 16 pins per register, each pin having a 2bits value 171 * 172 * This is for the first bank. Each bank will have the same layout, 173 * with an offset being a multiple of 0x24. 174 * 175 * The following functions calculate from the pin number the register 176 * and the bit offset that we should access. 177 */ 178 static inline u32 sunxi_mux_reg(u16 pin) 179 { 180 u8 bank = pin / PINS_PER_BANK; 181 u32 offset = bank * BANK_MEM_SIZE; 182 offset += MUX_REGS_OFFSET; 183 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04; 184 return round_down(offset, 4); 185 } 186 187 static inline u32 sunxi_mux_offset(u16 pin) 188 { 189 u32 pin_num = pin % MUX_PINS_PER_REG; 190 return pin_num * MUX_PINS_BITS; 191 } 192 193 static inline u32 sunxi_data_reg(u16 pin) 194 { 195 u8 bank = pin / PINS_PER_BANK; 196 u32 offset = bank * BANK_MEM_SIZE; 197 offset += DATA_REGS_OFFSET; 198 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04; 199 return round_down(offset, 4); 200 } 201 202 static inline u32 sunxi_data_offset(u16 pin) 203 { 204 u32 pin_num = pin % DATA_PINS_PER_REG; 205 return pin_num * DATA_PINS_BITS; 206 } 207 208 static inline u32 sunxi_dlevel_reg(u16 pin) 209 { 210 u8 bank = pin / PINS_PER_BANK; 211 u32 offset = bank * BANK_MEM_SIZE; 212 offset += DLEVEL_REGS_OFFSET; 213 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04; 214 return round_down(offset, 4); 215 } 216 217 static inline u32 sunxi_dlevel_offset(u16 pin) 218 { 219 u32 pin_num = pin % DLEVEL_PINS_PER_REG; 220 return pin_num * DLEVEL_PINS_BITS; 221 } 222 223 static inline u32 sunxi_pull_reg(u16 pin) 224 { 225 u8 bank = pin / PINS_PER_BANK; 226 u32 offset = bank * BANK_MEM_SIZE; 227 offset += PULL_REGS_OFFSET; 228 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04; 229 return round_down(offset, 4); 230 } 231 232 static inline u32 sunxi_pull_offset(u16 pin) 233 { 234 u32 pin_num = pin % PULL_PINS_PER_REG; 235 return pin_num * PULL_PINS_BITS; 236 } 237 238 static inline u32 sunxi_irq_cfg_reg(u16 irq, unsigned bank_base) 239 { 240 u8 bank = irq / IRQ_PER_BANK; 241 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; 242 243 return IRQ_CFG_REG + (bank_base + bank) * IRQ_MEM_SIZE + reg; 244 } 245 246 static inline u32 sunxi_irq_cfg_offset(u16 irq) 247 { 248 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG; 249 return irq_num * IRQ_CFG_IRQ_BITS; 250 } 251 252 static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank, unsigned bank_base) 253 { 254 return IRQ_CTRL_REG + (bank_base + bank) * IRQ_MEM_SIZE; 255 } 256 257 static inline u32 sunxi_irq_ctrl_reg(u16 irq, unsigned bank_base) 258 { 259 u8 bank = irq / IRQ_PER_BANK; 260 261 return sunxi_irq_ctrl_reg_from_bank(bank, bank_base); 262 } 263 264 static inline u32 sunxi_irq_ctrl_offset(u16 irq) 265 { 266 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG; 267 return irq_num * IRQ_CTRL_IRQ_BITS; 268 } 269 270 static inline u32 sunxi_irq_debounce_reg_from_bank(u8 bank, unsigned bank_base) 271 { 272 return IRQ_DEBOUNCE_REG + (bank_base + bank) * IRQ_MEM_SIZE; 273 } 274 275 static inline u32 sunxi_irq_status_reg_from_bank(u8 bank, unsigned bank_base) 276 { 277 return IRQ_STATUS_REG + (bank_base + bank) * IRQ_MEM_SIZE; 278 } 279 280 static inline u32 sunxi_irq_status_reg(u16 irq, unsigned bank_base) 281 { 282 u8 bank = irq / IRQ_PER_BANK; 283 284 return sunxi_irq_status_reg_from_bank(bank, bank_base); 285 } 286 287 static inline u32 sunxi_irq_status_offset(u16 irq) 288 { 289 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG; 290 return irq_num * IRQ_STATUS_IRQ_BITS; 291 } 292 293 int sunxi_pinctrl_init(struct platform_device *pdev, 294 const struct sunxi_pinctrl_desc *desc); 295 296 #endif /* __PINCTRL_SUNXI_H */ 297