1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #ifndef __PINCTRL_SUNXI_H 14 #define __PINCTRL_SUNXI_H 15 16 #include <linux/kernel.h> 17 #include <linux/spinlock.h> 18 19 #define PA_BASE 0 20 #define PB_BASE 32 21 #define PC_BASE 64 22 #define PD_BASE 96 23 #define PE_BASE 128 24 #define PF_BASE 160 25 #define PG_BASE 192 26 #define PH_BASE 224 27 #define PI_BASE 256 28 #define PL_BASE 352 29 #define PM_BASE 384 30 #define PN_BASE 416 31 32 #define SUNXI_PINCTRL_PIN(bank, pin) \ 33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin) 34 35 #define SUNXI_PIN_NAME_MAX_LEN 5 36 37 #define BANK_MEM_SIZE 0x24 38 #define MUX_REGS_OFFSET 0x0 39 #define DATA_REGS_OFFSET 0x10 40 #define DLEVEL_REGS_OFFSET 0x14 41 #define PULL_REGS_OFFSET 0x1c 42 43 #define PINS_PER_BANK 32 44 #define MUX_PINS_PER_REG 8 45 #define MUX_PINS_BITS 4 46 #define MUX_PINS_MASK 0x0f 47 #define DATA_PINS_PER_REG 32 48 #define DATA_PINS_BITS 1 49 #define DATA_PINS_MASK 0x01 50 #define DLEVEL_PINS_PER_REG 16 51 #define DLEVEL_PINS_BITS 2 52 #define DLEVEL_PINS_MASK 0x03 53 #define PULL_PINS_PER_REG 16 54 #define PULL_PINS_BITS 2 55 #define PULL_PINS_MASK 0x03 56 57 #define IRQ_PER_BANK 32 58 59 #define IRQ_CFG_REG 0x200 60 #define IRQ_CFG_IRQ_PER_REG 8 61 #define IRQ_CFG_IRQ_BITS 4 62 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1) 63 #define IRQ_CTRL_REG 0x210 64 #define IRQ_CTRL_IRQ_PER_REG 32 65 #define IRQ_CTRL_IRQ_BITS 1 66 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1) 67 #define IRQ_STATUS_REG 0x214 68 #define IRQ_STATUS_IRQ_PER_REG 32 69 #define IRQ_STATUS_IRQ_BITS 1 70 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) 71 72 #define IRQ_DEBOUNCE_REG 0x218 73 74 #define IRQ_MEM_SIZE 0x20 75 76 #define IRQ_EDGE_RISING 0x00 77 #define IRQ_EDGE_FALLING 0x01 78 #define IRQ_LEVEL_HIGH 0x02 79 #define IRQ_LEVEL_LOW 0x03 80 #define IRQ_EDGE_BOTH 0x04 81 82 #define GRP_CFG_REG 0x300 83 84 #define IO_BIAS_MASK GENMASK(3, 0) 85 86 #define SUN4I_FUNC_INPUT 0 87 #define SUN4I_FUNC_IRQ 6 88 89 #define PINCTRL_SUN5I_A10S BIT(1) 90 #define PINCTRL_SUN5I_A13 BIT(2) 91 #define PINCTRL_SUN5I_GR8 BIT(3) 92 #define PINCTRL_SUN6I_A31 BIT(4) 93 #define PINCTRL_SUN6I_A31S BIT(5) 94 #define PINCTRL_SUN4I_A10 BIT(6) 95 #define PINCTRL_SUN7I_A20 BIT(7) 96 #define PINCTRL_SUN8I_R40 BIT(8) 97 98 struct sunxi_desc_function { 99 unsigned long variant; 100 const char *name; 101 u8 muxval; 102 u8 irqbank; 103 u8 irqnum; 104 }; 105 106 struct sunxi_desc_pin { 107 struct pinctrl_pin_desc pin; 108 unsigned long variant; 109 struct sunxi_desc_function *functions; 110 }; 111 112 struct sunxi_pinctrl_desc { 113 const struct sunxi_desc_pin *pins; 114 int npins; 115 unsigned pin_base; 116 unsigned irq_banks; 117 const unsigned int *irq_bank_map; 118 bool irq_read_needs_mux; 119 bool disable_strict_mode; 120 bool has_io_bias_cfg; 121 }; 122 123 struct sunxi_pinctrl_function { 124 const char *name; 125 const char **groups; 126 unsigned ngroups; 127 }; 128 129 struct sunxi_pinctrl_group { 130 const char *name; 131 unsigned pin; 132 }; 133 134 struct sunxi_pinctrl_regulator { 135 struct regulator *regulator; 136 refcount_t refcount; 137 }; 138 139 struct sunxi_pinctrl { 140 void __iomem *membase; 141 struct gpio_chip *chip; 142 const struct sunxi_pinctrl_desc *desc; 143 struct device *dev; 144 struct sunxi_pinctrl_regulator regulators[9]; 145 struct irq_domain *domain; 146 struct sunxi_pinctrl_function *functions; 147 unsigned nfunctions; 148 struct sunxi_pinctrl_group *groups; 149 unsigned ngroups; 150 int *irq; 151 unsigned *irq_array; 152 raw_spinlock_t lock; 153 struct pinctrl_dev *pctl_dev; 154 unsigned long variant; 155 }; 156 157 #define SUNXI_PIN(_pin, ...) \ 158 { \ 159 .pin = _pin, \ 160 .functions = (struct sunxi_desc_function[]){ \ 161 __VA_ARGS__, { } }, \ 162 } 163 164 #define SUNXI_PIN_VARIANT(_pin, _variant, ...) \ 165 { \ 166 .pin = _pin, \ 167 .variant = _variant, \ 168 .functions = (struct sunxi_desc_function[]){ \ 169 __VA_ARGS__, { } }, \ 170 } 171 172 #define SUNXI_FUNCTION(_val, _name) \ 173 { \ 174 .name = _name, \ 175 .muxval = _val, \ 176 } 177 178 #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \ 179 { \ 180 .name = _name, \ 181 .muxval = _val, \ 182 .variant = _variant, \ 183 } 184 185 #define SUNXI_FUNCTION_IRQ(_val, _irq) \ 186 { \ 187 .name = "irq", \ 188 .muxval = _val, \ 189 .irqnum = _irq, \ 190 } 191 192 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ 193 { \ 194 .name = "irq", \ 195 .muxval = _val, \ 196 .irqbank = _bank, \ 197 .irqnum = _irq, \ 198 } 199 200 /* 201 * The sunXi PIO registers are organized as is: 202 * 0x00 - 0x0c Muxing values. 203 * 8 pins per register, each pin having a 4bits value 204 * 0x10 Pin values 205 * 32 bits per register, each pin corresponding to one bit 206 * 0x14 - 0x18 Drive level 207 * 16 pins per register, each pin having a 2bits value 208 * 0x1c - 0x20 Pull-Up values 209 * 16 pins per register, each pin having a 2bits value 210 * 211 * This is for the first bank. Each bank will have the same layout, 212 * with an offset being a multiple of 0x24. 213 * 214 * The following functions calculate from the pin number the register 215 * and the bit offset that we should access. 216 */ 217 static inline u32 sunxi_mux_reg(u16 pin) 218 { 219 u8 bank = pin / PINS_PER_BANK; 220 u32 offset = bank * BANK_MEM_SIZE; 221 offset += MUX_REGS_OFFSET; 222 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04; 223 return round_down(offset, 4); 224 } 225 226 static inline u32 sunxi_mux_offset(u16 pin) 227 { 228 u32 pin_num = pin % MUX_PINS_PER_REG; 229 return pin_num * MUX_PINS_BITS; 230 } 231 232 static inline u32 sunxi_data_reg(u16 pin) 233 { 234 u8 bank = pin / PINS_PER_BANK; 235 u32 offset = bank * BANK_MEM_SIZE; 236 offset += DATA_REGS_OFFSET; 237 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04; 238 return round_down(offset, 4); 239 } 240 241 static inline u32 sunxi_data_offset(u16 pin) 242 { 243 u32 pin_num = pin % DATA_PINS_PER_REG; 244 return pin_num * DATA_PINS_BITS; 245 } 246 247 static inline u32 sunxi_dlevel_reg(u16 pin) 248 { 249 u8 bank = pin / PINS_PER_BANK; 250 u32 offset = bank * BANK_MEM_SIZE; 251 offset += DLEVEL_REGS_OFFSET; 252 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04; 253 return round_down(offset, 4); 254 } 255 256 static inline u32 sunxi_dlevel_offset(u16 pin) 257 { 258 u32 pin_num = pin % DLEVEL_PINS_PER_REG; 259 return pin_num * DLEVEL_PINS_BITS; 260 } 261 262 static inline u32 sunxi_pull_reg(u16 pin) 263 { 264 u8 bank = pin / PINS_PER_BANK; 265 u32 offset = bank * BANK_MEM_SIZE; 266 offset += PULL_REGS_OFFSET; 267 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04; 268 return round_down(offset, 4); 269 } 270 271 static inline u32 sunxi_pull_offset(u16 pin) 272 { 273 u32 pin_num = pin % PULL_PINS_PER_REG; 274 return pin_num * PULL_PINS_BITS; 275 } 276 277 static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank) 278 { 279 if (!desc->irq_bank_map) 280 return bank; 281 else 282 return desc->irq_bank_map[bank]; 283 } 284 285 static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc, 286 u16 irq) 287 { 288 u8 bank = irq / IRQ_PER_BANK; 289 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; 290 291 return IRQ_CFG_REG + 292 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg; 293 } 294 295 static inline u32 sunxi_irq_cfg_offset(u16 irq) 296 { 297 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG; 298 return irq_num * IRQ_CFG_IRQ_BITS; 299 } 300 301 static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 302 { 303 return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 304 } 305 306 static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc, 307 u16 irq) 308 { 309 u8 bank = irq / IRQ_PER_BANK; 310 311 return sunxi_irq_ctrl_reg_from_bank(desc, bank); 312 } 313 314 static inline u32 sunxi_irq_ctrl_offset(u16 irq) 315 { 316 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG; 317 return irq_num * IRQ_CTRL_IRQ_BITS; 318 } 319 320 static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 321 { 322 return IRQ_DEBOUNCE_REG + 323 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 324 } 325 326 static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 327 { 328 return IRQ_STATUS_REG + 329 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 330 } 331 332 static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc, 333 u16 irq) 334 { 335 u8 bank = irq / IRQ_PER_BANK; 336 337 return sunxi_irq_status_reg_from_bank(desc, bank); 338 } 339 340 static inline u32 sunxi_irq_status_offset(u16 irq) 341 { 342 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG; 343 return irq_num * IRQ_STATUS_IRQ_BITS; 344 } 345 346 static inline u32 sunxi_grp_config_reg(u16 pin) 347 { 348 u8 bank = pin / PINS_PER_BANK; 349 350 return GRP_CFG_REG + bank * 0x4; 351 } 352 353 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, 354 const struct sunxi_pinctrl_desc *desc, 355 unsigned long variant); 356 357 #define sunxi_pinctrl_init(_dev, _desc) \ 358 sunxi_pinctrl_init_with_variant(_dev, _desc, 0) 359 360 #endif /* __PINCTRL_SUNXI_H */ 361