1 /*
2  * Allwinner A1X SoCs pinctrl driver.
3  *
4  * Copyright (C) 2012 Maxime Ripard
5  *
6  * Maxime Ripard <maxime.ripard@free-electrons.com>
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2.  This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  */
12 
13 #ifndef __PINCTRL_SUNXI_H
14 #define __PINCTRL_SUNXI_H
15 
16 #include <linux/kernel.h>
17 #include <linux/spinlock.h>
18 
19 #define PA_BASE	0
20 #define PB_BASE	32
21 #define PC_BASE	64
22 #define PD_BASE	96
23 #define PE_BASE	128
24 #define PF_BASE	160
25 #define PG_BASE	192
26 #define PH_BASE	224
27 #define PI_BASE	256
28 #define PL_BASE	352
29 #define PM_BASE	384
30 
31 #define SUNXI_PINCTRL_PIN(bank, pin)		\
32 	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
33 
34 #define SUNXI_PIN_NAME_MAX_LEN	5
35 
36 #define BANK_MEM_SIZE		0x24
37 #define MUX_REGS_OFFSET		0x0
38 #define DATA_REGS_OFFSET	0x10
39 #define DLEVEL_REGS_OFFSET	0x14
40 #define PULL_REGS_OFFSET	0x1c
41 
42 #define PINS_PER_BANK		32
43 #define MUX_PINS_PER_REG	8
44 #define MUX_PINS_BITS		4
45 #define MUX_PINS_MASK		0x0f
46 #define DATA_PINS_PER_REG	32
47 #define DATA_PINS_BITS		1
48 #define DATA_PINS_MASK		0x01
49 #define DLEVEL_PINS_PER_REG	16
50 #define DLEVEL_PINS_BITS	2
51 #define DLEVEL_PINS_MASK	0x03
52 #define PULL_PINS_PER_REG	16
53 #define PULL_PINS_BITS		2
54 #define PULL_PINS_MASK		0x03
55 
56 #define IRQ_PER_BANK		32
57 
58 #define IRQ_CFG_REG		0x200
59 #define IRQ_CFG_IRQ_PER_REG		8
60 #define IRQ_CFG_IRQ_BITS		4
61 #define IRQ_CFG_IRQ_MASK		((1 << IRQ_CFG_IRQ_BITS) - 1)
62 #define IRQ_CTRL_REG		0x210
63 #define IRQ_CTRL_IRQ_PER_REG		32
64 #define IRQ_CTRL_IRQ_BITS		1
65 #define IRQ_CTRL_IRQ_MASK		((1 << IRQ_CTRL_IRQ_BITS) - 1)
66 #define IRQ_STATUS_REG		0x214
67 #define IRQ_STATUS_IRQ_PER_REG		32
68 #define IRQ_STATUS_IRQ_BITS		1
69 #define IRQ_STATUS_IRQ_MASK		((1 << IRQ_STATUS_IRQ_BITS) - 1)
70 
71 #define IRQ_MEM_SIZE		0x20
72 
73 #define IRQ_EDGE_RISING		0x00
74 #define IRQ_EDGE_FALLING	0x01
75 #define IRQ_LEVEL_HIGH		0x02
76 #define IRQ_LEVEL_LOW		0x03
77 #define IRQ_EDGE_BOTH		0x04
78 
79 struct sunxi_desc_function {
80 	const char	*name;
81 	u8		muxval;
82 	u8		irqbank;
83 	u8		irqnum;
84 };
85 
86 struct sunxi_desc_pin {
87 	struct pinctrl_pin_desc		pin;
88 	struct sunxi_desc_function	*functions;
89 };
90 
91 struct sunxi_pinctrl_desc {
92 	const struct sunxi_desc_pin	*pins;
93 	int				npins;
94 	unsigned			pin_base;
95 	unsigned			irq_banks;
96 };
97 
98 struct sunxi_pinctrl_function {
99 	const char	*name;
100 	const char	**groups;
101 	unsigned	ngroups;
102 };
103 
104 struct sunxi_pinctrl_group {
105 	const char	*name;
106 	unsigned long	config;
107 	unsigned	pin;
108 };
109 
110 struct sunxi_pinctrl {
111 	void __iomem			*membase;
112 	struct gpio_chip		*chip;
113 	const struct sunxi_pinctrl_desc	*desc;
114 	struct device			*dev;
115 	struct irq_domain		*domain;
116 	struct sunxi_pinctrl_function	*functions;
117 	unsigned			nfunctions;
118 	struct sunxi_pinctrl_group	*groups;
119 	unsigned			ngroups;
120 	int				*irq;
121 	unsigned			*irq_array;
122 	spinlock_t			lock;
123 	struct pinctrl_dev		*pctl_dev;
124 };
125 
126 #define SUNXI_PIN(_pin, ...)					\
127 	{							\
128 		.pin = _pin,					\
129 		.functions = (struct sunxi_desc_function[]){	\
130 			__VA_ARGS__, { } },			\
131 	}
132 
133 #define SUNXI_FUNCTION(_val, _name)				\
134 	{							\
135 		.name = _name,					\
136 		.muxval = _val,					\
137 	}
138 
139 #define SUNXI_FUNCTION_IRQ(_val, _irq)				\
140 	{							\
141 		.name = "irq",					\
142 		.muxval = _val,					\
143 		.irqnum = _irq,					\
144 	}
145 
146 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq)		\
147 	{							\
148 		.name = "irq",					\
149 		.muxval = _val,					\
150 		.irqbank = _bank,				\
151 		.irqnum = _irq,					\
152 	}
153 
154 /*
155  * The sunXi PIO registers are organized as is:
156  * 0x00 - 0x0c	Muxing values.
157  *		8 pins per register, each pin having a 4bits value
158  * 0x10		Pin values
159  *		32 bits per register, each pin corresponding to one bit
160  * 0x14 - 0x18	Drive level
161  *		16 pins per register, each pin having a 2bits value
162  * 0x1c - 0x20	Pull-Up values
163  *		16 pins per register, each pin having a 2bits value
164  *
165  * This is for the first bank. Each bank will have the same layout,
166  * with an offset being a multiple of 0x24.
167  *
168  * The following functions calculate from the pin number the register
169  * and the bit offset that we should access.
170  */
171 static inline u32 sunxi_mux_reg(u16 pin)
172 {
173 	u8 bank = pin / PINS_PER_BANK;
174 	u32 offset = bank * BANK_MEM_SIZE;
175 	offset += MUX_REGS_OFFSET;
176 	offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
177 	return round_down(offset, 4);
178 }
179 
180 static inline u32 sunxi_mux_offset(u16 pin)
181 {
182 	u32 pin_num = pin % MUX_PINS_PER_REG;
183 	return pin_num * MUX_PINS_BITS;
184 }
185 
186 static inline u32 sunxi_data_reg(u16 pin)
187 {
188 	u8 bank = pin / PINS_PER_BANK;
189 	u32 offset = bank * BANK_MEM_SIZE;
190 	offset += DATA_REGS_OFFSET;
191 	offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
192 	return round_down(offset, 4);
193 }
194 
195 static inline u32 sunxi_data_offset(u16 pin)
196 {
197 	u32 pin_num = pin % DATA_PINS_PER_REG;
198 	return pin_num * DATA_PINS_BITS;
199 }
200 
201 static inline u32 sunxi_dlevel_reg(u16 pin)
202 {
203 	u8 bank = pin / PINS_PER_BANK;
204 	u32 offset = bank * BANK_MEM_SIZE;
205 	offset += DLEVEL_REGS_OFFSET;
206 	offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
207 	return round_down(offset, 4);
208 }
209 
210 static inline u32 sunxi_dlevel_offset(u16 pin)
211 {
212 	u32 pin_num = pin % DLEVEL_PINS_PER_REG;
213 	return pin_num * DLEVEL_PINS_BITS;
214 }
215 
216 static inline u32 sunxi_pull_reg(u16 pin)
217 {
218 	u8 bank = pin / PINS_PER_BANK;
219 	u32 offset = bank * BANK_MEM_SIZE;
220 	offset += PULL_REGS_OFFSET;
221 	offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
222 	return round_down(offset, 4);
223 }
224 
225 static inline u32 sunxi_pull_offset(u16 pin)
226 {
227 	u32 pin_num = pin % PULL_PINS_PER_REG;
228 	return pin_num * PULL_PINS_BITS;
229 }
230 
231 static inline u32 sunxi_irq_cfg_reg(u16 irq)
232 {
233 	u8 bank = irq / IRQ_PER_BANK;
234 	u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
235 
236 	return IRQ_CFG_REG + bank * IRQ_MEM_SIZE + reg;
237 }
238 
239 static inline u32 sunxi_irq_cfg_offset(u16 irq)
240 {
241 	u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
242 	return irq_num * IRQ_CFG_IRQ_BITS;
243 }
244 
245 static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank)
246 {
247 	return IRQ_CTRL_REG + bank * IRQ_MEM_SIZE;
248 }
249 
250 static inline u32 sunxi_irq_ctrl_reg(u16 irq)
251 {
252 	u8 bank = irq / IRQ_PER_BANK;
253 
254 	return sunxi_irq_ctrl_reg_from_bank(bank);
255 }
256 
257 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
258 {
259 	u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
260 	return irq_num * IRQ_CTRL_IRQ_BITS;
261 }
262 
263 static inline u32 sunxi_irq_status_reg_from_bank(u8 bank)
264 {
265 	return IRQ_STATUS_REG + bank * IRQ_MEM_SIZE;
266 }
267 
268 static inline u32 sunxi_irq_status_reg(u16 irq)
269 {
270 	u8 bank = irq / IRQ_PER_BANK;
271 
272 	return sunxi_irq_status_reg_from_bank(bank);
273 }
274 
275 static inline u32 sunxi_irq_status_offset(u16 irq)
276 {
277 	u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
278 	return irq_num * IRQ_STATUS_IRQ_BITS;
279 }
280 
281 int sunxi_pinctrl_init(struct platform_device *pdev,
282 		       const struct sunxi_pinctrl_desc *desc);
283 
284 #endif /* __PINCTRL_SUNXI_H */
285