1 /*
2  * Allwinner A1X SoCs pinctrl driver.
3  *
4  * Copyright (C) 2012 Maxime Ripard
5  *
6  * Maxime Ripard <maxime.ripard@free-electrons.com>
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2.  This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  */
12 
13 #ifndef __PINCTRL_SUNXI_H
14 #define __PINCTRL_SUNXI_H
15 
16 #include <linux/kernel.h>
17 #include <linux/spinlock.h>
18 
19 #define PA_BASE	0
20 #define PB_BASE	32
21 #define PC_BASE	64
22 #define PD_BASE	96
23 #define PE_BASE	128
24 #define PF_BASE	160
25 #define PG_BASE	192
26 #define PH_BASE	224
27 #define PI_BASE	256
28 #define PL_BASE	352
29 #define PM_BASE	384
30 #define PN_BASE	416
31 
32 #define SUNXI_PINCTRL_PIN(bank, pin)		\
33 	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
34 
35 #define SUNXI_PIN_NAME_MAX_LEN	5
36 
37 #define BANK_MEM_SIZE		0x24
38 #define MUX_REGS_OFFSET		0x0
39 #define DATA_REGS_OFFSET	0x10
40 #define DLEVEL_REGS_OFFSET	0x14
41 #define PULL_REGS_OFFSET	0x1c
42 
43 #define PINS_PER_BANK		32
44 #define MUX_PINS_PER_REG	8
45 #define MUX_PINS_BITS		4
46 #define MUX_PINS_MASK		0x0f
47 #define DATA_PINS_PER_REG	32
48 #define DATA_PINS_BITS		1
49 #define DATA_PINS_MASK		0x01
50 #define DLEVEL_PINS_PER_REG	16
51 #define DLEVEL_PINS_BITS	2
52 #define DLEVEL_PINS_MASK	0x03
53 #define PULL_PINS_PER_REG	16
54 #define PULL_PINS_BITS		2
55 #define PULL_PINS_MASK		0x03
56 
57 #define IRQ_PER_BANK		32
58 
59 #define IRQ_CFG_REG		0x200
60 #define IRQ_CFG_IRQ_PER_REG		8
61 #define IRQ_CFG_IRQ_BITS		4
62 #define IRQ_CFG_IRQ_MASK		((1 << IRQ_CFG_IRQ_BITS) - 1)
63 #define IRQ_CTRL_REG		0x210
64 #define IRQ_CTRL_IRQ_PER_REG		32
65 #define IRQ_CTRL_IRQ_BITS		1
66 #define IRQ_CTRL_IRQ_MASK		((1 << IRQ_CTRL_IRQ_BITS) - 1)
67 #define IRQ_STATUS_REG		0x214
68 #define IRQ_STATUS_IRQ_PER_REG		32
69 #define IRQ_STATUS_IRQ_BITS		1
70 #define IRQ_STATUS_IRQ_MASK		((1 << IRQ_STATUS_IRQ_BITS) - 1)
71 
72 #define IRQ_DEBOUNCE_REG	0x218
73 
74 #define IRQ_MEM_SIZE		0x20
75 
76 #define IRQ_EDGE_RISING		0x00
77 #define IRQ_EDGE_FALLING	0x01
78 #define IRQ_LEVEL_HIGH		0x02
79 #define IRQ_LEVEL_LOW		0x03
80 #define IRQ_EDGE_BOTH		0x04
81 
82 #define GRP_CFG_REG		0x300
83 
84 #define IO_BIAS_MASK		GENMASK(3, 0)
85 
86 #define SUN4I_FUNC_INPUT	0
87 #define SUN4I_FUNC_IRQ		6
88 
89 #define PINCTRL_SUN5I_A10S	BIT(1)
90 #define PINCTRL_SUN5I_A13	BIT(2)
91 #define PINCTRL_SUN5I_GR8	BIT(3)
92 #define PINCTRL_SUN6I_A31	BIT(4)
93 #define PINCTRL_SUN6I_A31S	BIT(5)
94 #define PINCTRL_SUN4I_A10	BIT(6)
95 #define PINCTRL_SUN7I_A20	BIT(7)
96 #define PINCTRL_SUN8I_R40	BIT(8)
97 
98 #define PIO_POW_MOD_SEL_REG	0x340
99 
100 enum sunxi_desc_bias_voltage {
101 	BIAS_VOLTAGE_NONE,
102 	/*
103 	 * Bias voltage configuration is done through
104 	 * Pn_GRP_CONFIG registers, as seen on A80 SoC.
105 	 */
106 	BIAS_VOLTAGE_GRP_CONFIG,
107 	/*
108 	 * Bias voltage is set through PIO_POW_MOD_SEL_REG
109 	 * register, as seen on H6 SoC, for example.
110 	 */
111 	BIAS_VOLTAGE_PIO_POW_MODE_SEL,
112 };
113 
114 struct sunxi_desc_function {
115 	unsigned long	variant;
116 	const char	*name;
117 	u8		muxval;
118 	u8		irqbank;
119 	u8		irqnum;
120 };
121 
122 struct sunxi_desc_pin {
123 	struct pinctrl_pin_desc		pin;
124 	unsigned long			variant;
125 	struct sunxi_desc_function	*functions;
126 };
127 
128 struct sunxi_pinctrl_desc {
129 	const struct sunxi_desc_pin	*pins;
130 	int				npins;
131 	unsigned			pin_base;
132 	unsigned			irq_banks;
133 	const unsigned int		*irq_bank_map;
134 	bool				irq_read_needs_mux;
135 	bool				disable_strict_mode;
136 	enum sunxi_desc_bias_voltage	io_bias_cfg_variant;
137 };
138 
139 struct sunxi_pinctrl_function {
140 	const char	*name;
141 	const char	**groups;
142 	unsigned	ngroups;
143 };
144 
145 struct sunxi_pinctrl_group {
146 	const char	*name;
147 	unsigned	pin;
148 };
149 
150 struct sunxi_pinctrl_regulator {
151 	struct regulator	*regulator;
152 	refcount_t		refcount;
153 };
154 
155 struct sunxi_pinctrl {
156 	void __iomem			*membase;
157 	struct gpio_chip		*chip;
158 	const struct sunxi_pinctrl_desc	*desc;
159 	struct device			*dev;
160 	struct sunxi_pinctrl_regulator	regulators[9];
161 	struct irq_domain		*domain;
162 	struct sunxi_pinctrl_function	*functions;
163 	unsigned			nfunctions;
164 	struct sunxi_pinctrl_group	*groups;
165 	unsigned			ngroups;
166 	int				*irq;
167 	unsigned			*irq_array;
168 	raw_spinlock_t			lock;
169 	struct pinctrl_dev		*pctl_dev;
170 	unsigned long			variant;
171 };
172 
173 #define SUNXI_PIN(_pin, ...)					\
174 	{							\
175 		.pin = _pin,					\
176 		.functions = (struct sunxi_desc_function[]){	\
177 			__VA_ARGS__, { } },			\
178 	}
179 
180 #define SUNXI_PIN_VARIANT(_pin, _variant, ...)			\
181 	{							\
182 		.pin = _pin,					\
183 		.variant = _variant,				\
184 		.functions = (struct sunxi_desc_function[]){	\
185 			__VA_ARGS__, { } },			\
186 	}
187 
188 #define SUNXI_FUNCTION(_val, _name)				\
189 	{							\
190 		.name = _name,					\
191 		.muxval = _val,					\
192 	}
193 
194 #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant)		\
195 	{							\
196 		.name = _name,					\
197 		.muxval = _val,					\
198 		.variant = _variant,				\
199 	}
200 
201 #define SUNXI_FUNCTION_IRQ(_val, _irq)				\
202 	{							\
203 		.name = "irq",					\
204 		.muxval = _val,					\
205 		.irqnum = _irq,					\
206 	}
207 
208 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq)		\
209 	{							\
210 		.name = "irq",					\
211 		.muxval = _val,					\
212 		.irqbank = _bank,				\
213 		.irqnum = _irq,					\
214 	}
215 
216 /*
217  * The sunXi PIO registers are organized as is:
218  * 0x00 - 0x0c	Muxing values.
219  *		8 pins per register, each pin having a 4bits value
220  * 0x10		Pin values
221  *		32 bits per register, each pin corresponding to one bit
222  * 0x14 - 0x18	Drive level
223  *		16 pins per register, each pin having a 2bits value
224  * 0x1c - 0x20	Pull-Up values
225  *		16 pins per register, each pin having a 2bits value
226  *
227  * This is for the first bank. Each bank will have the same layout,
228  * with an offset being a multiple of 0x24.
229  *
230  * The following functions calculate from the pin number the register
231  * and the bit offset that we should access.
232  */
233 static inline u32 sunxi_mux_reg(u16 pin)
234 {
235 	u8 bank = pin / PINS_PER_BANK;
236 	u32 offset = bank * BANK_MEM_SIZE;
237 	offset += MUX_REGS_OFFSET;
238 	offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
239 	return round_down(offset, 4);
240 }
241 
242 static inline u32 sunxi_mux_offset(u16 pin)
243 {
244 	u32 pin_num = pin % MUX_PINS_PER_REG;
245 	return pin_num * MUX_PINS_BITS;
246 }
247 
248 static inline u32 sunxi_data_reg(u16 pin)
249 {
250 	u8 bank = pin / PINS_PER_BANK;
251 	u32 offset = bank * BANK_MEM_SIZE;
252 	offset += DATA_REGS_OFFSET;
253 	offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
254 	return round_down(offset, 4);
255 }
256 
257 static inline u32 sunxi_data_offset(u16 pin)
258 {
259 	u32 pin_num = pin % DATA_PINS_PER_REG;
260 	return pin_num * DATA_PINS_BITS;
261 }
262 
263 static inline u32 sunxi_dlevel_reg(u16 pin)
264 {
265 	u8 bank = pin / PINS_PER_BANK;
266 	u32 offset = bank * BANK_MEM_SIZE;
267 	offset += DLEVEL_REGS_OFFSET;
268 	offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
269 	return round_down(offset, 4);
270 }
271 
272 static inline u32 sunxi_dlevel_offset(u16 pin)
273 {
274 	u32 pin_num = pin % DLEVEL_PINS_PER_REG;
275 	return pin_num * DLEVEL_PINS_BITS;
276 }
277 
278 static inline u32 sunxi_pull_reg(u16 pin)
279 {
280 	u8 bank = pin / PINS_PER_BANK;
281 	u32 offset = bank * BANK_MEM_SIZE;
282 	offset += PULL_REGS_OFFSET;
283 	offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
284 	return round_down(offset, 4);
285 }
286 
287 static inline u32 sunxi_pull_offset(u16 pin)
288 {
289 	u32 pin_num = pin % PULL_PINS_PER_REG;
290 	return pin_num * PULL_PINS_BITS;
291 }
292 
293 static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
294 {
295 	if (!desc->irq_bank_map)
296 		return bank;
297 	else
298 		return desc->irq_bank_map[bank];
299 }
300 
301 static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
302 				    u16 irq)
303 {
304 	u8 bank = irq / IRQ_PER_BANK;
305 	u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
306 
307 	return IRQ_CFG_REG +
308 	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
309 }
310 
311 static inline u32 sunxi_irq_cfg_offset(u16 irq)
312 {
313 	u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
314 	return irq_num * IRQ_CFG_IRQ_BITS;
315 }
316 
317 static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
318 {
319 	return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
320 }
321 
322 static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
323 				     u16 irq)
324 {
325 	u8 bank = irq / IRQ_PER_BANK;
326 
327 	return sunxi_irq_ctrl_reg_from_bank(desc, bank);
328 }
329 
330 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
331 {
332 	u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
333 	return irq_num * IRQ_CTRL_IRQ_BITS;
334 }
335 
336 static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
337 {
338 	return IRQ_DEBOUNCE_REG +
339 	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
340 }
341 
342 static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
343 {
344 	return IRQ_STATUS_REG +
345 	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
346 }
347 
348 static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
349 				       u16 irq)
350 {
351 	u8 bank = irq / IRQ_PER_BANK;
352 
353 	return sunxi_irq_status_reg_from_bank(desc, bank);
354 }
355 
356 static inline u32 sunxi_irq_status_offset(u16 irq)
357 {
358 	u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
359 	return irq_num * IRQ_STATUS_IRQ_BITS;
360 }
361 
362 static inline u32 sunxi_grp_config_reg(u16 pin)
363 {
364 	u8 bank = pin / PINS_PER_BANK;
365 
366 	return GRP_CFG_REG + bank * 0x4;
367 }
368 
369 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
370 				    const struct sunxi_pinctrl_desc *desc,
371 				    unsigned long variant);
372 
373 #define sunxi_pinctrl_init(_dev, _desc) \
374 	sunxi_pinctrl_init_with_variant(_dev, _desc, 0)
375 
376 #endif /* __PINCTRL_SUNXI_H */
377