1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #ifndef __PINCTRL_SUNXI_H 14 #define __PINCTRL_SUNXI_H 15 16 #include <linux/kernel.h> 17 #include <linux/spinlock.h> 18 19 #define PA_BASE 0 20 #define PB_BASE 32 21 #define PC_BASE 64 22 #define PD_BASE 96 23 #define PE_BASE 128 24 #define PF_BASE 160 25 #define PG_BASE 192 26 #define PH_BASE 224 27 #define PI_BASE 256 28 #define PL_BASE 352 29 #define PM_BASE 384 30 #define PN_BASE 416 31 32 #define SUNXI_PINCTRL_PIN(bank, pin) \ 33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin) 34 35 #define SUNXI_PIN_NAME_MAX_LEN 5 36 37 #define BANK_MEM_SIZE 0x24 38 #define MUX_REGS_OFFSET 0x0 39 #define DATA_REGS_OFFSET 0x10 40 #define DLEVEL_REGS_OFFSET 0x14 41 #define PULL_REGS_OFFSET 0x1c 42 43 #define PINS_PER_BANK 32 44 #define MUX_PINS_PER_REG 8 45 #define MUX_PINS_BITS 4 46 #define MUX_PINS_MASK 0x0f 47 #define DATA_PINS_PER_REG 32 48 #define DATA_PINS_BITS 1 49 #define DATA_PINS_MASK 0x01 50 #define DLEVEL_PINS_PER_REG 16 51 #define DLEVEL_PINS_BITS 2 52 #define DLEVEL_PINS_MASK 0x03 53 #define PULL_PINS_PER_REG 16 54 #define PULL_PINS_BITS 2 55 #define PULL_PINS_MASK 0x03 56 57 #define IRQ_PER_BANK 32 58 59 #define IRQ_CFG_REG 0x200 60 #define IRQ_CFG_IRQ_PER_REG 8 61 #define IRQ_CFG_IRQ_BITS 4 62 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1) 63 #define IRQ_CTRL_REG 0x210 64 #define IRQ_CTRL_IRQ_PER_REG 32 65 #define IRQ_CTRL_IRQ_BITS 1 66 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1) 67 #define IRQ_STATUS_REG 0x214 68 #define IRQ_STATUS_IRQ_PER_REG 32 69 #define IRQ_STATUS_IRQ_BITS 1 70 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) 71 72 #define IRQ_DEBOUNCE_REG 0x218 73 74 #define IRQ_MEM_SIZE 0x20 75 76 #define IRQ_EDGE_RISING 0x00 77 #define IRQ_EDGE_FALLING 0x01 78 #define IRQ_LEVEL_HIGH 0x02 79 #define IRQ_LEVEL_LOW 0x03 80 #define IRQ_EDGE_BOTH 0x04 81 82 #define SUN4I_FUNC_INPUT 0 83 #define SUN4I_FUNC_IRQ 6 84 85 #define PINCTRL_SUN5I_A10S BIT(1) 86 #define PINCTRL_SUN5I_A13 BIT(2) 87 #define PINCTRL_SUN5I_GR8 BIT(3) 88 #define PINCTRL_SUN6I_A31 BIT(4) 89 #define PINCTRL_SUN6I_A31S BIT(5) 90 #define PINCTRL_SUN4I_A10 BIT(6) 91 #define PINCTRL_SUN7I_A20 BIT(7) 92 #define PINCTRL_SUN8I_R40 BIT(8) 93 94 struct sunxi_desc_function { 95 unsigned long variant; 96 const char *name; 97 u8 muxval; 98 u8 irqbank; 99 u8 irqnum; 100 }; 101 102 struct sunxi_desc_pin { 103 struct pinctrl_pin_desc pin; 104 unsigned long variant; 105 struct sunxi_desc_function *functions; 106 }; 107 108 struct sunxi_pinctrl_desc { 109 const struct sunxi_desc_pin *pins; 110 int npins; 111 unsigned pin_base; 112 unsigned irq_banks; 113 const unsigned int *irq_bank_map; 114 bool irq_read_needs_mux; 115 bool disable_strict_mode; 116 }; 117 118 struct sunxi_pinctrl_function { 119 const char *name; 120 const char **groups; 121 unsigned ngroups; 122 }; 123 124 struct sunxi_pinctrl_group { 125 const char *name; 126 unsigned pin; 127 }; 128 129 struct sunxi_pinctrl_regulator { 130 struct regulator *regulator; 131 refcount_t refcount; 132 }; 133 134 struct sunxi_pinctrl { 135 void __iomem *membase; 136 struct gpio_chip *chip; 137 const struct sunxi_pinctrl_desc *desc; 138 struct device *dev; 139 struct sunxi_pinctrl_regulator regulators[12]; 140 struct irq_domain *domain; 141 struct sunxi_pinctrl_function *functions; 142 unsigned nfunctions; 143 struct sunxi_pinctrl_group *groups; 144 unsigned ngroups; 145 int *irq; 146 unsigned *irq_array; 147 raw_spinlock_t lock; 148 struct pinctrl_dev *pctl_dev; 149 unsigned long variant; 150 }; 151 152 #define SUNXI_PIN(_pin, ...) \ 153 { \ 154 .pin = _pin, \ 155 .functions = (struct sunxi_desc_function[]){ \ 156 __VA_ARGS__, { } }, \ 157 } 158 159 #define SUNXI_PIN_VARIANT(_pin, _variant, ...) \ 160 { \ 161 .pin = _pin, \ 162 .variant = _variant, \ 163 .functions = (struct sunxi_desc_function[]){ \ 164 __VA_ARGS__, { } }, \ 165 } 166 167 #define SUNXI_FUNCTION(_val, _name) \ 168 { \ 169 .name = _name, \ 170 .muxval = _val, \ 171 } 172 173 #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \ 174 { \ 175 .name = _name, \ 176 .muxval = _val, \ 177 .variant = _variant, \ 178 } 179 180 #define SUNXI_FUNCTION_IRQ(_val, _irq) \ 181 { \ 182 .name = "irq", \ 183 .muxval = _val, \ 184 .irqnum = _irq, \ 185 } 186 187 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ 188 { \ 189 .name = "irq", \ 190 .muxval = _val, \ 191 .irqbank = _bank, \ 192 .irqnum = _irq, \ 193 } 194 195 /* 196 * The sunXi PIO registers are organized as is: 197 * 0x00 - 0x0c Muxing values. 198 * 8 pins per register, each pin having a 4bits value 199 * 0x10 Pin values 200 * 32 bits per register, each pin corresponding to one bit 201 * 0x14 - 0x18 Drive level 202 * 16 pins per register, each pin having a 2bits value 203 * 0x1c - 0x20 Pull-Up values 204 * 16 pins per register, each pin having a 2bits value 205 * 206 * This is for the first bank. Each bank will have the same layout, 207 * with an offset being a multiple of 0x24. 208 * 209 * The following functions calculate from the pin number the register 210 * and the bit offset that we should access. 211 */ 212 static inline u32 sunxi_mux_reg(u16 pin) 213 { 214 u8 bank = pin / PINS_PER_BANK; 215 u32 offset = bank * BANK_MEM_SIZE; 216 offset += MUX_REGS_OFFSET; 217 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04; 218 return round_down(offset, 4); 219 } 220 221 static inline u32 sunxi_mux_offset(u16 pin) 222 { 223 u32 pin_num = pin % MUX_PINS_PER_REG; 224 return pin_num * MUX_PINS_BITS; 225 } 226 227 static inline u32 sunxi_data_reg(u16 pin) 228 { 229 u8 bank = pin / PINS_PER_BANK; 230 u32 offset = bank * BANK_MEM_SIZE; 231 offset += DATA_REGS_OFFSET; 232 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04; 233 return round_down(offset, 4); 234 } 235 236 static inline u32 sunxi_data_offset(u16 pin) 237 { 238 u32 pin_num = pin % DATA_PINS_PER_REG; 239 return pin_num * DATA_PINS_BITS; 240 } 241 242 static inline u32 sunxi_dlevel_reg(u16 pin) 243 { 244 u8 bank = pin / PINS_PER_BANK; 245 u32 offset = bank * BANK_MEM_SIZE; 246 offset += DLEVEL_REGS_OFFSET; 247 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04; 248 return round_down(offset, 4); 249 } 250 251 static inline u32 sunxi_dlevel_offset(u16 pin) 252 { 253 u32 pin_num = pin % DLEVEL_PINS_PER_REG; 254 return pin_num * DLEVEL_PINS_BITS; 255 } 256 257 static inline u32 sunxi_pull_reg(u16 pin) 258 { 259 u8 bank = pin / PINS_PER_BANK; 260 u32 offset = bank * BANK_MEM_SIZE; 261 offset += PULL_REGS_OFFSET; 262 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04; 263 return round_down(offset, 4); 264 } 265 266 static inline u32 sunxi_pull_offset(u16 pin) 267 { 268 u32 pin_num = pin % PULL_PINS_PER_REG; 269 return pin_num * PULL_PINS_BITS; 270 } 271 272 static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank) 273 { 274 if (!desc->irq_bank_map) 275 return bank; 276 else 277 return desc->irq_bank_map[bank]; 278 } 279 280 static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc, 281 u16 irq) 282 { 283 u8 bank = irq / IRQ_PER_BANK; 284 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; 285 286 return IRQ_CFG_REG + 287 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg; 288 } 289 290 static inline u32 sunxi_irq_cfg_offset(u16 irq) 291 { 292 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG; 293 return irq_num * IRQ_CFG_IRQ_BITS; 294 } 295 296 static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 297 { 298 return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 299 } 300 301 static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc, 302 u16 irq) 303 { 304 u8 bank = irq / IRQ_PER_BANK; 305 306 return sunxi_irq_ctrl_reg_from_bank(desc, bank); 307 } 308 309 static inline u32 sunxi_irq_ctrl_offset(u16 irq) 310 { 311 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG; 312 return irq_num * IRQ_CTRL_IRQ_BITS; 313 } 314 315 static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 316 { 317 return IRQ_DEBOUNCE_REG + 318 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 319 } 320 321 static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 322 { 323 return IRQ_STATUS_REG + 324 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 325 } 326 327 static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc, 328 u16 irq) 329 { 330 u8 bank = irq / IRQ_PER_BANK; 331 332 return sunxi_irq_status_reg_from_bank(desc, bank); 333 } 334 335 static inline u32 sunxi_irq_status_offset(u16 irq) 336 { 337 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG; 338 return irq_num * IRQ_STATUS_IRQ_BITS; 339 } 340 341 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, 342 const struct sunxi_pinctrl_desc *desc, 343 unsigned long variant); 344 345 #define sunxi_pinctrl_init(_dev, _desc) \ 346 sunxi_pinctrl_init_with_variant(_dev, _desc, 0) 347 348 #endif /* __PINCTRL_SUNXI_H */ 349