1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #ifndef __PINCTRL_SUNXI_H 14 #define __PINCTRL_SUNXI_H 15 16 #include <linux/kernel.h> 17 #include <linux/spinlock.h> 18 19 #define PA_BASE 0 20 #define PB_BASE 32 21 #define PC_BASE 64 22 #define PD_BASE 96 23 #define PE_BASE 128 24 #define PF_BASE 160 25 #define PG_BASE 192 26 #define PH_BASE 224 27 #define PI_BASE 256 28 #define PL_BASE 352 29 #define PM_BASE 384 30 #define PN_BASE 416 31 32 #define SUNXI_PINCTRL_PIN(bank, pin) \ 33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin) 34 35 #define SUNXI_PIN_NAME_MAX_LEN 5 36 37 #define BANK_MEM_SIZE 0x24 38 #define MUX_REGS_OFFSET 0x0 39 #define DATA_REGS_OFFSET 0x10 40 #define DLEVEL_REGS_OFFSET 0x14 41 #define PULL_REGS_OFFSET 0x1c 42 43 #define PINS_PER_BANK 32 44 #define MUX_PINS_PER_REG 8 45 #define MUX_PINS_BITS 4 46 #define MUX_PINS_MASK 0x0f 47 #define DATA_PINS_PER_REG 32 48 #define DATA_PINS_BITS 1 49 #define DATA_PINS_MASK 0x01 50 #define DLEVEL_PINS_PER_REG 16 51 #define DLEVEL_PINS_BITS 2 52 #define DLEVEL_PINS_MASK 0x03 53 #define PULL_PINS_PER_REG 16 54 #define PULL_PINS_BITS 2 55 #define PULL_PINS_MASK 0x03 56 57 #define IRQ_PER_BANK 32 58 59 #define IRQ_CFG_REG 0x200 60 #define IRQ_CFG_IRQ_PER_REG 8 61 #define IRQ_CFG_IRQ_BITS 4 62 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1) 63 #define IRQ_CTRL_REG 0x210 64 #define IRQ_CTRL_IRQ_PER_REG 32 65 #define IRQ_CTRL_IRQ_BITS 1 66 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1) 67 #define IRQ_STATUS_REG 0x214 68 #define IRQ_STATUS_IRQ_PER_REG 32 69 #define IRQ_STATUS_IRQ_BITS 1 70 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) 71 72 #define IRQ_MEM_SIZE 0x20 73 74 #define IRQ_EDGE_RISING 0x00 75 #define IRQ_EDGE_FALLING 0x01 76 #define IRQ_LEVEL_HIGH 0x02 77 #define IRQ_LEVEL_LOW 0x03 78 #define IRQ_EDGE_BOTH 0x04 79 80 #define SUN4I_FUNC_INPUT 0 81 #define SUN4I_FUNC_IRQ 6 82 83 struct sunxi_desc_function { 84 const char *name; 85 u8 muxval; 86 u8 irqbank; 87 u8 irqnum; 88 }; 89 90 struct sunxi_desc_pin { 91 struct pinctrl_pin_desc pin; 92 struct sunxi_desc_function *functions; 93 }; 94 95 struct sunxi_pinctrl_desc { 96 const struct sunxi_desc_pin *pins; 97 int npins; 98 unsigned pin_base; 99 unsigned irq_banks; 100 unsigned irq_bank_base; 101 bool irq_read_needs_mux; 102 }; 103 104 struct sunxi_pinctrl_function { 105 const char *name; 106 const char **groups; 107 unsigned ngroups; 108 }; 109 110 struct sunxi_pinctrl_group { 111 const char *name; 112 unsigned long config; 113 unsigned pin; 114 }; 115 116 struct sunxi_pinctrl { 117 void __iomem *membase; 118 struct gpio_chip *chip; 119 const struct sunxi_pinctrl_desc *desc; 120 struct device *dev; 121 struct irq_domain *domain; 122 struct sunxi_pinctrl_function *functions; 123 unsigned nfunctions; 124 struct sunxi_pinctrl_group *groups; 125 unsigned ngroups; 126 int *irq; 127 unsigned *irq_array; 128 spinlock_t lock; 129 struct pinctrl_dev *pctl_dev; 130 }; 131 132 #define SUNXI_PIN(_pin, ...) \ 133 { \ 134 .pin = _pin, \ 135 .functions = (struct sunxi_desc_function[]){ \ 136 __VA_ARGS__, { } }, \ 137 } 138 139 #define SUNXI_FUNCTION(_val, _name) \ 140 { \ 141 .name = _name, \ 142 .muxval = _val, \ 143 } 144 145 #define SUNXI_FUNCTION_IRQ(_val, _irq) \ 146 { \ 147 .name = "irq", \ 148 .muxval = _val, \ 149 .irqnum = _irq, \ 150 } 151 152 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ 153 { \ 154 .name = "irq", \ 155 .muxval = _val, \ 156 .irqbank = _bank, \ 157 .irqnum = _irq, \ 158 } 159 160 /* 161 * The sunXi PIO registers are organized as is: 162 * 0x00 - 0x0c Muxing values. 163 * 8 pins per register, each pin having a 4bits value 164 * 0x10 Pin values 165 * 32 bits per register, each pin corresponding to one bit 166 * 0x14 - 0x18 Drive level 167 * 16 pins per register, each pin having a 2bits value 168 * 0x1c - 0x20 Pull-Up values 169 * 16 pins per register, each pin having a 2bits value 170 * 171 * This is for the first bank. Each bank will have the same layout, 172 * with an offset being a multiple of 0x24. 173 * 174 * The following functions calculate from the pin number the register 175 * and the bit offset that we should access. 176 */ 177 static inline u32 sunxi_mux_reg(u16 pin) 178 { 179 u8 bank = pin / PINS_PER_BANK; 180 u32 offset = bank * BANK_MEM_SIZE; 181 offset += MUX_REGS_OFFSET; 182 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04; 183 return round_down(offset, 4); 184 } 185 186 static inline u32 sunxi_mux_offset(u16 pin) 187 { 188 u32 pin_num = pin % MUX_PINS_PER_REG; 189 return pin_num * MUX_PINS_BITS; 190 } 191 192 static inline u32 sunxi_data_reg(u16 pin) 193 { 194 u8 bank = pin / PINS_PER_BANK; 195 u32 offset = bank * BANK_MEM_SIZE; 196 offset += DATA_REGS_OFFSET; 197 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04; 198 return round_down(offset, 4); 199 } 200 201 static inline u32 sunxi_data_offset(u16 pin) 202 { 203 u32 pin_num = pin % DATA_PINS_PER_REG; 204 return pin_num * DATA_PINS_BITS; 205 } 206 207 static inline u32 sunxi_dlevel_reg(u16 pin) 208 { 209 u8 bank = pin / PINS_PER_BANK; 210 u32 offset = bank * BANK_MEM_SIZE; 211 offset += DLEVEL_REGS_OFFSET; 212 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04; 213 return round_down(offset, 4); 214 } 215 216 static inline u32 sunxi_dlevel_offset(u16 pin) 217 { 218 u32 pin_num = pin % DLEVEL_PINS_PER_REG; 219 return pin_num * DLEVEL_PINS_BITS; 220 } 221 222 static inline u32 sunxi_pull_reg(u16 pin) 223 { 224 u8 bank = pin / PINS_PER_BANK; 225 u32 offset = bank * BANK_MEM_SIZE; 226 offset += PULL_REGS_OFFSET; 227 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04; 228 return round_down(offset, 4); 229 } 230 231 static inline u32 sunxi_pull_offset(u16 pin) 232 { 233 u32 pin_num = pin % PULL_PINS_PER_REG; 234 return pin_num * PULL_PINS_BITS; 235 } 236 237 static inline u32 sunxi_irq_cfg_reg(u16 irq, unsigned bank_base) 238 { 239 u8 bank = irq / IRQ_PER_BANK; 240 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; 241 242 return IRQ_CFG_REG + (bank_base + bank) * IRQ_MEM_SIZE + reg; 243 } 244 245 static inline u32 sunxi_irq_cfg_offset(u16 irq) 246 { 247 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG; 248 return irq_num * IRQ_CFG_IRQ_BITS; 249 } 250 251 static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank, unsigned bank_base) 252 { 253 return IRQ_CTRL_REG + (bank_base + bank) * IRQ_MEM_SIZE; 254 } 255 256 static inline u32 sunxi_irq_ctrl_reg(u16 irq, unsigned bank_base) 257 { 258 u8 bank = irq / IRQ_PER_BANK; 259 260 return sunxi_irq_ctrl_reg_from_bank(bank, bank_base); 261 } 262 263 static inline u32 sunxi_irq_ctrl_offset(u16 irq) 264 { 265 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG; 266 return irq_num * IRQ_CTRL_IRQ_BITS; 267 } 268 269 static inline u32 sunxi_irq_status_reg_from_bank(u8 bank, unsigned bank_base) 270 { 271 return IRQ_STATUS_REG + (bank_base + bank) * IRQ_MEM_SIZE; 272 } 273 274 static inline u32 sunxi_irq_status_reg(u16 irq, unsigned bank_base) 275 { 276 u8 bank = irq / IRQ_PER_BANK; 277 278 return sunxi_irq_status_reg_from_bank(bank, bank_base); 279 } 280 281 static inline u32 sunxi_irq_status_offset(u16 irq) 282 { 283 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG; 284 return irq_num * IRQ_STATUS_IRQ_BITS; 285 } 286 287 int sunxi_pinctrl_init(struct platform_device *pdev, 288 const struct sunxi_pinctrl_desc *desc); 289 290 #endif /* __PINCTRL_SUNXI_H */ 291