15f910777SMaxime Ripard /* 25f910777SMaxime Ripard * Allwinner A1X SoCs pinctrl driver. 35f910777SMaxime Ripard * 45f910777SMaxime Ripard * Copyright (C) 2012 Maxime Ripard 55f910777SMaxime Ripard * 65f910777SMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com> 75f910777SMaxime Ripard * 85f910777SMaxime Ripard * This file is licensed under the terms of the GNU General Public 95f910777SMaxime Ripard * License version 2. This program is licensed "as is" without any 105f910777SMaxime Ripard * warranty of any kind, whether express or implied. 115f910777SMaxime Ripard */ 125f910777SMaxime Ripard 135f910777SMaxime Ripard #ifndef __PINCTRL_SUNXI_H 145f910777SMaxime Ripard #define __PINCTRL_SUNXI_H 155f910777SMaxime Ripard 165f910777SMaxime Ripard #include <linux/kernel.h> 175f910777SMaxime Ripard #include <linux/spinlock.h> 185f910777SMaxime Ripard 195f910777SMaxime Ripard #define PA_BASE 0 205f910777SMaxime Ripard #define PB_BASE 32 215f910777SMaxime Ripard #define PC_BASE 64 225f910777SMaxime Ripard #define PD_BASE 96 235f910777SMaxime Ripard #define PE_BASE 128 245f910777SMaxime Ripard #define PF_BASE 160 255f910777SMaxime Ripard #define PG_BASE 192 265f910777SMaxime Ripard #define PH_BASE 224 275f910777SMaxime Ripard #define PI_BASE 256 285f910777SMaxime Ripard #define PL_BASE 352 295f910777SMaxime Ripard #define PM_BASE 384 304f6bd5cfSMaxime Ripard #define PN_BASE 416 315f910777SMaxime Ripard 32d10acc63SMaxime Ripard #define SUNXI_PINCTRL_PIN(bank, pin) \ 33d10acc63SMaxime Ripard PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin) 345f910777SMaxime Ripard 355f910777SMaxime Ripard #define SUNXI_PIN_NAME_MAX_LEN 5 365f910777SMaxime Ripard 375f910777SMaxime Ripard #define BANK_MEM_SIZE 0x24 385f910777SMaxime Ripard #define MUX_REGS_OFFSET 0x0 395f910777SMaxime Ripard #define DATA_REGS_OFFSET 0x10 405f910777SMaxime Ripard #define DLEVEL_REGS_OFFSET 0x14 415f910777SMaxime Ripard #define PULL_REGS_OFFSET 0x1c 425f910777SMaxime Ripard 435f910777SMaxime Ripard #define PINS_PER_BANK 32 445f910777SMaxime Ripard #define MUX_PINS_PER_REG 8 455f910777SMaxime Ripard #define MUX_PINS_BITS 4 465f910777SMaxime Ripard #define MUX_PINS_MASK 0x0f 475f910777SMaxime Ripard #define DATA_PINS_PER_REG 32 485f910777SMaxime Ripard #define DATA_PINS_BITS 1 495f910777SMaxime Ripard #define DATA_PINS_MASK 0x01 505f910777SMaxime Ripard #define DLEVEL_PINS_PER_REG 16 515f910777SMaxime Ripard #define DLEVEL_PINS_BITS 2 525f910777SMaxime Ripard #define DLEVEL_PINS_MASK 0x03 535f910777SMaxime Ripard #define PULL_PINS_PER_REG 16 545f910777SMaxime Ripard #define PULL_PINS_BITS 2 555f910777SMaxime Ripard #define PULL_PINS_MASK 0x03 565f910777SMaxime Ripard 57aebdc8abSMaxime Ripard #define IRQ_PER_BANK 32 585f910777SMaxime Ripard 595f910777SMaxime Ripard #define IRQ_CFG_REG 0x200 605f910777SMaxime Ripard #define IRQ_CFG_IRQ_PER_REG 8 615f910777SMaxime Ripard #define IRQ_CFG_IRQ_BITS 4 625f910777SMaxime Ripard #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1) 635f910777SMaxime Ripard #define IRQ_CTRL_REG 0x210 645f910777SMaxime Ripard #define IRQ_CTRL_IRQ_PER_REG 32 655f910777SMaxime Ripard #define IRQ_CTRL_IRQ_BITS 1 665f910777SMaxime Ripard #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1) 675f910777SMaxime Ripard #define IRQ_STATUS_REG 0x214 685f910777SMaxime Ripard #define IRQ_STATUS_IRQ_PER_REG 32 695f910777SMaxime Ripard #define IRQ_STATUS_IRQ_BITS 1 705f910777SMaxime Ripard #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) 715f910777SMaxime Ripard 727c926492SMaxime Ripard #define IRQ_DEBOUNCE_REG 0x218 737c926492SMaxime Ripard 74aebdc8abSMaxime Ripard #define IRQ_MEM_SIZE 0x20 75aebdc8abSMaxime Ripard 765f910777SMaxime Ripard #define IRQ_EDGE_RISING 0x00 775f910777SMaxime Ripard #define IRQ_EDGE_FALLING 0x01 785f910777SMaxime Ripard #define IRQ_LEVEL_HIGH 0x02 795f910777SMaxime Ripard #define IRQ_LEVEL_LOW 0x03 805f910777SMaxime Ripard #define IRQ_EDGE_BOTH 0x04 815f910777SMaxime Ripard 82402bfb3cSChen-Yu Tsai #define GRP_CFG_REG 0x300 83402bfb3cSChen-Yu Tsai 84402bfb3cSChen-Yu Tsai #define IO_BIAS_MASK GENMASK(3, 0) 85402bfb3cSChen-Yu Tsai 86ef6d24ccSHans de Goede #define SUN4I_FUNC_INPUT 0 87ef6d24ccSHans de Goede #define SUN4I_FUNC_IRQ 6 88ef6d24ccSHans de Goede 89858f559fSMaxime Ripard #define PINCTRL_SUN5I_A10S BIT(1) 90858f559fSMaxime Ripard #define PINCTRL_SUN5I_A13 BIT(2) 91858f559fSMaxime Ripard #define PINCTRL_SUN5I_GR8 BIT(3) 924924982eSChen-Yu Tsai #define PINCTRL_SUN6I_A31 BIT(4) 934924982eSChen-Yu Tsai #define PINCTRL_SUN6I_A31S BIT(5) 9488798ba2SIcenowy Zheng #define PINCTRL_SUN4I_A10 BIT(6) 9588798ba2SIcenowy Zheng #define PINCTRL_SUN7I_A20 BIT(7) 9688798ba2SIcenowy Zheng #define PINCTRL_SUN8I_R40 BIT(8) 97fb18f188SIcenowy Zheng #define PINCTRL_SUN8I_V3 BIT(9) 98fb18f188SIcenowy Zheng #define PINCTRL_SUN8I_V3S BIT(10) 99858f559fSMaxime Ripard 100cc62383fSOndrej Jirman #define PIO_POW_MOD_SEL_REG 0x340 101cc62383fSOndrej Jirman 102f7275345SOndrej Jirman enum sunxi_desc_bias_voltage { 103f7275345SOndrej Jirman BIAS_VOLTAGE_NONE, 104f7275345SOndrej Jirman /* 105f7275345SOndrej Jirman * Bias voltage configuration is done through 106f7275345SOndrej Jirman * Pn_GRP_CONFIG registers, as seen on A80 SoC. 107f7275345SOndrej Jirman */ 108f7275345SOndrej Jirman BIAS_VOLTAGE_GRP_CONFIG, 109cc62383fSOndrej Jirman /* 110cc62383fSOndrej Jirman * Bias voltage is set through PIO_POW_MOD_SEL_REG 111cc62383fSOndrej Jirman * register, as seen on H6 SoC, for example. 112cc62383fSOndrej Jirman */ 113cc62383fSOndrej Jirman BIAS_VOLTAGE_PIO_POW_MODE_SEL, 114f7275345SOndrej Jirman }; 115f7275345SOndrej Jirman 1165f910777SMaxime Ripard struct sunxi_desc_function { 117578db85fSMaxime Ripard unsigned long variant; 1185f910777SMaxime Ripard const char *name; 1195f910777SMaxime Ripard u8 muxval; 1206e1c3023SMaxime Ripard u8 irqbank; 1215f910777SMaxime Ripard u8 irqnum; 1225f910777SMaxime Ripard }; 1235f910777SMaxime Ripard 1245f910777SMaxime Ripard struct sunxi_desc_pin { 1255f910777SMaxime Ripard struct pinctrl_pin_desc pin; 126578db85fSMaxime Ripard unsigned long variant; 1275f910777SMaxime Ripard struct sunxi_desc_function *functions; 1285f910777SMaxime Ripard }; 1295f910777SMaxime Ripard 1305f910777SMaxime Ripard struct sunxi_pinctrl_desc { 1315f910777SMaxime Ripard const struct sunxi_desc_pin *pins; 1325f910777SMaxime Ripard int npins; 1335f910777SMaxime Ripard unsigned pin_base; 1348966ada2SMaxime Ripard unsigned irq_banks; 13535817d34SIcenowy Zheng const unsigned int *irq_bank_map; 136ef6d24ccSHans de Goede bool irq_read_needs_mux; 137aae842a3SMaxime Ripard bool disable_strict_mode; 138f7275345SOndrej Jirman enum sunxi_desc_bias_voltage io_bias_cfg_variant; 1395f910777SMaxime Ripard }; 1405f910777SMaxime Ripard 1415f910777SMaxime Ripard struct sunxi_pinctrl_function { 1425f910777SMaxime Ripard const char *name; 1435f910777SMaxime Ripard const char **groups; 1445f910777SMaxime Ripard unsigned ngroups; 1455f910777SMaxime Ripard }; 1465f910777SMaxime Ripard 1475f910777SMaxime Ripard struct sunxi_pinctrl_group { 1485f910777SMaxime Ripard const char *name; 1495f910777SMaxime Ripard unsigned pin; 1505f910777SMaxime Ripard }; 1515f910777SMaxime Ripard 1529a2a566aSMaxime Ripard struct sunxi_pinctrl_regulator { 1539a2a566aSMaxime Ripard struct regulator *regulator; 1549a2a566aSMaxime Ripard refcount_t refcount; 1559a2a566aSMaxime Ripard }; 1569a2a566aSMaxime Ripard 1575f910777SMaxime Ripard struct sunxi_pinctrl { 1585f910777SMaxime Ripard void __iomem *membase; 1595f910777SMaxime Ripard struct gpio_chip *chip; 1605f910777SMaxime Ripard const struct sunxi_pinctrl_desc *desc; 1615f910777SMaxime Ripard struct device *dev; 162ca443844SChen-Yu Tsai struct sunxi_pinctrl_regulator regulators[9]; 1635f910777SMaxime Ripard struct irq_domain *domain; 1645f910777SMaxime Ripard struct sunxi_pinctrl_function *functions; 1655f910777SMaxime Ripard unsigned nfunctions; 1665f910777SMaxime Ripard struct sunxi_pinctrl_group *groups; 1675f910777SMaxime Ripard unsigned ngroups; 168aebdc8abSMaxime Ripard int *irq; 169aebdc8abSMaxime Ripard unsigned *irq_array; 170f658ed36SJulia Cartwright raw_spinlock_t lock; 1715f910777SMaxime Ripard struct pinctrl_dev *pctl_dev; 172578db85fSMaxime Ripard unsigned long variant; 1735f910777SMaxime Ripard }; 1745f910777SMaxime Ripard 1755f910777SMaxime Ripard #define SUNXI_PIN(_pin, ...) \ 1765f910777SMaxime Ripard { \ 1775f910777SMaxime Ripard .pin = _pin, \ 1785f910777SMaxime Ripard .functions = (struct sunxi_desc_function[]){ \ 1795f910777SMaxime Ripard __VA_ARGS__, { } }, \ 1805f910777SMaxime Ripard } 1815f910777SMaxime Ripard 182578db85fSMaxime Ripard #define SUNXI_PIN_VARIANT(_pin, _variant, ...) \ 183578db85fSMaxime Ripard { \ 184578db85fSMaxime Ripard .pin = _pin, \ 185578db85fSMaxime Ripard .variant = _variant, \ 186578db85fSMaxime Ripard .functions = (struct sunxi_desc_function[]){ \ 187578db85fSMaxime Ripard __VA_ARGS__, { } }, \ 188578db85fSMaxime Ripard } 189578db85fSMaxime Ripard 1905f910777SMaxime Ripard #define SUNXI_FUNCTION(_val, _name) \ 1915f910777SMaxime Ripard { \ 1925f910777SMaxime Ripard .name = _name, \ 1935f910777SMaxime Ripard .muxval = _val, \ 1945f910777SMaxime Ripard } 1955f910777SMaxime Ripard 196578db85fSMaxime Ripard #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \ 197578db85fSMaxime Ripard { \ 198578db85fSMaxime Ripard .name = _name, \ 199578db85fSMaxime Ripard .muxval = _val, \ 200578db85fSMaxime Ripard .variant = _variant, \ 201578db85fSMaxime Ripard } 202578db85fSMaxime Ripard 2035f910777SMaxime Ripard #define SUNXI_FUNCTION_IRQ(_val, _irq) \ 2045f910777SMaxime Ripard { \ 2055f910777SMaxime Ripard .name = "irq", \ 2065f910777SMaxime Ripard .muxval = _val, \ 2075f910777SMaxime Ripard .irqnum = _irq, \ 2085f910777SMaxime Ripard } 2095f910777SMaxime Ripard 2106e1c3023SMaxime Ripard #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ 2116e1c3023SMaxime Ripard { \ 2126e1c3023SMaxime Ripard .name = "irq", \ 2136e1c3023SMaxime Ripard .muxval = _val, \ 2146e1c3023SMaxime Ripard .irqbank = _bank, \ 2156e1c3023SMaxime Ripard .irqnum = _irq, \ 2166e1c3023SMaxime Ripard } 2176e1c3023SMaxime Ripard 2185f910777SMaxime Ripard /* 2195f910777SMaxime Ripard * The sunXi PIO registers are organized as is: 2205f910777SMaxime Ripard * 0x00 - 0x0c Muxing values. 2215f910777SMaxime Ripard * 8 pins per register, each pin having a 4bits value 2225f910777SMaxime Ripard * 0x10 Pin values 2235f910777SMaxime Ripard * 32 bits per register, each pin corresponding to one bit 2245f910777SMaxime Ripard * 0x14 - 0x18 Drive level 2255f910777SMaxime Ripard * 16 pins per register, each pin having a 2bits value 2265f910777SMaxime Ripard * 0x1c - 0x20 Pull-Up values 2275f910777SMaxime Ripard * 16 pins per register, each pin having a 2bits value 2285f910777SMaxime Ripard * 2295f910777SMaxime Ripard * This is for the first bank. Each bank will have the same layout, 2305f910777SMaxime Ripard * with an offset being a multiple of 0x24. 2315f910777SMaxime Ripard * 2325f910777SMaxime Ripard * The following functions calculate from the pin number the register 2335f910777SMaxime Ripard * and the bit offset that we should access. 2345f910777SMaxime Ripard */ 2355f910777SMaxime Ripard static inline u32 sunxi_mux_reg(u16 pin) 2365f910777SMaxime Ripard { 2375f910777SMaxime Ripard u8 bank = pin / PINS_PER_BANK; 2385f910777SMaxime Ripard u32 offset = bank * BANK_MEM_SIZE; 2395f910777SMaxime Ripard offset += MUX_REGS_OFFSET; 2405f910777SMaxime Ripard offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04; 2415f910777SMaxime Ripard return round_down(offset, 4); 2425f910777SMaxime Ripard } 2435f910777SMaxime Ripard 2445f910777SMaxime Ripard static inline u32 sunxi_mux_offset(u16 pin) 2455f910777SMaxime Ripard { 2465f910777SMaxime Ripard u32 pin_num = pin % MUX_PINS_PER_REG; 2475f910777SMaxime Ripard return pin_num * MUX_PINS_BITS; 2485f910777SMaxime Ripard } 2495f910777SMaxime Ripard 2505f910777SMaxime Ripard static inline u32 sunxi_data_reg(u16 pin) 2515f910777SMaxime Ripard { 2525f910777SMaxime Ripard u8 bank = pin / PINS_PER_BANK; 2535f910777SMaxime Ripard u32 offset = bank * BANK_MEM_SIZE; 2545f910777SMaxime Ripard offset += DATA_REGS_OFFSET; 2555f910777SMaxime Ripard offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04; 2565f910777SMaxime Ripard return round_down(offset, 4); 2575f910777SMaxime Ripard } 2585f910777SMaxime Ripard 2595f910777SMaxime Ripard static inline u32 sunxi_data_offset(u16 pin) 2605f910777SMaxime Ripard { 2615f910777SMaxime Ripard u32 pin_num = pin % DATA_PINS_PER_REG; 2625f910777SMaxime Ripard return pin_num * DATA_PINS_BITS; 2635f910777SMaxime Ripard } 2645f910777SMaxime Ripard 2655f910777SMaxime Ripard static inline u32 sunxi_dlevel_reg(u16 pin) 2665f910777SMaxime Ripard { 2675f910777SMaxime Ripard u8 bank = pin / PINS_PER_BANK; 2685f910777SMaxime Ripard u32 offset = bank * BANK_MEM_SIZE; 2695f910777SMaxime Ripard offset += DLEVEL_REGS_OFFSET; 2705f910777SMaxime Ripard offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04; 2715f910777SMaxime Ripard return round_down(offset, 4); 2725f910777SMaxime Ripard } 2735f910777SMaxime Ripard 2745f910777SMaxime Ripard static inline u32 sunxi_dlevel_offset(u16 pin) 2755f910777SMaxime Ripard { 2765f910777SMaxime Ripard u32 pin_num = pin % DLEVEL_PINS_PER_REG; 2775f910777SMaxime Ripard return pin_num * DLEVEL_PINS_BITS; 2785f910777SMaxime Ripard } 2795f910777SMaxime Ripard 2805f910777SMaxime Ripard static inline u32 sunxi_pull_reg(u16 pin) 2815f910777SMaxime Ripard { 2825f910777SMaxime Ripard u8 bank = pin / PINS_PER_BANK; 2835f910777SMaxime Ripard u32 offset = bank * BANK_MEM_SIZE; 2845f910777SMaxime Ripard offset += PULL_REGS_OFFSET; 2855f910777SMaxime Ripard offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04; 2865f910777SMaxime Ripard return round_down(offset, 4); 2875f910777SMaxime Ripard } 2885f910777SMaxime Ripard 2895f910777SMaxime Ripard static inline u32 sunxi_pull_offset(u16 pin) 2905f910777SMaxime Ripard { 2915f910777SMaxime Ripard u32 pin_num = pin % PULL_PINS_PER_REG; 2925f910777SMaxime Ripard return pin_num * PULL_PINS_BITS; 2935f910777SMaxime Ripard } 2945f910777SMaxime Ripard 29529dfc6bbSIcenowy Zheng static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank) 29629dfc6bbSIcenowy Zheng { 29735817d34SIcenowy Zheng if (!desc->irq_bank_map) 29835817d34SIcenowy Zheng return bank; 29935817d34SIcenowy Zheng else 30035817d34SIcenowy Zheng return desc->irq_bank_map[bank]; 30129dfc6bbSIcenowy Zheng } 30229dfc6bbSIcenowy Zheng 3034b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc, 3044b0d6c5aSIcenowy Zheng u16 irq) 3055f910777SMaxime Ripard { 306aebdc8abSMaxime Ripard u8 bank = irq / IRQ_PER_BANK; 307aebdc8abSMaxime Ripard u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; 308aebdc8abSMaxime Ripard 30929dfc6bbSIcenowy Zheng return IRQ_CFG_REG + 31029dfc6bbSIcenowy Zheng sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg; 3115f910777SMaxime Ripard } 3125f910777SMaxime Ripard 3135f910777SMaxime Ripard static inline u32 sunxi_irq_cfg_offset(u16 irq) 3145f910777SMaxime Ripard { 3155f910777SMaxime Ripard u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG; 3165f910777SMaxime Ripard return irq_num * IRQ_CFG_IRQ_BITS; 3175f910777SMaxime Ripard } 3185f910777SMaxime Ripard 3194b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 320aebdc8abSMaxime Ripard { 32129dfc6bbSIcenowy Zheng return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 322aebdc8abSMaxime Ripard } 323aebdc8abSMaxime Ripard 3244b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc, 3254b0d6c5aSIcenowy Zheng u16 irq) 3265f910777SMaxime Ripard { 327aebdc8abSMaxime Ripard u8 bank = irq / IRQ_PER_BANK; 328aebdc8abSMaxime Ripard 3294b0d6c5aSIcenowy Zheng return sunxi_irq_ctrl_reg_from_bank(desc, bank); 3305f910777SMaxime Ripard } 3315f910777SMaxime Ripard 3325f910777SMaxime Ripard static inline u32 sunxi_irq_ctrl_offset(u16 irq) 3335f910777SMaxime Ripard { 3345f910777SMaxime Ripard u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG; 3355f910777SMaxime Ripard return irq_num * IRQ_CTRL_IRQ_BITS; 3365f910777SMaxime Ripard } 3375f910777SMaxime Ripard 3384b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 3397c926492SMaxime Ripard { 34029dfc6bbSIcenowy Zheng return IRQ_DEBOUNCE_REG + 34129dfc6bbSIcenowy Zheng sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 3427c926492SMaxime Ripard } 3437c926492SMaxime Ripard 3444b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 345aebdc8abSMaxime Ripard { 34629dfc6bbSIcenowy Zheng return IRQ_STATUS_REG + 34729dfc6bbSIcenowy Zheng sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 348aebdc8abSMaxime Ripard } 349aebdc8abSMaxime Ripard 3504b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc, 3514b0d6c5aSIcenowy Zheng u16 irq) 3525f910777SMaxime Ripard { 353aebdc8abSMaxime Ripard u8 bank = irq / IRQ_PER_BANK; 354aebdc8abSMaxime Ripard 3554b0d6c5aSIcenowy Zheng return sunxi_irq_status_reg_from_bank(desc, bank); 3565f910777SMaxime Ripard } 3575f910777SMaxime Ripard 3585f910777SMaxime Ripard static inline u32 sunxi_irq_status_offset(u16 irq) 3595f910777SMaxime Ripard { 3605f910777SMaxime Ripard u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG; 3615f910777SMaxime Ripard return irq_num * IRQ_STATUS_IRQ_BITS; 3625f910777SMaxime Ripard } 3635f910777SMaxime Ripard 364402bfb3cSChen-Yu Tsai static inline u32 sunxi_grp_config_reg(u16 pin) 365402bfb3cSChen-Yu Tsai { 366402bfb3cSChen-Yu Tsai u8 bank = pin / PINS_PER_BANK; 367402bfb3cSChen-Yu Tsai 368402bfb3cSChen-Yu Tsai return GRP_CFG_REG + bank * 0x4; 369402bfb3cSChen-Yu Tsai } 370402bfb3cSChen-Yu Tsai 371578db85fSMaxime Ripard int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, 372578db85fSMaxime Ripard const struct sunxi_pinctrl_desc *desc, 373578db85fSMaxime Ripard unsigned long variant); 374578db85fSMaxime Ripard 375578db85fSMaxime Ripard #define sunxi_pinctrl_init(_dev, _desc) \ 376578db85fSMaxime Ripard sunxi_pinctrl_init_with_variant(_dev, _desc, 0) 3772284ba6bSMaxime Ripard 3785f910777SMaxime Ripard #endif /* __PINCTRL_SUNXI_H */ 379