15f910777SMaxime Ripard /* 25f910777SMaxime Ripard * Allwinner A1X SoCs pinctrl driver. 35f910777SMaxime Ripard * 45f910777SMaxime Ripard * Copyright (C) 2012 Maxime Ripard 55f910777SMaxime Ripard * 65f910777SMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com> 75f910777SMaxime Ripard * 85f910777SMaxime Ripard * This file is licensed under the terms of the GNU General Public 95f910777SMaxime Ripard * License version 2. This program is licensed "as is" without any 105f910777SMaxime Ripard * warranty of any kind, whether express or implied. 115f910777SMaxime Ripard */ 125f910777SMaxime Ripard 135f910777SMaxime Ripard #ifndef __PINCTRL_SUNXI_H 145f910777SMaxime Ripard #define __PINCTRL_SUNXI_H 155f910777SMaxime Ripard 165f910777SMaxime Ripard #include <linux/kernel.h> 175f910777SMaxime Ripard #include <linux/spinlock.h> 185f910777SMaxime Ripard 195f910777SMaxime Ripard #define PA_BASE 0 205f910777SMaxime Ripard #define PB_BASE 32 215f910777SMaxime Ripard #define PC_BASE 64 225f910777SMaxime Ripard #define PD_BASE 96 235f910777SMaxime Ripard #define PE_BASE 128 245f910777SMaxime Ripard #define PF_BASE 160 255f910777SMaxime Ripard #define PG_BASE 192 265f910777SMaxime Ripard #define PH_BASE 224 275f910777SMaxime Ripard #define PI_BASE 256 285f910777SMaxime Ripard #define PL_BASE 352 295f910777SMaxime Ripard #define PM_BASE 384 305f910777SMaxime Ripard 31d10acc63SMaxime Ripard #define SUNXI_PINCTRL_PIN(bank, pin) \ 32d10acc63SMaxime Ripard PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin) 335f910777SMaxime Ripard 345f910777SMaxime Ripard #define SUNXI_PIN_NAME_MAX_LEN 5 355f910777SMaxime Ripard 365f910777SMaxime Ripard #define BANK_MEM_SIZE 0x24 375f910777SMaxime Ripard #define MUX_REGS_OFFSET 0x0 385f910777SMaxime Ripard #define DATA_REGS_OFFSET 0x10 395f910777SMaxime Ripard #define DLEVEL_REGS_OFFSET 0x14 405f910777SMaxime Ripard #define PULL_REGS_OFFSET 0x1c 415f910777SMaxime Ripard 425f910777SMaxime Ripard #define PINS_PER_BANK 32 435f910777SMaxime Ripard #define MUX_PINS_PER_REG 8 445f910777SMaxime Ripard #define MUX_PINS_BITS 4 455f910777SMaxime Ripard #define MUX_PINS_MASK 0x0f 465f910777SMaxime Ripard #define DATA_PINS_PER_REG 32 475f910777SMaxime Ripard #define DATA_PINS_BITS 1 485f910777SMaxime Ripard #define DATA_PINS_MASK 0x01 495f910777SMaxime Ripard #define DLEVEL_PINS_PER_REG 16 505f910777SMaxime Ripard #define DLEVEL_PINS_BITS 2 515f910777SMaxime Ripard #define DLEVEL_PINS_MASK 0x03 525f910777SMaxime Ripard #define PULL_PINS_PER_REG 16 535f910777SMaxime Ripard #define PULL_PINS_BITS 2 545f910777SMaxime Ripard #define PULL_PINS_MASK 0x03 555f910777SMaxime Ripard 565f910777SMaxime Ripard #define SUNXI_IRQ_NUMBER 32 575f910777SMaxime Ripard 585f910777SMaxime Ripard #define IRQ_CFG_REG 0x200 595f910777SMaxime Ripard #define IRQ_CFG_IRQ_PER_REG 8 605f910777SMaxime Ripard #define IRQ_CFG_IRQ_BITS 4 615f910777SMaxime Ripard #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1) 625f910777SMaxime Ripard #define IRQ_CTRL_REG 0x210 635f910777SMaxime Ripard #define IRQ_CTRL_IRQ_PER_REG 32 645f910777SMaxime Ripard #define IRQ_CTRL_IRQ_BITS 1 655f910777SMaxime Ripard #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1) 665f910777SMaxime Ripard #define IRQ_STATUS_REG 0x214 675f910777SMaxime Ripard #define IRQ_STATUS_IRQ_PER_REG 32 685f910777SMaxime Ripard #define IRQ_STATUS_IRQ_BITS 1 695f910777SMaxime Ripard #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) 705f910777SMaxime Ripard 715f910777SMaxime Ripard #define IRQ_EDGE_RISING 0x00 725f910777SMaxime Ripard #define IRQ_EDGE_FALLING 0x01 735f910777SMaxime Ripard #define IRQ_LEVEL_HIGH 0x02 745f910777SMaxime Ripard #define IRQ_LEVEL_LOW 0x03 755f910777SMaxime Ripard #define IRQ_EDGE_BOTH 0x04 765f910777SMaxime Ripard 775f910777SMaxime Ripard struct sunxi_desc_function { 785f910777SMaxime Ripard const char *name; 795f910777SMaxime Ripard u8 muxval; 805f910777SMaxime Ripard u8 irqnum; 815f910777SMaxime Ripard }; 825f910777SMaxime Ripard 835f910777SMaxime Ripard struct sunxi_desc_pin { 845f910777SMaxime Ripard struct pinctrl_pin_desc pin; 855f910777SMaxime Ripard struct sunxi_desc_function *functions; 865f910777SMaxime Ripard }; 875f910777SMaxime Ripard 885f910777SMaxime Ripard struct sunxi_pinctrl_desc { 895f910777SMaxime Ripard const struct sunxi_desc_pin *pins; 905f910777SMaxime Ripard int npins; 915f910777SMaxime Ripard unsigned pin_base; 925f910777SMaxime Ripard }; 935f910777SMaxime Ripard 945f910777SMaxime Ripard struct sunxi_pinctrl_function { 955f910777SMaxime Ripard const char *name; 965f910777SMaxime Ripard const char **groups; 975f910777SMaxime Ripard unsigned ngroups; 985f910777SMaxime Ripard }; 995f910777SMaxime Ripard 1005f910777SMaxime Ripard struct sunxi_pinctrl_group { 1015f910777SMaxime Ripard const char *name; 1025f910777SMaxime Ripard unsigned long config; 1035f910777SMaxime Ripard unsigned pin; 1045f910777SMaxime Ripard }; 1055f910777SMaxime Ripard 1065f910777SMaxime Ripard struct sunxi_pinctrl { 1075f910777SMaxime Ripard void __iomem *membase; 1085f910777SMaxime Ripard struct gpio_chip *chip; 1095f910777SMaxime Ripard const struct sunxi_pinctrl_desc *desc; 1105f910777SMaxime Ripard struct device *dev; 1115f910777SMaxime Ripard struct irq_domain *domain; 1125f910777SMaxime Ripard struct sunxi_pinctrl_function *functions; 1135f910777SMaxime Ripard unsigned nfunctions; 1145f910777SMaxime Ripard struct sunxi_pinctrl_group *groups; 1155f910777SMaxime Ripard unsigned ngroups; 1165f910777SMaxime Ripard int irq; 1175f910777SMaxime Ripard int irq_array[SUNXI_IRQ_NUMBER]; 1185f910777SMaxime Ripard spinlock_t lock; 1195f910777SMaxime Ripard struct pinctrl_dev *pctl_dev; 1205f910777SMaxime Ripard }; 1215f910777SMaxime Ripard 1225f910777SMaxime Ripard #define SUNXI_PIN(_pin, ...) \ 1235f910777SMaxime Ripard { \ 1245f910777SMaxime Ripard .pin = _pin, \ 1255f910777SMaxime Ripard .functions = (struct sunxi_desc_function[]){ \ 1265f910777SMaxime Ripard __VA_ARGS__, { } }, \ 1275f910777SMaxime Ripard } 1285f910777SMaxime Ripard 1295f910777SMaxime Ripard #define SUNXI_FUNCTION(_val, _name) \ 1305f910777SMaxime Ripard { \ 1315f910777SMaxime Ripard .name = _name, \ 1325f910777SMaxime Ripard .muxval = _val, \ 1335f910777SMaxime Ripard } 1345f910777SMaxime Ripard 1355f910777SMaxime Ripard #define SUNXI_FUNCTION_IRQ(_val, _irq) \ 1365f910777SMaxime Ripard { \ 1375f910777SMaxime Ripard .name = "irq", \ 1385f910777SMaxime Ripard .muxval = _val, \ 1395f910777SMaxime Ripard .irqnum = _irq, \ 1405f910777SMaxime Ripard } 1415f910777SMaxime Ripard 1425f910777SMaxime Ripard /* 1435f910777SMaxime Ripard * The sunXi PIO registers are organized as is: 1445f910777SMaxime Ripard * 0x00 - 0x0c Muxing values. 1455f910777SMaxime Ripard * 8 pins per register, each pin having a 4bits value 1465f910777SMaxime Ripard * 0x10 Pin values 1475f910777SMaxime Ripard * 32 bits per register, each pin corresponding to one bit 1485f910777SMaxime Ripard * 0x14 - 0x18 Drive level 1495f910777SMaxime Ripard * 16 pins per register, each pin having a 2bits value 1505f910777SMaxime Ripard * 0x1c - 0x20 Pull-Up values 1515f910777SMaxime Ripard * 16 pins per register, each pin having a 2bits value 1525f910777SMaxime Ripard * 1535f910777SMaxime Ripard * This is for the first bank. Each bank will have the same layout, 1545f910777SMaxime Ripard * with an offset being a multiple of 0x24. 1555f910777SMaxime Ripard * 1565f910777SMaxime Ripard * The following functions calculate from the pin number the register 1575f910777SMaxime Ripard * and the bit offset that we should access. 1585f910777SMaxime Ripard */ 1595f910777SMaxime Ripard static inline u32 sunxi_mux_reg(u16 pin) 1605f910777SMaxime Ripard { 1615f910777SMaxime Ripard u8 bank = pin / PINS_PER_BANK; 1625f910777SMaxime Ripard u32 offset = bank * BANK_MEM_SIZE; 1635f910777SMaxime Ripard offset += MUX_REGS_OFFSET; 1645f910777SMaxime Ripard offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04; 1655f910777SMaxime Ripard return round_down(offset, 4); 1665f910777SMaxime Ripard } 1675f910777SMaxime Ripard 1685f910777SMaxime Ripard static inline u32 sunxi_mux_offset(u16 pin) 1695f910777SMaxime Ripard { 1705f910777SMaxime Ripard u32 pin_num = pin % MUX_PINS_PER_REG; 1715f910777SMaxime Ripard return pin_num * MUX_PINS_BITS; 1725f910777SMaxime Ripard } 1735f910777SMaxime Ripard 1745f910777SMaxime Ripard static inline u32 sunxi_data_reg(u16 pin) 1755f910777SMaxime Ripard { 1765f910777SMaxime Ripard u8 bank = pin / PINS_PER_BANK; 1775f910777SMaxime Ripard u32 offset = bank * BANK_MEM_SIZE; 1785f910777SMaxime Ripard offset += DATA_REGS_OFFSET; 1795f910777SMaxime Ripard offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04; 1805f910777SMaxime Ripard return round_down(offset, 4); 1815f910777SMaxime Ripard } 1825f910777SMaxime Ripard 1835f910777SMaxime Ripard static inline u32 sunxi_data_offset(u16 pin) 1845f910777SMaxime Ripard { 1855f910777SMaxime Ripard u32 pin_num = pin % DATA_PINS_PER_REG; 1865f910777SMaxime Ripard return pin_num * DATA_PINS_BITS; 1875f910777SMaxime Ripard } 1885f910777SMaxime Ripard 1895f910777SMaxime Ripard static inline u32 sunxi_dlevel_reg(u16 pin) 1905f910777SMaxime Ripard { 1915f910777SMaxime Ripard u8 bank = pin / PINS_PER_BANK; 1925f910777SMaxime Ripard u32 offset = bank * BANK_MEM_SIZE; 1935f910777SMaxime Ripard offset += DLEVEL_REGS_OFFSET; 1945f910777SMaxime Ripard offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04; 1955f910777SMaxime Ripard return round_down(offset, 4); 1965f910777SMaxime Ripard } 1975f910777SMaxime Ripard 1985f910777SMaxime Ripard static inline u32 sunxi_dlevel_offset(u16 pin) 1995f910777SMaxime Ripard { 2005f910777SMaxime Ripard u32 pin_num = pin % DLEVEL_PINS_PER_REG; 2015f910777SMaxime Ripard return pin_num * DLEVEL_PINS_BITS; 2025f910777SMaxime Ripard } 2035f910777SMaxime Ripard 2045f910777SMaxime Ripard static inline u32 sunxi_pull_reg(u16 pin) 2055f910777SMaxime Ripard { 2065f910777SMaxime Ripard u8 bank = pin / PINS_PER_BANK; 2075f910777SMaxime Ripard u32 offset = bank * BANK_MEM_SIZE; 2085f910777SMaxime Ripard offset += PULL_REGS_OFFSET; 2095f910777SMaxime Ripard offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04; 2105f910777SMaxime Ripard return round_down(offset, 4); 2115f910777SMaxime Ripard } 2125f910777SMaxime Ripard 2135f910777SMaxime Ripard static inline u32 sunxi_pull_offset(u16 pin) 2145f910777SMaxime Ripard { 2155f910777SMaxime Ripard u32 pin_num = pin % PULL_PINS_PER_REG; 2165f910777SMaxime Ripard return pin_num * PULL_PINS_BITS; 2175f910777SMaxime Ripard } 2185f910777SMaxime Ripard 2195f910777SMaxime Ripard static inline u32 sunxi_irq_cfg_reg(u16 irq) 2205f910777SMaxime Ripard { 2215f910777SMaxime Ripard u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04; 2225f910777SMaxime Ripard return reg + IRQ_CFG_REG; 2235f910777SMaxime Ripard } 2245f910777SMaxime Ripard 2255f910777SMaxime Ripard static inline u32 sunxi_irq_cfg_offset(u16 irq) 2265f910777SMaxime Ripard { 2275f910777SMaxime Ripard u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG; 2285f910777SMaxime Ripard return irq_num * IRQ_CFG_IRQ_BITS; 2295f910777SMaxime Ripard } 2305f910777SMaxime Ripard 2315f910777SMaxime Ripard static inline u32 sunxi_irq_ctrl_reg(u16 irq) 2325f910777SMaxime Ripard { 2335f910777SMaxime Ripard u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04; 2345f910777SMaxime Ripard return reg + IRQ_CTRL_REG; 2355f910777SMaxime Ripard } 2365f910777SMaxime Ripard 2375f910777SMaxime Ripard static inline u32 sunxi_irq_ctrl_offset(u16 irq) 2385f910777SMaxime Ripard { 2395f910777SMaxime Ripard u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG; 2405f910777SMaxime Ripard return irq_num * IRQ_CTRL_IRQ_BITS; 2415f910777SMaxime Ripard } 2425f910777SMaxime Ripard 2435f910777SMaxime Ripard static inline u32 sunxi_irq_status_reg(u16 irq) 2445f910777SMaxime Ripard { 2455f910777SMaxime Ripard u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04; 2465f910777SMaxime Ripard return reg + IRQ_STATUS_REG; 2475f910777SMaxime Ripard } 2485f910777SMaxime Ripard 2495f910777SMaxime Ripard static inline u32 sunxi_irq_status_offset(u16 irq) 2505f910777SMaxime Ripard { 2515f910777SMaxime Ripard u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG; 2525f910777SMaxime Ripard return irq_num * IRQ_STATUS_IRQ_BITS; 2535f910777SMaxime Ripard } 2545f910777SMaxime Ripard 2555f910777SMaxime Ripard #endif /* __PINCTRL_SUNXI_H */ 256