15f910777SMaxime Ripard /* 25f910777SMaxime Ripard * Allwinner A1X SoCs pinctrl driver. 35f910777SMaxime Ripard * 45f910777SMaxime Ripard * Copyright (C) 2012 Maxime Ripard 55f910777SMaxime Ripard * 65f910777SMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com> 75f910777SMaxime Ripard * 85f910777SMaxime Ripard * This file is licensed under the terms of the GNU General Public 95f910777SMaxime Ripard * License version 2. This program is licensed "as is" without any 105f910777SMaxime Ripard * warranty of any kind, whether express or implied. 115f910777SMaxime Ripard */ 125f910777SMaxime Ripard 135f910777SMaxime Ripard #ifndef __PINCTRL_SUNXI_H 145f910777SMaxime Ripard #define __PINCTRL_SUNXI_H 155f910777SMaxime Ripard 165f910777SMaxime Ripard #include <linux/kernel.h> 175f910777SMaxime Ripard #include <linux/spinlock.h> 185f910777SMaxime Ripard 195f910777SMaxime Ripard #define PA_BASE 0 205f910777SMaxime Ripard #define PB_BASE 32 215f910777SMaxime Ripard #define PC_BASE 64 225f910777SMaxime Ripard #define PD_BASE 96 235f910777SMaxime Ripard #define PE_BASE 128 245f910777SMaxime Ripard #define PF_BASE 160 255f910777SMaxime Ripard #define PG_BASE 192 265f910777SMaxime Ripard #define PH_BASE 224 275f910777SMaxime Ripard #define PI_BASE 256 285f910777SMaxime Ripard #define PL_BASE 352 295f910777SMaxime Ripard #define PM_BASE 384 304f6bd5cfSMaxime Ripard #define PN_BASE 416 315f910777SMaxime Ripard 32d10acc63SMaxime Ripard #define SUNXI_PINCTRL_PIN(bank, pin) \ 33d10acc63SMaxime Ripard PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin) 345f910777SMaxime Ripard 355f910777SMaxime Ripard #define SUNXI_PIN_NAME_MAX_LEN 5 365f910777SMaxime Ripard 375f910777SMaxime Ripard #define BANK_MEM_SIZE 0x24 385f910777SMaxime Ripard #define MUX_REGS_OFFSET 0x0 395f910777SMaxime Ripard #define DATA_REGS_OFFSET 0x10 405f910777SMaxime Ripard #define DLEVEL_REGS_OFFSET 0x14 415f910777SMaxime Ripard #define PULL_REGS_OFFSET 0x1c 425f910777SMaxime Ripard 435f910777SMaxime Ripard #define PINS_PER_BANK 32 445f910777SMaxime Ripard #define MUX_PINS_PER_REG 8 455f910777SMaxime Ripard #define MUX_PINS_BITS 4 465f910777SMaxime Ripard #define MUX_PINS_MASK 0x0f 475f910777SMaxime Ripard #define DATA_PINS_PER_REG 32 485f910777SMaxime Ripard #define DATA_PINS_BITS 1 495f910777SMaxime Ripard #define DATA_PINS_MASK 0x01 505f910777SMaxime Ripard #define DLEVEL_PINS_PER_REG 16 515f910777SMaxime Ripard #define DLEVEL_PINS_BITS 2 525f910777SMaxime Ripard #define DLEVEL_PINS_MASK 0x03 535f910777SMaxime Ripard #define PULL_PINS_PER_REG 16 545f910777SMaxime Ripard #define PULL_PINS_BITS 2 555f910777SMaxime Ripard #define PULL_PINS_MASK 0x03 565f910777SMaxime Ripard 57aebdc8abSMaxime Ripard #define IRQ_PER_BANK 32 585f910777SMaxime Ripard 595f910777SMaxime Ripard #define IRQ_CFG_REG 0x200 605f910777SMaxime Ripard #define IRQ_CFG_IRQ_PER_REG 8 615f910777SMaxime Ripard #define IRQ_CFG_IRQ_BITS 4 625f910777SMaxime Ripard #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1) 635f910777SMaxime Ripard #define IRQ_CTRL_REG 0x210 645f910777SMaxime Ripard #define IRQ_CTRL_IRQ_PER_REG 32 655f910777SMaxime Ripard #define IRQ_CTRL_IRQ_BITS 1 665f910777SMaxime Ripard #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1) 675f910777SMaxime Ripard #define IRQ_STATUS_REG 0x214 685f910777SMaxime Ripard #define IRQ_STATUS_IRQ_PER_REG 32 695f910777SMaxime Ripard #define IRQ_STATUS_IRQ_BITS 1 705f910777SMaxime Ripard #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) 715f910777SMaxime Ripard 727c926492SMaxime Ripard #define IRQ_DEBOUNCE_REG 0x218 737c926492SMaxime Ripard 74aebdc8abSMaxime Ripard #define IRQ_MEM_SIZE 0x20 75aebdc8abSMaxime Ripard 765f910777SMaxime Ripard #define IRQ_EDGE_RISING 0x00 775f910777SMaxime Ripard #define IRQ_EDGE_FALLING 0x01 785f910777SMaxime Ripard #define IRQ_LEVEL_HIGH 0x02 795f910777SMaxime Ripard #define IRQ_LEVEL_LOW 0x03 805f910777SMaxime Ripard #define IRQ_EDGE_BOTH 0x04 815f910777SMaxime Ripard 82ef6d24ccSHans de Goede #define SUN4I_FUNC_INPUT 0 83ef6d24ccSHans de Goede #define SUN4I_FUNC_IRQ 6 84ef6d24ccSHans de Goede 85858f559fSMaxime Ripard #define PINCTRL_SUN5I_A10S BIT(1) 86858f559fSMaxime Ripard #define PINCTRL_SUN5I_A13 BIT(2) 87858f559fSMaxime Ripard #define PINCTRL_SUN5I_GR8 BIT(3) 884924982eSChen-Yu Tsai #define PINCTRL_SUN6I_A31 BIT(4) 894924982eSChen-Yu Tsai #define PINCTRL_SUN6I_A31S BIT(5) 9088798ba2SIcenowy Zheng #define PINCTRL_SUN4I_A10 BIT(6) 9188798ba2SIcenowy Zheng #define PINCTRL_SUN7I_A20 BIT(7) 9288798ba2SIcenowy Zheng #define PINCTRL_SUN8I_R40 BIT(8) 93858f559fSMaxime Ripard 945f910777SMaxime Ripard struct sunxi_desc_function { 95578db85fSMaxime Ripard unsigned long variant; 965f910777SMaxime Ripard const char *name; 975f910777SMaxime Ripard u8 muxval; 986e1c3023SMaxime Ripard u8 irqbank; 995f910777SMaxime Ripard u8 irqnum; 1005f910777SMaxime Ripard }; 1015f910777SMaxime Ripard 1025f910777SMaxime Ripard struct sunxi_desc_pin { 1035f910777SMaxime Ripard struct pinctrl_pin_desc pin; 104578db85fSMaxime Ripard unsigned long variant; 1055f910777SMaxime Ripard struct sunxi_desc_function *functions; 1065f910777SMaxime Ripard }; 1075f910777SMaxime Ripard 1085f910777SMaxime Ripard struct sunxi_pinctrl_desc { 1095f910777SMaxime Ripard const struct sunxi_desc_pin *pins; 1105f910777SMaxime Ripard int npins; 1115f910777SMaxime Ripard unsigned pin_base; 1128966ada2SMaxime Ripard unsigned irq_banks; 1135e7515baSHans de Goede unsigned irq_bank_base; 114ef6d24ccSHans de Goede bool irq_read_needs_mux; 1155f910777SMaxime Ripard }; 1165f910777SMaxime Ripard 1175f910777SMaxime Ripard struct sunxi_pinctrl_function { 1185f910777SMaxime Ripard const char *name; 1195f910777SMaxime Ripard const char **groups; 1205f910777SMaxime Ripard unsigned ngroups; 1215f910777SMaxime Ripard }; 1225f910777SMaxime Ripard 1235f910777SMaxime Ripard struct sunxi_pinctrl_group { 1245f910777SMaxime Ripard const char *name; 1255f910777SMaxime Ripard unsigned pin; 1265f910777SMaxime Ripard }; 1275f910777SMaxime Ripard 1285f910777SMaxime Ripard struct sunxi_pinctrl { 1295f910777SMaxime Ripard void __iomem *membase; 1305f910777SMaxime Ripard struct gpio_chip *chip; 1315f910777SMaxime Ripard const struct sunxi_pinctrl_desc *desc; 1325f910777SMaxime Ripard struct device *dev; 1335f910777SMaxime Ripard struct irq_domain *domain; 1345f910777SMaxime Ripard struct sunxi_pinctrl_function *functions; 1355f910777SMaxime Ripard unsigned nfunctions; 1365f910777SMaxime Ripard struct sunxi_pinctrl_group *groups; 1375f910777SMaxime Ripard unsigned ngroups; 138aebdc8abSMaxime Ripard int *irq; 139aebdc8abSMaxime Ripard unsigned *irq_array; 140f658ed36SJulia Cartwright raw_spinlock_t lock; 1415f910777SMaxime Ripard struct pinctrl_dev *pctl_dev; 142578db85fSMaxime Ripard unsigned long variant; 1435f910777SMaxime Ripard }; 1445f910777SMaxime Ripard 1455f910777SMaxime Ripard #define SUNXI_PIN(_pin, ...) \ 1465f910777SMaxime Ripard { \ 1475f910777SMaxime Ripard .pin = _pin, \ 1485f910777SMaxime Ripard .functions = (struct sunxi_desc_function[]){ \ 1495f910777SMaxime Ripard __VA_ARGS__, { } }, \ 1505f910777SMaxime Ripard } 1515f910777SMaxime Ripard 152578db85fSMaxime Ripard #define SUNXI_PIN_VARIANT(_pin, _variant, ...) \ 153578db85fSMaxime Ripard { \ 154578db85fSMaxime Ripard .pin = _pin, \ 155578db85fSMaxime Ripard .variant = _variant, \ 156578db85fSMaxime Ripard .functions = (struct sunxi_desc_function[]){ \ 157578db85fSMaxime Ripard __VA_ARGS__, { } }, \ 158578db85fSMaxime Ripard } 159578db85fSMaxime Ripard 1605f910777SMaxime Ripard #define SUNXI_FUNCTION(_val, _name) \ 1615f910777SMaxime Ripard { \ 1625f910777SMaxime Ripard .name = _name, \ 1635f910777SMaxime Ripard .muxval = _val, \ 1645f910777SMaxime Ripard } 1655f910777SMaxime Ripard 166578db85fSMaxime Ripard #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \ 167578db85fSMaxime Ripard { \ 168578db85fSMaxime Ripard .name = _name, \ 169578db85fSMaxime Ripard .muxval = _val, \ 170578db85fSMaxime Ripard .variant = _variant, \ 171578db85fSMaxime Ripard } 172578db85fSMaxime Ripard 1735f910777SMaxime Ripard #define SUNXI_FUNCTION_IRQ(_val, _irq) \ 1745f910777SMaxime Ripard { \ 1755f910777SMaxime Ripard .name = "irq", \ 1765f910777SMaxime Ripard .muxval = _val, \ 1775f910777SMaxime Ripard .irqnum = _irq, \ 1785f910777SMaxime Ripard } 1795f910777SMaxime Ripard 1806e1c3023SMaxime Ripard #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ 1816e1c3023SMaxime Ripard { \ 1826e1c3023SMaxime Ripard .name = "irq", \ 1836e1c3023SMaxime Ripard .muxval = _val, \ 1846e1c3023SMaxime Ripard .irqbank = _bank, \ 1856e1c3023SMaxime Ripard .irqnum = _irq, \ 1866e1c3023SMaxime Ripard } 1876e1c3023SMaxime Ripard 1885f910777SMaxime Ripard /* 1895f910777SMaxime Ripard * The sunXi PIO registers are organized as is: 1905f910777SMaxime Ripard * 0x00 - 0x0c Muxing values. 1915f910777SMaxime Ripard * 8 pins per register, each pin having a 4bits value 1925f910777SMaxime Ripard * 0x10 Pin values 1935f910777SMaxime Ripard * 32 bits per register, each pin corresponding to one bit 1945f910777SMaxime Ripard * 0x14 - 0x18 Drive level 1955f910777SMaxime Ripard * 16 pins per register, each pin having a 2bits value 1965f910777SMaxime Ripard * 0x1c - 0x20 Pull-Up values 1975f910777SMaxime Ripard * 16 pins per register, each pin having a 2bits value 1985f910777SMaxime Ripard * 1995f910777SMaxime Ripard * This is for the first bank. Each bank will have the same layout, 2005f910777SMaxime Ripard * with an offset being a multiple of 0x24. 2015f910777SMaxime Ripard * 2025f910777SMaxime Ripard * The following functions calculate from the pin number the register 2035f910777SMaxime Ripard * and the bit offset that we should access. 2045f910777SMaxime Ripard */ 2055f910777SMaxime Ripard static inline u32 sunxi_mux_reg(u16 pin) 2065f910777SMaxime Ripard { 2075f910777SMaxime Ripard u8 bank = pin / PINS_PER_BANK; 2085f910777SMaxime Ripard u32 offset = bank * BANK_MEM_SIZE; 2095f910777SMaxime Ripard offset += MUX_REGS_OFFSET; 2105f910777SMaxime Ripard offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04; 2115f910777SMaxime Ripard return round_down(offset, 4); 2125f910777SMaxime Ripard } 2135f910777SMaxime Ripard 2145f910777SMaxime Ripard static inline u32 sunxi_mux_offset(u16 pin) 2155f910777SMaxime Ripard { 2165f910777SMaxime Ripard u32 pin_num = pin % MUX_PINS_PER_REG; 2175f910777SMaxime Ripard return pin_num * MUX_PINS_BITS; 2185f910777SMaxime Ripard } 2195f910777SMaxime Ripard 2205f910777SMaxime Ripard static inline u32 sunxi_data_reg(u16 pin) 2215f910777SMaxime Ripard { 2225f910777SMaxime Ripard u8 bank = pin / PINS_PER_BANK; 2235f910777SMaxime Ripard u32 offset = bank * BANK_MEM_SIZE; 2245f910777SMaxime Ripard offset += DATA_REGS_OFFSET; 2255f910777SMaxime Ripard offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04; 2265f910777SMaxime Ripard return round_down(offset, 4); 2275f910777SMaxime Ripard } 2285f910777SMaxime Ripard 2295f910777SMaxime Ripard static inline u32 sunxi_data_offset(u16 pin) 2305f910777SMaxime Ripard { 2315f910777SMaxime Ripard u32 pin_num = pin % DATA_PINS_PER_REG; 2325f910777SMaxime Ripard return pin_num * DATA_PINS_BITS; 2335f910777SMaxime Ripard } 2345f910777SMaxime Ripard 2355f910777SMaxime Ripard static inline u32 sunxi_dlevel_reg(u16 pin) 2365f910777SMaxime Ripard { 2375f910777SMaxime Ripard u8 bank = pin / PINS_PER_BANK; 2385f910777SMaxime Ripard u32 offset = bank * BANK_MEM_SIZE; 2395f910777SMaxime Ripard offset += DLEVEL_REGS_OFFSET; 2405f910777SMaxime Ripard offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04; 2415f910777SMaxime Ripard return round_down(offset, 4); 2425f910777SMaxime Ripard } 2435f910777SMaxime Ripard 2445f910777SMaxime Ripard static inline u32 sunxi_dlevel_offset(u16 pin) 2455f910777SMaxime Ripard { 2465f910777SMaxime Ripard u32 pin_num = pin % DLEVEL_PINS_PER_REG; 2475f910777SMaxime Ripard return pin_num * DLEVEL_PINS_BITS; 2485f910777SMaxime Ripard } 2495f910777SMaxime Ripard 2505f910777SMaxime Ripard static inline u32 sunxi_pull_reg(u16 pin) 2515f910777SMaxime Ripard { 2525f910777SMaxime Ripard u8 bank = pin / PINS_PER_BANK; 2535f910777SMaxime Ripard u32 offset = bank * BANK_MEM_SIZE; 2545f910777SMaxime Ripard offset += PULL_REGS_OFFSET; 2555f910777SMaxime Ripard offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04; 2565f910777SMaxime Ripard return round_down(offset, 4); 2575f910777SMaxime Ripard } 2585f910777SMaxime Ripard 2595f910777SMaxime Ripard static inline u32 sunxi_pull_offset(u16 pin) 2605f910777SMaxime Ripard { 2615f910777SMaxime Ripard u32 pin_num = pin % PULL_PINS_PER_REG; 2625f910777SMaxime Ripard return pin_num * PULL_PINS_BITS; 2635f910777SMaxime Ripard } 2645f910777SMaxime Ripard 2655e7515baSHans de Goede static inline u32 sunxi_irq_cfg_reg(u16 irq, unsigned bank_base) 2665f910777SMaxime Ripard { 267aebdc8abSMaxime Ripard u8 bank = irq / IRQ_PER_BANK; 268aebdc8abSMaxime Ripard u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; 269aebdc8abSMaxime Ripard 2705e7515baSHans de Goede return IRQ_CFG_REG + (bank_base + bank) * IRQ_MEM_SIZE + reg; 2715f910777SMaxime Ripard } 2725f910777SMaxime Ripard 2735f910777SMaxime Ripard static inline u32 sunxi_irq_cfg_offset(u16 irq) 2745f910777SMaxime Ripard { 2755f910777SMaxime Ripard u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG; 2765f910777SMaxime Ripard return irq_num * IRQ_CFG_IRQ_BITS; 2775f910777SMaxime Ripard } 2785f910777SMaxime Ripard 2795e7515baSHans de Goede static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank, unsigned bank_base) 280aebdc8abSMaxime Ripard { 2815e7515baSHans de Goede return IRQ_CTRL_REG + (bank_base + bank) * IRQ_MEM_SIZE; 282aebdc8abSMaxime Ripard } 283aebdc8abSMaxime Ripard 2845e7515baSHans de Goede static inline u32 sunxi_irq_ctrl_reg(u16 irq, unsigned bank_base) 2855f910777SMaxime Ripard { 286aebdc8abSMaxime Ripard u8 bank = irq / IRQ_PER_BANK; 287aebdc8abSMaxime Ripard 2885e7515baSHans de Goede return sunxi_irq_ctrl_reg_from_bank(bank, bank_base); 2895f910777SMaxime Ripard } 2905f910777SMaxime Ripard 2915f910777SMaxime Ripard static inline u32 sunxi_irq_ctrl_offset(u16 irq) 2925f910777SMaxime Ripard { 2935f910777SMaxime Ripard u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG; 2945f910777SMaxime Ripard return irq_num * IRQ_CTRL_IRQ_BITS; 2955f910777SMaxime Ripard } 2965f910777SMaxime Ripard 2977c926492SMaxime Ripard static inline u32 sunxi_irq_debounce_reg_from_bank(u8 bank, unsigned bank_base) 2987c926492SMaxime Ripard { 2997c926492SMaxime Ripard return IRQ_DEBOUNCE_REG + (bank_base + bank) * IRQ_MEM_SIZE; 3007c926492SMaxime Ripard } 3017c926492SMaxime Ripard 3025e7515baSHans de Goede static inline u32 sunxi_irq_status_reg_from_bank(u8 bank, unsigned bank_base) 303aebdc8abSMaxime Ripard { 3045e7515baSHans de Goede return IRQ_STATUS_REG + (bank_base + bank) * IRQ_MEM_SIZE; 305aebdc8abSMaxime Ripard } 306aebdc8abSMaxime Ripard 3075e7515baSHans de Goede static inline u32 sunxi_irq_status_reg(u16 irq, unsigned bank_base) 3085f910777SMaxime Ripard { 309aebdc8abSMaxime Ripard u8 bank = irq / IRQ_PER_BANK; 310aebdc8abSMaxime Ripard 3115e7515baSHans de Goede return sunxi_irq_status_reg_from_bank(bank, bank_base); 3125f910777SMaxime Ripard } 3135f910777SMaxime Ripard 3145f910777SMaxime Ripard static inline u32 sunxi_irq_status_offset(u16 irq) 3155f910777SMaxime Ripard { 3165f910777SMaxime Ripard u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG; 3175f910777SMaxime Ripard return irq_num * IRQ_STATUS_IRQ_BITS; 3185f910777SMaxime Ripard } 3195f910777SMaxime Ripard 320578db85fSMaxime Ripard int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, 321578db85fSMaxime Ripard const struct sunxi_pinctrl_desc *desc, 322578db85fSMaxime Ripard unsigned long variant); 323578db85fSMaxime Ripard 324578db85fSMaxime Ripard #define sunxi_pinctrl_init(_dev, _desc) \ 325578db85fSMaxime Ripard sunxi_pinctrl_init_with_variant(_dev, _desc, 0) 3262284ba6bSMaxime Ripard 3275f910777SMaxime Ripard #endif /* __PINCTRL_SUNXI_H */ 328