15f910777SMaxime Ripard /* 25f910777SMaxime Ripard * Allwinner A1X SoCs pinctrl driver. 35f910777SMaxime Ripard * 45f910777SMaxime Ripard * Copyright (C) 2012 Maxime Ripard 55f910777SMaxime Ripard * 65f910777SMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com> 75f910777SMaxime Ripard * 85f910777SMaxime Ripard * This file is licensed under the terms of the GNU General Public 95f910777SMaxime Ripard * License version 2. This program is licensed "as is" without any 105f910777SMaxime Ripard * warranty of any kind, whether express or implied. 115f910777SMaxime Ripard */ 125f910777SMaxime Ripard 135f910777SMaxime Ripard #ifndef __PINCTRL_SUNXI_H 145f910777SMaxime Ripard #define __PINCTRL_SUNXI_H 155f910777SMaxime Ripard 165f910777SMaxime Ripard #include <linux/kernel.h> 175f910777SMaxime Ripard #include <linux/spinlock.h> 185f910777SMaxime Ripard 195f910777SMaxime Ripard #define PA_BASE 0 205f910777SMaxime Ripard #define PB_BASE 32 215f910777SMaxime Ripard #define PC_BASE 64 225f910777SMaxime Ripard #define PD_BASE 96 235f910777SMaxime Ripard #define PE_BASE 128 245f910777SMaxime Ripard #define PF_BASE 160 255f910777SMaxime Ripard #define PG_BASE 192 265f910777SMaxime Ripard #define PH_BASE 224 275f910777SMaxime Ripard #define PI_BASE 256 285f910777SMaxime Ripard #define PL_BASE 352 295f910777SMaxime Ripard #define PM_BASE 384 304f6bd5cfSMaxime Ripard #define PN_BASE 416 315f910777SMaxime Ripard 32d10acc63SMaxime Ripard #define SUNXI_PINCTRL_PIN(bank, pin) \ 33d10acc63SMaxime Ripard PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin) 345f910777SMaxime Ripard 355f910777SMaxime Ripard #define SUNXI_PIN_NAME_MAX_LEN 5 365f910777SMaxime Ripard 375f910777SMaxime Ripard #define BANK_MEM_SIZE 0x24 385f910777SMaxime Ripard #define MUX_REGS_OFFSET 0x0 390bb95ae2SSamuel Holland #define MUX_FIELD_WIDTH 4 405f910777SMaxime Ripard #define DATA_REGS_OFFSET 0x10 410bb95ae2SSamuel Holland #define DATA_FIELD_WIDTH 1 425f910777SMaxime Ripard #define DLEVEL_REGS_OFFSET 0x14 430bb95ae2SSamuel Holland #define DLEVEL_FIELD_WIDTH 2 445f910777SMaxime Ripard #define PULL_REGS_OFFSET 0x1c 450bb95ae2SSamuel Holland #define PULL_FIELD_WIDTH 2 465f910777SMaxime Ripard 475f910777SMaxime Ripard #define PINS_PER_BANK 32 485f910777SMaxime Ripard 49aebdc8abSMaxime Ripard #define IRQ_PER_BANK 32 505f910777SMaxime Ripard 515f910777SMaxime Ripard #define IRQ_CFG_REG 0x200 525f910777SMaxime Ripard #define IRQ_CFG_IRQ_PER_REG 8 535f910777SMaxime Ripard #define IRQ_CFG_IRQ_BITS 4 545f910777SMaxime Ripard #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1) 555f910777SMaxime Ripard #define IRQ_CTRL_REG 0x210 565f910777SMaxime Ripard #define IRQ_CTRL_IRQ_PER_REG 32 575f910777SMaxime Ripard #define IRQ_CTRL_IRQ_BITS 1 585f910777SMaxime Ripard #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1) 595f910777SMaxime Ripard #define IRQ_STATUS_REG 0x214 605f910777SMaxime Ripard #define IRQ_STATUS_IRQ_PER_REG 32 615f910777SMaxime Ripard #define IRQ_STATUS_IRQ_BITS 1 625f910777SMaxime Ripard #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) 635f910777SMaxime Ripard 647c926492SMaxime Ripard #define IRQ_DEBOUNCE_REG 0x218 657c926492SMaxime Ripard 66aebdc8abSMaxime Ripard #define IRQ_MEM_SIZE 0x20 67aebdc8abSMaxime Ripard 685f910777SMaxime Ripard #define IRQ_EDGE_RISING 0x00 695f910777SMaxime Ripard #define IRQ_EDGE_FALLING 0x01 705f910777SMaxime Ripard #define IRQ_LEVEL_HIGH 0x02 715f910777SMaxime Ripard #define IRQ_LEVEL_LOW 0x03 725f910777SMaxime Ripard #define IRQ_EDGE_BOTH 0x04 735f910777SMaxime Ripard 74402bfb3cSChen-Yu Tsai #define GRP_CFG_REG 0x300 75402bfb3cSChen-Yu Tsai 76402bfb3cSChen-Yu Tsai #define IO_BIAS_MASK GENMASK(3, 0) 77402bfb3cSChen-Yu Tsai 78ef6d24ccSHans de Goede #define SUN4I_FUNC_INPUT 0 79ef6d24ccSHans de Goede #define SUN4I_FUNC_IRQ 6 80ef6d24ccSHans de Goede 81858f559fSMaxime Ripard #define PINCTRL_SUN5I_A10S BIT(1) 82858f559fSMaxime Ripard #define PINCTRL_SUN5I_A13 BIT(2) 83858f559fSMaxime Ripard #define PINCTRL_SUN5I_GR8 BIT(3) 844924982eSChen-Yu Tsai #define PINCTRL_SUN6I_A31 BIT(4) 854924982eSChen-Yu Tsai #define PINCTRL_SUN6I_A31S BIT(5) 8688798ba2SIcenowy Zheng #define PINCTRL_SUN4I_A10 BIT(6) 8788798ba2SIcenowy Zheng #define PINCTRL_SUN7I_A20 BIT(7) 8888798ba2SIcenowy Zheng #define PINCTRL_SUN8I_R40 BIT(8) 89fb18f188SIcenowy Zheng #define PINCTRL_SUN8I_V3 BIT(9) 90fb18f188SIcenowy Zheng #define PINCTRL_SUN8I_V3S BIT(10) 91858f559fSMaxime Ripard 92cc62383fSOndrej Jirman #define PIO_POW_MOD_SEL_REG 0x340 9388df36f2SSamuel Holland #define PIO_POW_MOD_CTL_REG 0x344 94cc62383fSOndrej Jirman 95f7275345SOndrej Jirman enum sunxi_desc_bias_voltage { 96f7275345SOndrej Jirman BIAS_VOLTAGE_NONE, 97f7275345SOndrej Jirman /* 98f7275345SOndrej Jirman * Bias voltage configuration is done through 99f7275345SOndrej Jirman * Pn_GRP_CONFIG registers, as seen on A80 SoC. 100f7275345SOndrej Jirman */ 101f7275345SOndrej Jirman BIAS_VOLTAGE_GRP_CONFIG, 102cc62383fSOndrej Jirman /* 103cc62383fSOndrej Jirman * Bias voltage is set through PIO_POW_MOD_SEL_REG 104cc62383fSOndrej Jirman * register, as seen on H6 SoC, for example. 105cc62383fSOndrej Jirman */ 106cc62383fSOndrej Jirman BIAS_VOLTAGE_PIO_POW_MODE_SEL, 10788df36f2SSamuel Holland /* 10888df36f2SSamuel Holland * Bias voltage is set through PIO_POW_MOD_SEL_REG 10988df36f2SSamuel Holland * and PIO_POW_MOD_CTL_REG register, as seen on 11088df36f2SSamuel Holland * A100 and D1 SoC, for example. 11188df36f2SSamuel Holland */ 11288df36f2SSamuel Holland BIAS_VOLTAGE_PIO_POW_MODE_CTL, 113f7275345SOndrej Jirman }; 114f7275345SOndrej Jirman 1155f910777SMaxime Ripard struct sunxi_desc_function { 116578db85fSMaxime Ripard unsigned long variant; 1175f910777SMaxime Ripard const char *name; 1185f910777SMaxime Ripard u8 muxval; 1196e1c3023SMaxime Ripard u8 irqbank; 1205f910777SMaxime Ripard u8 irqnum; 1215f910777SMaxime Ripard }; 1225f910777SMaxime Ripard 1235f910777SMaxime Ripard struct sunxi_desc_pin { 1245f910777SMaxime Ripard struct pinctrl_pin_desc pin; 125578db85fSMaxime Ripard unsigned long variant; 1265f910777SMaxime Ripard struct sunxi_desc_function *functions; 1275f910777SMaxime Ripard }; 1285f910777SMaxime Ripard 1295f910777SMaxime Ripard struct sunxi_pinctrl_desc { 1305f910777SMaxime Ripard const struct sunxi_desc_pin *pins; 1315f910777SMaxime Ripard int npins; 1325f910777SMaxime Ripard unsigned pin_base; 1338966ada2SMaxime Ripard unsigned irq_banks; 13435817d34SIcenowy Zheng const unsigned int *irq_bank_map; 135ef6d24ccSHans de Goede bool irq_read_needs_mux; 136aae842a3SMaxime Ripard bool disable_strict_mode; 137f7275345SOndrej Jirman enum sunxi_desc_bias_voltage io_bias_cfg_variant; 1385f910777SMaxime Ripard }; 1395f910777SMaxime Ripard 1405f910777SMaxime Ripard struct sunxi_pinctrl_function { 1415f910777SMaxime Ripard const char *name; 1425f910777SMaxime Ripard const char **groups; 1435f910777SMaxime Ripard unsigned ngroups; 1445f910777SMaxime Ripard }; 1455f910777SMaxime Ripard 1465f910777SMaxime Ripard struct sunxi_pinctrl_group { 1475f910777SMaxime Ripard const char *name; 1485f910777SMaxime Ripard unsigned pin; 1495f910777SMaxime Ripard }; 1505f910777SMaxime Ripard 1519a2a566aSMaxime Ripard struct sunxi_pinctrl_regulator { 1529a2a566aSMaxime Ripard struct regulator *regulator; 1539a2a566aSMaxime Ripard refcount_t refcount; 1549a2a566aSMaxime Ripard }; 1559a2a566aSMaxime Ripard 1565f910777SMaxime Ripard struct sunxi_pinctrl { 1575f910777SMaxime Ripard void __iomem *membase; 1585f910777SMaxime Ripard struct gpio_chip *chip; 1595f910777SMaxime Ripard const struct sunxi_pinctrl_desc *desc; 1605f910777SMaxime Ripard struct device *dev; 161ca443844SChen-Yu Tsai struct sunxi_pinctrl_regulator regulators[9]; 1625f910777SMaxime Ripard struct irq_domain *domain; 1635f910777SMaxime Ripard struct sunxi_pinctrl_function *functions; 1645f910777SMaxime Ripard unsigned nfunctions; 1655f910777SMaxime Ripard struct sunxi_pinctrl_group *groups; 1665f910777SMaxime Ripard unsigned ngroups; 167aebdc8abSMaxime Ripard int *irq; 168aebdc8abSMaxime Ripard unsigned *irq_array; 169f658ed36SJulia Cartwright raw_spinlock_t lock; 1705f910777SMaxime Ripard struct pinctrl_dev *pctl_dev; 171578db85fSMaxime Ripard unsigned long variant; 172*622b681eSSamuel Holland u32 bank_mem_size; 173*622b681eSSamuel Holland u32 pull_regs_offset; 174*622b681eSSamuel Holland u32 dlevel_field_width; 1755f910777SMaxime Ripard }; 1765f910777SMaxime Ripard 1775f910777SMaxime Ripard #define SUNXI_PIN(_pin, ...) \ 1785f910777SMaxime Ripard { \ 1795f910777SMaxime Ripard .pin = _pin, \ 1805f910777SMaxime Ripard .functions = (struct sunxi_desc_function[]){ \ 1815f910777SMaxime Ripard __VA_ARGS__, { } }, \ 1825f910777SMaxime Ripard } 1835f910777SMaxime Ripard 184578db85fSMaxime Ripard #define SUNXI_PIN_VARIANT(_pin, _variant, ...) \ 185578db85fSMaxime Ripard { \ 186578db85fSMaxime Ripard .pin = _pin, \ 187578db85fSMaxime Ripard .variant = _variant, \ 188578db85fSMaxime Ripard .functions = (struct sunxi_desc_function[]){ \ 189578db85fSMaxime Ripard __VA_ARGS__, { } }, \ 190578db85fSMaxime Ripard } 191578db85fSMaxime Ripard 1925f910777SMaxime Ripard #define SUNXI_FUNCTION(_val, _name) \ 1935f910777SMaxime Ripard { \ 1945f910777SMaxime Ripard .name = _name, \ 1955f910777SMaxime Ripard .muxval = _val, \ 1965f910777SMaxime Ripard } 1975f910777SMaxime Ripard 198578db85fSMaxime Ripard #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \ 199578db85fSMaxime Ripard { \ 200578db85fSMaxime Ripard .name = _name, \ 201578db85fSMaxime Ripard .muxval = _val, \ 202578db85fSMaxime Ripard .variant = _variant, \ 203578db85fSMaxime Ripard } 204578db85fSMaxime Ripard 2055f910777SMaxime Ripard #define SUNXI_FUNCTION_IRQ(_val, _irq) \ 2065f910777SMaxime Ripard { \ 2075f910777SMaxime Ripard .name = "irq", \ 2085f910777SMaxime Ripard .muxval = _val, \ 2095f910777SMaxime Ripard .irqnum = _irq, \ 2105f910777SMaxime Ripard } 2115f910777SMaxime Ripard 2126e1c3023SMaxime Ripard #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ 2136e1c3023SMaxime Ripard { \ 2146e1c3023SMaxime Ripard .name = "irq", \ 2156e1c3023SMaxime Ripard .muxval = _val, \ 2166e1c3023SMaxime Ripard .irqbank = _bank, \ 2176e1c3023SMaxime Ripard .irqnum = _irq, \ 2186e1c3023SMaxime Ripard } 2196e1c3023SMaxime Ripard 22029dfc6bbSIcenowy Zheng static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank) 22129dfc6bbSIcenowy Zheng { 22235817d34SIcenowy Zheng if (!desc->irq_bank_map) 22335817d34SIcenowy Zheng return bank; 22435817d34SIcenowy Zheng else 22535817d34SIcenowy Zheng return desc->irq_bank_map[bank]; 22629dfc6bbSIcenowy Zheng } 22729dfc6bbSIcenowy Zheng 2284b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc, 2294b0d6c5aSIcenowy Zheng u16 irq) 2305f910777SMaxime Ripard { 231aebdc8abSMaxime Ripard u8 bank = irq / IRQ_PER_BANK; 232aebdc8abSMaxime Ripard u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; 233aebdc8abSMaxime Ripard 23429dfc6bbSIcenowy Zheng return IRQ_CFG_REG + 23529dfc6bbSIcenowy Zheng sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg; 2365f910777SMaxime Ripard } 2375f910777SMaxime Ripard 2385f910777SMaxime Ripard static inline u32 sunxi_irq_cfg_offset(u16 irq) 2395f910777SMaxime Ripard { 2405f910777SMaxime Ripard u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG; 2415f910777SMaxime Ripard return irq_num * IRQ_CFG_IRQ_BITS; 2425f910777SMaxime Ripard } 2435f910777SMaxime Ripard 2444b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 245aebdc8abSMaxime Ripard { 24629dfc6bbSIcenowy Zheng return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 247aebdc8abSMaxime Ripard } 248aebdc8abSMaxime Ripard 2494b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc, 2504b0d6c5aSIcenowy Zheng u16 irq) 2515f910777SMaxime Ripard { 252aebdc8abSMaxime Ripard u8 bank = irq / IRQ_PER_BANK; 253aebdc8abSMaxime Ripard 2544b0d6c5aSIcenowy Zheng return sunxi_irq_ctrl_reg_from_bank(desc, bank); 2555f910777SMaxime Ripard } 2565f910777SMaxime Ripard 2575f910777SMaxime Ripard static inline u32 sunxi_irq_ctrl_offset(u16 irq) 2585f910777SMaxime Ripard { 2595f910777SMaxime Ripard u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG; 2605f910777SMaxime Ripard return irq_num * IRQ_CTRL_IRQ_BITS; 2615f910777SMaxime Ripard } 2625f910777SMaxime Ripard 2634b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 2647c926492SMaxime Ripard { 26529dfc6bbSIcenowy Zheng return IRQ_DEBOUNCE_REG + 26629dfc6bbSIcenowy Zheng sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 2677c926492SMaxime Ripard } 2687c926492SMaxime Ripard 2694b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 270aebdc8abSMaxime Ripard { 27129dfc6bbSIcenowy Zheng return IRQ_STATUS_REG + 27229dfc6bbSIcenowy Zheng sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 273aebdc8abSMaxime Ripard } 274aebdc8abSMaxime Ripard 2754b0d6c5aSIcenowy Zheng static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc, 2764b0d6c5aSIcenowy Zheng u16 irq) 2775f910777SMaxime Ripard { 278aebdc8abSMaxime Ripard u8 bank = irq / IRQ_PER_BANK; 279aebdc8abSMaxime Ripard 2804b0d6c5aSIcenowy Zheng return sunxi_irq_status_reg_from_bank(desc, bank); 2815f910777SMaxime Ripard } 2825f910777SMaxime Ripard 2835f910777SMaxime Ripard static inline u32 sunxi_irq_status_offset(u16 irq) 2845f910777SMaxime Ripard { 2855f910777SMaxime Ripard u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG; 2865f910777SMaxime Ripard return irq_num * IRQ_STATUS_IRQ_BITS; 2875f910777SMaxime Ripard } 2885f910777SMaxime Ripard 289402bfb3cSChen-Yu Tsai static inline u32 sunxi_grp_config_reg(u16 pin) 290402bfb3cSChen-Yu Tsai { 291402bfb3cSChen-Yu Tsai u8 bank = pin / PINS_PER_BANK; 292402bfb3cSChen-Yu Tsai 293402bfb3cSChen-Yu Tsai return GRP_CFG_REG + bank * 0x4; 294402bfb3cSChen-Yu Tsai } 295402bfb3cSChen-Yu Tsai 296578db85fSMaxime Ripard int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, 297578db85fSMaxime Ripard const struct sunxi_pinctrl_desc *desc, 298578db85fSMaxime Ripard unsigned long variant); 299578db85fSMaxime Ripard 300578db85fSMaxime Ripard #define sunxi_pinctrl_init(_dev, _desc) \ 301578db85fSMaxime Ripard sunxi_pinctrl_init_with_variant(_dev, _desc, 0) 3022284ba6bSMaxime Ripard 3035f910777SMaxime Ripard #endif /* __PINCTRL_SUNXI_H */ 304