1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/io.h> 14 #include <linux/clk.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/irqdomain.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/export.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_device.h> 22 #include <linux/of_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/machine.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinconf-generic.h> 27 #include <linux/pinctrl/pinmux.h> 28 #include <linux/platform_device.h> 29 #include <linux/slab.h> 30 31 #include <dt-bindings/pinctrl/sun4i-a10.h> 32 33 #include "../core.h" 34 #include "pinctrl-sunxi.h" 35 36 static struct irq_chip sunxi_pinctrl_edge_irq_chip; 37 static struct irq_chip sunxi_pinctrl_level_irq_chip; 38 39 static struct sunxi_pinctrl_group * 40 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 41 { 42 int i; 43 44 for (i = 0; i < pctl->ngroups; i++) { 45 struct sunxi_pinctrl_group *grp = pctl->groups + i; 46 47 if (!strcmp(grp->name, group)) 48 return grp; 49 } 50 51 return NULL; 52 } 53 54 static struct sunxi_pinctrl_function * 55 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 56 const char *name) 57 { 58 struct sunxi_pinctrl_function *func = pctl->functions; 59 int i; 60 61 for (i = 0; i < pctl->nfunctions; i++) { 62 if (!func[i].name) 63 break; 64 65 if (!strcmp(func[i].name, name)) 66 return func + i; 67 } 68 69 return NULL; 70 } 71 72 static struct sunxi_desc_function * 73 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 74 const char *pin_name, 75 const char *func_name) 76 { 77 int i; 78 79 for (i = 0; i < pctl->desc->npins; i++) { 80 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 81 82 if (!strcmp(pin->pin.name, pin_name)) { 83 struct sunxi_desc_function *func = pin->functions; 84 85 while (func->name) { 86 if (!strcmp(func->name, func_name)) 87 return func; 88 89 func++; 90 } 91 } 92 } 93 94 return NULL; 95 } 96 97 static struct sunxi_desc_function * 98 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, 99 const u16 pin_num, 100 const char *func_name) 101 { 102 int i; 103 104 for (i = 0; i < pctl->desc->npins; i++) { 105 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 106 107 if (pin->pin.number == pin_num) { 108 struct sunxi_desc_function *func = pin->functions; 109 110 while (func->name) { 111 if (!strcmp(func->name, func_name)) 112 return func; 113 114 func++; 115 } 116 } 117 } 118 119 return NULL; 120 } 121 122 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 123 { 124 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 125 126 return pctl->ngroups; 127 } 128 129 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 130 unsigned group) 131 { 132 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 133 134 return pctl->groups[group].name; 135 } 136 137 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 138 unsigned group, 139 const unsigned **pins, 140 unsigned *num_pins) 141 { 142 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 143 144 *pins = (unsigned *)&pctl->groups[group].pin; 145 *num_pins = 1; 146 147 return 0; 148 } 149 150 static bool sunxi_pctrl_has_bias_prop(struct device_node *node) 151 { 152 return of_find_property(node, "bias-pull-up", NULL) || 153 of_find_property(node, "bias-pull-down", NULL) || 154 of_find_property(node, "bias-disable", NULL) || 155 of_find_property(node, "allwinner,pull", NULL); 156 } 157 158 static bool sunxi_pctrl_has_drive_prop(struct device_node *node) 159 { 160 return of_find_property(node, "drive-strength", NULL) || 161 of_find_property(node, "allwinner,drive", NULL); 162 } 163 164 static int sunxi_pctrl_parse_bias_prop(struct device_node *node) 165 { 166 u32 val; 167 168 /* Try the new style binding */ 169 if (of_find_property(node, "bias-pull-up", NULL)) 170 return PIN_CONFIG_BIAS_PULL_UP; 171 172 if (of_find_property(node, "bias-pull-down", NULL)) 173 return PIN_CONFIG_BIAS_PULL_DOWN; 174 175 if (of_find_property(node, "bias-disable", NULL)) 176 return PIN_CONFIG_BIAS_DISABLE; 177 178 /* And fall back to the old binding */ 179 if (of_property_read_u32(node, "allwinner,pull", &val)) 180 return -EINVAL; 181 182 switch (val) { 183 case SUN4I_PINCTRL_NO_PULL: 184 return PIN_CONFIG_BIAS_DISABLE; 185 case SUN4I_PINCTRL_PULL_UP: 186 return PIN_CONFIG_BIAS_PULL_UP; 187 case SUN4I_PINCTRL_PULL_DOWN: 188 return PIN_CONFIG_BIAS_PULL_DOWN; 189 } 190 191 return -EINVAL; 192 } 193 194 static int sunxi_pctrl_parse_drive_prop(struct device_node *node) 195 { 196 u32 val; 197 198 /* Try the new style binding */ 199 if (!of_property_read_u32(node, "drive-strength", &val)) { 200 /* We can't go below 10mA ... */ 201 if (val < 10) 202 return -EINVAL; 203 204 /* ... and only up to 40 mA ... */ 205 if (val > 40) 206 val = 40; 207 208 /* by steps of 10 mA */ 209 return rounddown(val, 10); 210 } 211 212 /* And then fall back to the old binding */ 213 if (of_property_read_u32(node, "allwinner,drive", &val)) 214 return -EINVAL; 215 216 return (val + 1) * 10; 217 } 218 219 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node) 220 { 221 const char *function; 222 int ret; 223 224 /* Try the generic binding */ 225 ret = of_property_read_string(node, "function", &function); 226 if (!ret) 227 return function; 228 229 /* And fall back to our legacy one */ 230 ret = of_property_read_string(node, "allwinner,function", &function); 231 if (!ret) 232 return function; 233 234 return NULL; 235 } 236 237 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node, 238 int *npins) 239 { 240 int count; 241 242 /* Try the generic binding */ 243 count = of_property_count_strings(node, "pins"); 244 if (count > 0) { 245 *npins = count; 246 return "pins"; 247 } 248 249 /* And fall back to our legacy one */ 250 count = of_property_count_strings(node, "allwinner,pins"); 251 if (count > 0) { 252 *npins = count; 253 return "allwinner,pins"; 254 } 255 256 return NULL; 257 } 258 259 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node, 260 unsigned int *len) 261 { 262 unsigned long *pinconfig; 263 unsigned int configlen = 0, idx = 0; 264 int ret; 265 266 if (sunxi_pctrl_has_drive_prop(node)) 267 configlen++; 268 if (sunxi_pctrl_has_bias_prop(node)) 269 configlen++; 270 271 /* 272 * If we don't have any configuration, bail out 273 */ 274 if (!configlen) 275 return NULL; 276 277 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); 278 if (!pinconfig) 279 return ERR_PTR(-ENOMEM); 280 281 if (sunxi_pctrl_has_drive_prop(node)) { 282 int drive = sunxi_pctrl_parse_drive_prop(node); 283 if (drive < 0) { 284 ret = drive; 285 goto err_free; 286 } 287 288 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 289 drive); 290 } 291 292 if (sunxi_pctrl_has_bias_prop(node)) { 293 int pull = sunxi_pctrl_parse_bias_prop(node); 294 int arg = 0; 295 if (pull < 0) { 296 ret = pull; 297 goto err_free; 298 } 299 300 if (pull != PIN_CONFIG_BIAS_DISABLE) 301 arg = 1; /* hardware uses weak pull resistors */ 302 303 pinconfig[idx++] = pinconf_to_config_packed(pull, arg); 304 } 305 306 307 *len = configlen; 308 return pinconfig; 309 310 err_free: 311 kfree(pinconfig); 312 return ERR_PTR(ret); 313 } 314 315 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 316 struct device_node *node, 317 struct pinctrl_map **map, 318 unsigned *num_maps) 319 { 320 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 321 unsigned long *pinconfig; 322 struct property *prop; 323 const char *function, *pin_prop; 324 const char *group; 325 int ret, npins, nmaps, configlen = 0, i = 0; 326 327 *map = NULL; 328 *num_maps = 0; 329 330 function = sunxi_pctrl_parse_function_prop(node); 331 if (!function) { 332 dev_err(pctl->dev, "missing function property in node %s\n", 333 node->name); 334 return -EINVAL; 335 } 336 337 pin_prop = sunxi_pctrl_find_pins_prop(node, &npins); 338 if (!pin_prop) { 339 dev_err(pctl->dev, "missing pins property in node %s\n", 340 node->name); 341 return -EINVAL; 342 } 343 344 /* 345 * We have two maps for each pin: one for the function, one 346 * for the configuration (bias, strength, etc). 347 * 348 * We might be slightly overshooting, since we might not have 349 * any configuration. 350 */ 351 nmaps = npins * 2; 352 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); 353 if (!*map) 354 return -ENOMEM; 355 356 pinconfig = sunxi_pctrl_build_pin_config(node, &configlen); 357 if (IS_ERR(pinconfig)) { 358 ret = PTR_ERR(pinconfig); 359 goto err_free_map; 360 } 361 362 of_property_for_each_string(node, pin_prop, prop, group) { 363 struct sunxi_pinctrl_group *grp = 364 sunxi_pinctrl_find_group_by_name(pctl, group); 365 366 if (!grp) { 367 dev_err(pctl->dev, "unknown pin %s", group); 368 continue; 369 } 370 371 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 372 grp->name, 373 function)) { 374 dev_err(pctl->dev, "unsupported function %s on pin %s", 375 function, group); 376 continue; 377 } 378 379 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 380 (*map)[i].data.mux.group = group; 381 (*map)[i].data.mux.function = function; 382 383 i++; 384 385 if (pinconfig) { 386 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 387 (*map)[i].data.configs.group_or_pin = group; 388 (*map)[i].data.configs.configs = pinconfig; 389 (*map)[i].data.configs.num_configs = configlen; 390 i++; 391 } 392 } 393 394 *num_maps = i; 395 396 /* 397 * We know have the number of maps we need, we can resize our 398 * map array 399 */ 400 *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL); 401 if (!*map) 402 return -ENOMEM; 403 404 return 0; 405 406 err_free_map: 407 kfree(*map); 408 *map = NULL; 409 return ret; 410 } 411 412 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 413 struct pinctrl_map *map, 414 unsigned num_maps) 415 { 416 int i; 417 418 /* pin config is never in the first map */ 419 for (i = 1; i < num_maps; i++) { 420 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP) 421 continue; 422 423 /* 424 * All the maps share the same pin config, 425 * free only the first one we find. 426 */ 427 kfree(map[i].data.configs.configs); 428 break; 429 } 430 431 kfree(map); 432 } 433 434 static const struct pinctrl_ops sunxi_pctrl_ops = { 435 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 436 .dt_free_map = sunxi_pctrl_dt_free_map, 437 .get_groups_count = sunxi_pctrl_get_groups_count, 438 .get_group_name = sunxi_pctrl_get_group_name, 439 .get_group_pins = sunxi_pctrl_get_group_pins, 440 }; 441 442 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param, 443 u32 *offset, u32 *shift, u32 *mask) 444 { 445 switch (param) { 446 case PIN_CONFIG_DRIVE_STRENGTH: 447 *offset = sunxi_dlevel_reg(pin); 448 *shift = sunxi_dlevel_offset(pin); 449 *mask = DLEVEL_PINS_MASK; 450 break; 451 452 case PIN_CONFIG_BIAS_PULL_UP: 453 case PIN_CONFIG_BIAS_PULL_DOWN: 454 case PIN_CONFIG_BIAS_DISABLE: 455 *offset = sunxi_pull_reg(pin); 456 *shift = sunxi_pull_offset(pin); 457 *mask = PULL_PINS_MASK; 458 break; 459 460 default: 461 return -ENOTSUPP; 462 } 463 464 return 0; 465 } 466 467 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin, 468 unsigned long *config) 469 { 470 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 471 enum pin_config_param param = pinconf_to_config_param(*config); 472 u32 offset, shift, mask, val; 473 u16 arg; 474 int ret; 475 476 pin -= pctl->desc->pin_base; 477 478 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); 479 if (ret < 0) 480 return ret; 481 482 val = (readl(pctl->membase + offset) >> shift) & mask; 483 484 switch (pinconf_to_config_param(*config)) { 485 case PIN_CONFIG_DRIVE_STRENGTH: 486 arg = (val + 1) * 10; 487 break; 488 489 case PIN_CONFIG_BIAS_PULL_UP: 490 if (val != SUN4I_PINCTRL_PULL_UP) 491 return -EINVAL; 492 arg = 1; /* hardware is weak pull-up */ 493 break; 494 495 case PIN_CONFIG_BIAS_PULL_DOWN: 496 if (val != SUN4I_PINCTRL_PULL_DOWN) 497 return -EINVAL; 498 arg = 1; /* hardware is weak pull-down */ 499 break; 500 501 case PIN_CONFIG_BIAS_DISABLE: 502 if (val != SUN4I_PINCTRL_NO_PULL) 503 return -EINVAL; 504 arg = 0; 505 break; 506 507 default: 508 /* sunxi_pconf_reg should catch anything unsupported */ 509 WARN_ON(1); 510 return -ENOTSUPP; 511 } 512 513 *config = pinconf_to_config_packed(param, arg); 514 515 return 0; 516 } 517 518 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 519 unsigned group, 520 unsigned long *config) 521 { 522 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 523 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 524 525 /* We only support 1 pin per group. Chain it to the pin callback */ 526 return sunxi_pconf_get(pctldev, g->pin, config); 527 } 528 529 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, 530 unsigned group, 531 unsigned long *configs, 532 unsigned num_configs) 533 { 534 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 535 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 536 unsigned pin = g->pin - pctl->desc->pin_base; 537 int i; 538 539 for (i = 0; i < num_configs; i++) { 540 enum pin_config_param param; 541 unsigned long flags; 542 u32 offset, shift, mask, reg; 543 u32 arg, val; 544 int ret; 545 546 param = pinconf_to_config_param(configs[i]); 547 arg = pinconf_to_config_argument(configs[i]); 548 549 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); 550 if (ret < 0) 551 return ret; 552 553 switch (param) { 554 case PIN_CONFIG_DRIVE_STRENGTH: 555 if (arg < 10 || arg > 40) 556 return -EINVAL; 557 /* 558 * We convert from mA to what the register expects: 559 * 0: 10mA 560 * 1: 20mA 561 * 2: 30mA 562 * 3: 40mA 563 */ 564 val = arg / 10 - 1; 565 break; 566 case PIN_CONFIG_BIAS_DISABLE: 567 continue; 568 case PIN_CONFIG_BIAS_PULL_UP: 569 if (arg == 0) 570 return -EINVAL; 571 val = 1; 572 break; 573 case PIN_CONFIG_BIAS_PULL_DOWN: 574 if (arg == 0) 575 return -EINVAL; 576 val = 2; 577 break; 578 default: 579 /* sunxi_pconf_reg should catch anything unsupported */ 580 WARN_ON(1); 581 return -ENOTSUPP; 582 } 583 584 raw_spin_lock_irqsave(&pctl->lock, flags); 585 reg = readl(pctl->membase + offset); 586 reg &= ~(mask << shift); 587 writel(reg | val << shift, pctl->membase + offset); 588 raw_spin_unlock_irqrestore(&pctl->lock, flags); 589 } /* for each config */ 590 591 return 0; 592 } 593 594 static const struct pinconf_ops sunxi_pconf_ops = { 595 .is_generic = true, 596 .pin_config_get = sunxi_pconf_get, 597 .pin_config_group_get = sunxi_pconf_group_get, 598 .pin_config_group_set = sunxi_pconf_group_set, 599 }; 600 601 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 602 { 603 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 604 605 return pctl->nfunctions; 606 } 607 608 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 609 unsigned function) 610 { 611 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 612 613 return pctl->functions[function].name; 614 } 615 616 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 617 unsigned function, 618 const char * const **groups, 619 unsigned * const num_groups) 620 { 621 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 622 623 *groups = pctl->functions[function].groups; 624 *num_groups = pctl->functions[function].ngroups; 625 626 return 0; 627 } 628 629 static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 630 unsigned pin, 631 u8 config) 632 { 633 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 634 unsigned long flags; 635 u32 val, mask; 636 637 raw_spin_lock_irqsave(&pctl->lock, flags); 638 639 pin -= pctl->desc->pin_base; 640 val = readl(pctl->membase + sunxi_mux_reg(pin)); 641 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 642 writel((val & ~mask) | config << sunxi_mux_offset(pin), 643 pctl->membase + sunxi_mux_reg(pin)); 644 645 raw_spin_unlock_irqrestore(&pctl->lock, flags); 646 } 647 648 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, 649 unsigned function, 650 unsigned group) 651 { 652 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 653 struct sunxi_pinctrl_group *g = pctl->groups + group; 654 struct sunxi_pinctrl_function *func = pctl->functions + function; 655 struct sunxi_desc_function *desc = 656 sunxi_pinctrl_desc_find_function_by_name(pctl, 657 g->name, 658 func->name); 659 660 if (!desc) 661 return -EINVAL; 662 663 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 664 665 return 0; 666 } 667 668 static int 669 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 670 struct pinctrl_gpio_range *range, 671 unsigned offset, 672 bool input) 673 { 674 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 675 struct sunxi_desc_function *desc; 676 const char *func; 677 678 if (input) 679 func = "gpio_in"; 680 else 681 func = "gpio_out"; 682 683 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); 684 if (!desc) 685 return -EINVAL; 686 687 sunxi_pmx_set(pctldev, offset, desc->muxval); 688 689 return 0; 690 } 691 692 static const struct pinmux_ops sunxi_pmx_ops = { 693 .get_functions_count = sunxi_pmx_get_funcs_cnt, 694 .get_function_name = sunxi_pmx_get_func_name, 695 .get_function_groups = sunxi_pmx_get_func_groups, 696 .set_mux = sunxi_pmx_set_mux, 697 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 698 }; 699 700 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 701 unsigned offset) 702 { 703 return pinctrl_gpio_direction_input(chip->base + offset); 704 } 705 706 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 707 { 708 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 709 u32 reg = sunxi_data_reg(offset); 710 u8 index = sunxi_data_offset(offset); 711 bool set_mux = pctl->desc->irq_read_needs_mux && 712 gpiochip_line_is_irq(chip, offset); 713 u32 pin = offset + chip->base; 714 u32 val; 715 716 if (set_mux) 717 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); 718 719 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; 720 721 if (set_mux) 722 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); 723 724 return !!val; 725 } 726 727 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 728 unsigned offset, int value) 729 { 730 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 731 u32 reg = sunxi_data_reg(offset); 732 u8 index = sunxi_data_offset(offset); 733 unsigned long flags; 734 u32 regval; 735 736 raw_spin_lock_irqsave(&pctl->lock, flags); 737 738 regval = readl(pctl->membase + reg); 739 740 if (value) 741 regval |= BIT(index); 742 else 743 regval &= ~(BIT(index)); 744 745 writel(regval, pctl->membase + reg); 746 747 raw_spin_unlock_irqrestore(&pctl->lock, flags); 748 } 749 750 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 751 unsigned offset, int value) 752 { 753 sunxi_pinctrl_gpio_set(chip, offset, value); 754 return pinctrl_gpio_direction_output(chip->base + offset); 755 } 756 757 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 758 const struct of_phandle_args *gpiospec, 759 u32 *flags) 760 { 761 int pin, base; 762 763 base = PINS_PER_BANK * gpiospec->args[0]; 764 pin = base + gpiospec->args[1]; 765 766 if (pin > gc->ngpio) 767 return -EINVAL; 768 769 if (flags) 770 *flags = gpiospec->args[2]; 771 772 return pin; 773 } 774 775 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 776 { 777 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 778 struct sunxi_desc_function *desc; 779 unsigned pinnum = pctl->desc->pin_base + offset; 780 unsigned irqnum; 781 782 if (offset >= chip->ngpio) 783 return -ENXIO; 784 785 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq"); 786 if (!desc) 787 return -EINVAL; 788 789 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum; 790 791 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n", 792 chip->label, offset + chip->base, irqnum); 793 794 return irq_find_mapping(pctl->domain, irqnum); 795 } 796 797 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) 798 { 799 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 800 struct sunxi_desc_function *func; 801 int ret; 802 803 func = sunxi_pinctrl_desc_find_function_by_pin(pctl, 804 pctl->irq_array[d->hwirq], "irq"); 805 if (!func) 806 return -EINVAL; 807 808 ret = gpiochip_lock_as_irq(pctl->chip, 809 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 810 if (ret) { 811 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 812 irqd_to_hwirq(d)); 813 return ret; 814 } 815 816 /* Change muxing to INT mode */ 817 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); 818 819 return 0; 820 } 821 822 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) 823 { 824 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 825 826 gpiochip_unlock_as_irq(pctl->chip, 827 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 828 } 829 830 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) 831 { 832 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 833 u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base); 834 u8 index = sunxi_irq_cfg_offset(d->hwirq); 835 unsigned long flags; 836 u32 regval; 837 u8 mode; 838 839 switch (type) { 840 case IRQ_TYPE_EDGE_RISING: 841 mode = IRQ_EDGE_RISING; 842 break; 843 case IRQ_TYPE_EDGE_FALLING: 844 mode = IRQ_EDGE_FALLING; 845 break; 846 case IRQ_TYPE_EDGE_BOTH: 847 mode = IRQ_EDGE_BOTH; 848 break; 849 case IRQ_TYPE_LEVEL_HIGH: 850 mode = IRQ_LEVEL_HIGH; 851 break; 852 case IRQ_TYPE_LEVEL_LOW: 853 mode = IRQ_LEVEL_LOW; 854 break; 855 default: 856 return -EINVAL; 857 } 858 859 raw_spin_lock_irqsave(&pctl->lock, flags); 860 861 if (type & IRQ_TYPE_LEVEL_MASK) 862 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip, 863 handle_fasteoi_irq, NULL); 864 else 865 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip, 866 handle_edge_irq, NULL); 867 868 regval = readl(pctl->membase + reg); 869 regval &= ~(IRQ_CFG_IRQ_MASK << index); 870 writel(regval | (mode << index), pctl->membase + reg); 871 872 raw_spin_unlock_irqrestore(&pctl->lock, flags); 873 874 return 0; 875 } 876 877 static void sunxi_pinctrl_irq_ack(struct irq_data *d) 878 { 879 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 880 u32 status_reg = sunxi_irq_status_reg(d->hwirq, 881 pctl->desc->irq_bank_base); 882 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 883 884 /* Clear the IRQ */ 885 writel(1 << status_idx, pctl->membase + status_reg); 886 } 887 888 static void sunxi_pinctrl_irq_mask(struct irq_data *d) 889 { 890 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 891 u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base); 892 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 893 unsigned long flags; 894 u32 val; 895 896 raw_spin_lock_irqsave(&pctl->lock, flags); 897 898 /* Mask the IRQ */ 899 val = readl(pctl->membase + reg); 900 writel(val & ~(1 << idx), pctl->membase + reg); 901 902 raw_spin_unlock_irqrestore(&pctl->lock, flags); 903 } 904 905 static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 906 { 907 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 908 u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base); 909 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 910 unsigned long flags; 911 u32 val; 912 913 raw_spin_lock_irqsave(&pctl->lock, flags); 914 915 /* Unmask the IRQ */ 916 val = readl(pctl->membase + reg); 917 writel(val | (1 << idx), pctl->membase + reg); 918 919 raw_spin_unlock_irqrestore(&pctl->lock, flags); 920 } 921 922 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) 923 { 924 sunxi_pinctrl_irq_ack(d); 925 sunxi_pinctrl_irq_unmask(d); 926 } 927 928 static struct irq_chip sunxi_pinctrl_edge_irq_chip = { 929 .name = "sunxi_pio_edge", 930 .irq_ack = sunxi_pinctrl_irq_ack, 931 .irq_mask = sunxi_pinctrl_irq_mask, 932 .irq_unmask = sunxi_pinctrl_irq_unmask, 933 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 934 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 935 .irq_set_type = sunxi_pinctrl_irq_set_type, 936 .flags = IRQCHIP_SKIP_SET_WAKE, 937 }; 938 939 static struct irq_chip sunxi_pinctrl_level_irq_chip = { 940 .name = "sunxi_pio_level", 941 .irq_eoi = sunxi_pinctrl_irq_ack, 942 .irq_mask = sunxi_pinctrl_irq_mask, 943 .irq_unmask = sunxi_pinctrl_irq_unmask, 944 /* Define irq_enable / disable to avoid spurious irqs for drivers 945 * using these to suppress irqs while they clear the irq source */ 946 .irq_enable = sunxi_pinctrl_irq_ack_unmask, 947 .irq_disable = sunxi_pinctrl_irq_mask, 948 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 949 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 950 .irq_set_type = sunxi_pinctrl_irq_set_type, 951 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED | 952 IRQCHIP_EOI_IF_HANDLED, 953 }; 954 955 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, 956 struct device_node *node, 957 const u32 *intspec, 958 unsigned int intsize, 959 unsigned long *out_hwirq, 960 unsigned int *out_type) 961 { 962 struct sunxi_pinctrl *pctl = d->host_data; 963 struct sunxi_desc_function *desc; 964 int pin, base; 965 966 if (intsize < 3) 967 return -EINVAL; 968 969 base = PINS_PER_BANK * intspec[0]; 970 pin = pctl->desc->pin_base + base + intspec[1]; 971 972 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); 973 if (!desc) 974 return -EINVAL; 975 976 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum; 977 *out_type = intspec[2]; 978 979 return 0; 980 } 981 982 static struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = { 983 .xlate = sunxi_pinctrl_irq_of_xlate, 984 }; 985 986 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) 987 { 988 unsigned int irq = irq_desc_get_irq(desc); 989 struct irq_chip *chip = irq_desc_get_chip(desc); 990 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc); 991 unsigned long bank, reg, val; 992 993 for (bank = 0; bank < pctl->desc->irq_banks; bank++) 994 if (irq == pctl->irq[bank]) 995 break; 996 997 if (bank == pctl->desc->irq_banks) 998 return; 999 1000 reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base); 1001 val = readl(pctl->membase + reg); 1002 1003 if (val) { 1004 int irqoffset; 1005 1006 chained_irq_enter(chip, desc); 1007 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) { 1008 int pin_irq = irq_find_mapping(pctl->domain, 1009 bank * IRQ_PER_BANK + irqoffset); 1010 generic_handle_irq(pin_irq); 1011 } 1012 chained_irq_exit(chip, desc); 1013 } 1014 } 1015 1016 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 1017 const char *name) 1018 { 1019 struct sunxi_pinctrl_function *func = pctl->functions; 1020 1021 while (func->name) { 1022 /* function already there */ 1023 if (strcmp(func->name, name) == 0) { 1024 func->ngroups++; 1025 return -EEXIST; 1026 } 1027 func++; 1028 } 1029 1030 func->name = name; 1031 func->ngroups = 1; 1032 1033 pctl->nfunctions++; 1034 1035 return 0; 1036 } 1037 1038 static int sunxi_pinctrl_build_state(struct platform_device *pdev) 1039 { 1040 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 1041 int i; 1042 1043 /* 1044 * Allocate groups 1045 * 1046 * We assume that the number of groups is the number of pins 1047 * given in the data array. 1048 1049 * This will not always be true, since some pins might not be 1050 * available in the current variant, but fortunately for us, 1051 * this means that the number of pins is the maximum group 1052 * number we will ever see. 1053 */ 1054 pctl->groups = devm_kzalloc(&pdev->dev, 1055 pctl->desc->npins * sizeof(*pctl->groups), 1056 GFP_KERNEL); 1057 if (!pctl->groups) 1058 return -ENOMEM; 1059 1060 for (i = 0; i < pctl->desc->npins; i++) { 1061 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1062 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups; 1063 1064 if (pin->variant && !(pctl->variant & pin->variant)) 1065 continue; 1066 1067 group->name = pin->pin.name; 1068 group->pin = pin->pin.number; 1069 1070 /* And now we count the actual number of pins / groups */ 1071 pctl->ngroups++; 1072 } 1073 1074 /* 1075 * We suppose that we won't have any more functions than pins, 1076 * we'll reallocate that later anyway 1077 */ 1078 pctl->functions = devm_kzalloc(&pdev->dev, 1079 pctl->ngroups * sizeof(*pctl->functions), 1080 GFP_KERNEL); 1081 if (!pctl->functions) 1082 return -ENOMEM; 1083 1084 /* Count functions and their associated groups */ 1085 for (i = 0; i < pctl->desc->npins; i++) { 1086 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1087 struct sunxi_desc_function *func; 1088 1089 if (pin->variant && !(pctl->variant & pin->variant)) 1090 continue; 1091 1092 for (func = pin->functions; func->name; func++) { 1093 if (func->variant && !(pctl->variant & func->variant)) 1094 continue; 1095 1096 /* Create interrupt mapping while we're at it */ 1097 if (!strcmp(func->name, "irq")) { 1098 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; 1099 pctl->irq_array[irqnum] = pin->pin.number; 1100 } 1101 1102 sunxi_pinctrl_add_function(pctl, func->name); 1103 } 1104 } 1105 1106 /* And now allocated and fill the array for real */ 1107 pctl->functions = krealloc(pctl->functions, 1108 pctl->nfunctions * sizeof(*pctl->functions), 1109 GFP_KERNEL); 1110 if (!pctl->functions) { 1111 kfree(pctl->functions); 1112 return -ENOMEM; 1113 } 1114 1115 for (i = 0; i < pctl->desc->npins; i++) { 1116 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1117 struct sunxi_desc_function *func; 1118 1119 if (pin->variant && !(pctl->variant & pin->variant)) 1120 continue; 1121 1122 for (func = pin->functions; func->name; func++) { 1123 struct sunxi_pinctrl_function *func_item; 1124 const char **func_grp; 1125 1126 if (func->variant && !(pctl->variant & func->variant)) 1127 continue; 1128 1129 func_item = sunxi_pinctrl_find_function_by_name(pctl, 1130 func->name); 1131 if (!func_item) 1132 return -EINVAL; 1133 1134 if (!func_item->groups) { 1135 func_item->groups = 1136 devm_kzalloc(&pdev->dev, 1137 func_item->ngroups * sizeof(*func_item->groups), 1138 GFP_KERNEL); 1139 if (!func_item->groups) 1140 return -ENOMEM; 1141 } 1142 1143 func_grp = func_item->groups; 1144 while (*func_grp) 1145 func_grp++; 1146 1147 *func_grp = pin->pin.name; 1148 } 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff) 1155 { 1156 unsigned long clock = clk_get_rate(clk); 1157 unsigned int best_diff, best_div; 1158 int i; 1159 1160 best_diff = abs(freq - clock); 1161 best_div = 0; 1162 1163 for (i = 1; i < 8; i++) { 1164 int cur_diff = abs(freq - (clock >> i)); 1165 1166 if (cur_diff < best_diff) { 1167 best_diff = cur_diff; 1168 best_div = i; 1169 } 1170 } 1171 1172 *diff = best_diff; 1173 return best_div; 1174 } 1175 1176 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, 1177 struct device_node *node) 1178 { 1179 unsigned int hosc_diff, losc_diff; 1180 unsigned int hosc_div, losc_div; 1181 struct clk *hosc, *losc; 1182 u8 div, src; 1183 int i, ret; 1184 1185 /* Deal with old DTs that didn't have the oscillators */ 1186 if (of_count_phandle_with_args(node, "clocks", "#clock-cells") != 3) 1187 return 0; 1188 1189 /* If we don't have any setup, bail out */ 1190 if (!of_find_property(node, "input-debounce", NULL)) 1191 return 0; 1192 1193 losc = devm_clk_get(pctl->dev, "losc"); 1194 if (IS_ERR(losc)) 1195 return PTR_ERR(losc); 1196 1197 hosc = devm_clk_get(pctl->dev, "hosc"); 1198 if (IS_ERR(hosc)) 1199 return PTR_ERR(hosc); 1200 1201 for (i = 0; i < pctl->desc->irq_banks; i++) { 1202 unsigned long debounce_freq; 1203 u32 debounce; 1204 1205 ret = of_property_read_u32_index(node, "input-debounce", 1206 i, &debounce); 1207 if (ret) 1208 return ret; 1209 1210 if (!debounce) 1211 continue; 1212 1213 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce); 1214 losc_div = sunxi_pinctrl_get_debounce_div(losc, 1215 debounce_freq, 1216 &losc_diff); 1217 1218 hosc_div = sunxi_pinctrl_get_debounce_div(hosc, 1219 debounce_freq, 1220 &hosc_diff); 1221 1222 if (hosc_diff < losc_diff) { 1223 div = hosc_div; 1224 src = 1; 1225 } else { 1226 div = losc_div; 1227 src = 0; 1228 } 1229 1230 writel(src | div << 4, 1231 pctl->membase + 1232 sunxi_irq_debounce_reg_from_bank(i, 1233 pctl->desc->irq_bank_base)); 1234 } 1235 1236 return 0; 1237 } 1238 1239 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, 1240 const struct sunxi_pinctrl_desc *desc, 1241 unsigned long variant) 1242 { 1243 struct device_node *node = pdev->dev.of_node; 1244 struct pinctrl_desc *pctrl_desc; 1245 struct pinctrl_pin_desc *pins; 1246 struct sunxi_pinctrl *pctl; 1247 struct resource *res; 1248 int i, ret, last_pin, pin_idx; 1249 struct clk *clk; 1250 1251 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1252 if (!pctl) 1253 return -ENOMEM; 1254 platform_set_drvdata(pdev, pctl); 1255 1256 raw_spin_lock_init(&pctl->lock); 1257 1258 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1259 pctl->membase = devm_ioremap_resource(&pdev->dev, res); 1260 if (IS_ERR(pctl->membase)) 1261 return PTR_ERR(pctl->membase); 1262 1263 pctl->dev = &pdev->dev; 1264 pctl->desc = desc; 1265 pctl->variant = variant; 1266 1267 pctl->irq_array = devm_kcalloc(&pdev->dev, 1268 IRQ_PER_BANK * pctl->desc->irq_banks, 1269 sizeof(*pctl->irq_array), 1270 GFP_KERNEL); 1271 if (!pctl->irq_array) 1272 return -ENOMEM; 1273 1274 ret = sunxi_pinctrl_build_state(pdev); 1275 if (ret) { 1276 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 1277 return ret; 1278 } 1279 1280 pins = devm_kzalloc(&pdev->dev, 1281 pctl->desc->npins * sizeof(*pins), 1282 GFP_KERNEL); 1283 if (!pins) 1284 return -ENOMEM; 1285 1286 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) { 1287 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1288 1289 if (pin->variant && !(pctl->variant & pin->variant)) 1290 continue; 1291 1292 pins[pin_idx++] = pin->pin; 1293 } 1294 1295 pctrl_desc = devm_kzalloc(&pdev->dev, 1296 sizeof(*pctrl_desc), 1297 GFP_KERNEL); 1298 if (!pctrl_desc) 1299 return -ENOMEM; 1300 1301 pctrl_desc->name = dev_name(&pdev->dev); 1302 pctrl_desc->owner = THIS_MODULE; 1303 pctrl_desc->pins = pins; 1304 pctrl_desc->npins = pctl->ngroups; 1305 pctrl_desc->confops = &sunxi_pconf_ops; 1306 pctrl_desc->pctlops = &sunxi_pctrl_ops; 1307 pctrl_desc->pmxops = &sunxi_pmx_ops; 1308 1309 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); 1310 if (IS_ERR(pctl->pctl_dev)) { 1311 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1312 return PTR_ERR(pctl->pctl_dev); 1313 } 1314 1315 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1316 if (!pctl->chip) 1317 return -ENOMEM; 1318 1319 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 1320 pctl->chip->owner = THIS_MODULE; 1321 pctl->chip->request = gpiochip_generic_request, 1322 pctl->chip->free = gpiochip_generic_free, 1323 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input, 1324 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output, 1325 pctl->chip->get = sunxi_pinctrl_gpio_get, 1326 pctl->chip->set = sunxi_pinctrl_gpio_set, 1327 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate, 1328 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq, 1329 pctl->chip->of_gpio_n_cells = 3, 1330 pctl->chip->can_sleep = false, 1331 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - 1332 pctl->desc->pin_base; 1333 pctl->chip->label = dev_name(&pdev->dev); 1334 pctl->chip->parent = &pdev->dev; 1335 pctl->chip->base = pctl->desc->pin_base; 1336 1337 ret = gpiochip_add_data(pctl->chip, pctl); 1338 if (ret) 1339 return ret; 1340 1341 for (i = 0; i < pctl->desc->npins; i++) { 1342 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1343 1344 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1345 pin->pin.number - pctl->desc->pin_base, 1346 pin->pin.number, 1); 1347 if (ret) 1348 goto gpiochip_error; 1349 } 1350 1351 clk = devm_clk_get(&pdev->dev, NULL); 1352 if (IS_ERR(clk)) { 1353 ret = PTR_ERR(clk); 1354 goto gpiochip_error; 1355 } 1356 1357 ret = clk_prepare_enable(clk); 1358 if (ret) 1359 goto gpiochip_error; 1360 1361 pctl->irq = devm_kcalloc(&pdev->dev, 1362 pctl->desc->irq_banks, 1363 sizeof(*pctl->irq), 1364 GFP_KERNEL); 1365 if (!pctl->irq) { 1366 ret = -ENOMEM; 1367 goto clk_error; 1368 } 1369 1370 for (i = 0; i < pctl->desc->irq_banks; i++) { 1371 pctl->irq[i] = platform_get_irq(pdev, i); 1372 if (pctl->irq[i] < 0) { 1373 ret = pctl->irq[i]; 1374 goto clk_error; 1375 } 1376 } 1377 1378 pctl->domain = irq_domain_add_linear(node, 1379 pctl->desc->irq_banks * IRQ_PER_BANK, 1380 &sunxi_pinctrl_irq_domain_ops, 1381 pctl); 1382 if (!pctl->domain) { 1383 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 1384 ret = -ENOMEM; 1385 goto clk_error; 1386 } 1387 1388 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { 1389 int irqno = irq_create_mapping(pctl->domain, i); 1390 1391 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, 1392 handle_edge_irq); 1393 irq_set_chip_data(irqno, pctl); 1394 } 1395 1396 for (i = 0; i < pctl->desc->irq_banks; i++) { 1397 /* Mask and clear all IRQs before registering a handler */ 1398 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i, 1399 pctl->desc->irq_bank_base)); 1400 writel(0xffffffff, 1401 pctl->membase + sunxi_irq_status_reg_from_bank(i, 1402 pctl->desc->irq_bank_base)); 1403 1404 irq_set_chained_handler_and_data(pctl->irq[i], 1405 sunxi_pinctrl_irq_handler, 1406 pctl); 1407 } 1408 1409 sunxi_pinctrl_setup_debounce(pctl, node); 1410 1411 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1412 1413 return 0; 1414 1415 clk_error: 1416 clk_disable_unprepare(clk); 1417 gpiochip_error: 1418 gpiochip_remove(pctl->chip); 1419 return ret; 1420 } 1421