1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/io.h> 14 #include <linux/clk.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/interrupt.h> 17 #include <linux/irqdomain.h> 18 #include <linux/irqchip/chained_irq.h> 19 #include <linux/export.h> 20 #include <linux/of.h> 21 #include <linux/of_clk.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/of_irq.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/pinctrl/machine.h> 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinconf-generic.h> 29 #include <linux/pinctrl/pinmux.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/platform_device.h> 32 #include <linux/slab.h> 33 34 #include <dt-bindings/pinctrl/sun4i-a10.h> 35 36 #include "../core.h" 37 #include "pinctrl-sunxi.h" 38 39 /* 40 * These lock classes tell lockdep that GPIO IRQs are in a different 41 * category than their parents, so it won't report false recursion. 42 */ 43 static struct lock_class_key sunxi_pinctrl_irq_lock_class; 44 static struct lock_class_key sunxi_pinctrl_irq_request_class; 45 46 static struct irq_chip sunxi_pinctrl_edge_irq_chip; 47 static struct irq_chip sunxi_pinctrl_level_irq_chip; 48 49 static struct sunxi_pinctrl_group * 50 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 51 { 52 int i; 53 54 for (i = 0; i < pctl->ngroups; i++) { 55 struct sunxi_pinctrl_group *grp = pctl->groups + i; 56 57 if (!strcmp(grp->name, group)) 58 return grp; 59 } 60 61 return NULL; 62 } 63 64 static struct sunxi_pinctrl_function * 65 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 66 const char *name) 67 { 68 struct sunxi_pinctrl_function *func = pctl->functions; 69 int i; 70 71 for (i = 0; i < pctl->nfunctions; i++) { 72 if (!func[i].name) 73 break; 74 75 if (!strcmp(func[i].name, name)) 76 return func + i; 77 } 78 79 return NULL; 80 } 81 82 static struct sunxi_desc_function * 83 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 84 const char *pin_name, 85 const char *func_name) 86 { 87 int i; 88 89 for (i = 0; i < pctl->desc->npins; i++) { 90 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 91 92 if (!strcmp(pin->pin.name, pin_name)) { 93 struct sunxi_desc_function *func = pin->functions; 94 95 while (func->name) { 96 if (!strcmp(func->name, func_name) && 97 (!func->variant || 98 func->variant & pctl->variant)) 99 return func; 100 101 func++; 102 } 103 } 104 } 105 106 return NULL; 107 } 108 109 static struct sunxi_desc_function * 110 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, 111 const u16 pin_num, 112 const char *func_name) 113 { 114 int i; 115 116 for (i = 0; i < pctl->desc->npins; i++) { 117 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 118 119 if (pin->pin.number == pin_num) { 120 struct sunxi_desc_function *func = pin->functions; 121 122 while (func->name) { 123 if (!strcmp(func->name, func_name)) 124 return func; 125 126 func++; 127 } 128 } 129 } 130 131 return NULL; 132 } 133 134 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 135 { 136 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 137 138 return pctl->ngroups; 139 } 140 141 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 142 unsigned group) 143 { 144 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 145 146 return pctl->groups[group].name; 147 } 148 149 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 150 unsigned group, 151 const unsigned **pins, 152 unsigned *num_pins) 153 { 154 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 155 156 *pins = (unsigned *)&pctl->groups[group].pin; 157 *num_pins = 1; 158 159 return 0; 160 } 161 162 static bool sunxi_pctrl_has_bias_prop(struct device_node *node) 163 { 164 return of_find_property(node, "bias-pull-up", NULL) || 165 of_find_property(node, "bias-pull-down", NULL) || 166 of_find_property(node, "bias-disable", NULL) || 167 of_find_property(node, "allwinner,pull", NULL); 168 } 169 170 static bool sunxi_pctrl_has_drive_prop(struct device_node *node) 171 { 172 return of_find_property(node, "drive-strength", NULL) || 173 of_find_property(node, "allwinner,drive", NULL); 174 } 175 176 static int sunxi_pctrl_parse_bias_prop(struct device_node *node) 177 { 178 u32 val; 179 180 /* Try the new style binding */ 181 if (of_find_property(node, "bias-pull-up", NULL)) 182 return PIN_CONFIG_BIAS_PULL_UP; 183 184 if (of_find_property(node, "bias-pull-down", NULL)) 185 return PIN_CONFIG_BIAS_PULL_DOWN; 186 187 if (of_find_property(node, "bias-disable", NULL)) 188 return PIN_CONFIG_BIAS_DISABLE; 189 190 /* And fall back to the old binding */ 191 if (of_property_read_u32(node, "allwinner,pull", &val)) 192 return -EINVAL; 193 194 switch (val) { 195 case SUN4I_PINCTRL_NO_PULL: 196 return PIN_CONFIG_BIAS_DISABLE; 197 case SUN4I_PINCTRL_PULL_UP: 198 return PIN_CONFIG_BIAS_PULL_UP; 199 case SUN4I_PINCTRL_PULL_DOWN: 200 return PIN_CONFIG_BIAS_PULL_DOWN; 201 } 202 203 return -EINVAL; 204 } 205 206 static int sunxi_pctrl_parse_drive_prop(struct device_node *node) 207 { 208 u32 val; 209 210 /* Try the new style binding */ 211 if (!of_property_read_u32(node, "drive-strength", &val)) { 212 /* We can't go below 10mA ... */ 213 if (val < 10) 214 return -EINVAL; 215 216 /* ... and only up to 40 mA ... */ 217 if (val > 40) 218 val = 40; 219 220 /* by steps of 10 mA */ 221 return rounddown(val, 10); 222 } 223 224 /* And then fall back to the old binding */ 225 if (of_property_read_u32(node, "allwinner,drive", &val)) 226 return -EINVAL; 227 228 return (val + 1) * 10; 229 } 230 231 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node) 232 { 233 const char *function; 234 int ret; 235 236 /* Try the generic binding */ 237 ret = of_property_read_string(node, "function", &function); 238 if (!ret) 239 return function; 240 241 /* And fall back to our legacy one */ 242 ret = of_property_read_string(node, "allwinner,function", &function); 243 if (!ret) 244 return function; 245 246 return NULL; 247 } 248 249 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node, 250 int *npins) 251 { 252 int count; 253 254 /* Try the generic binding */ 255 count = of_property_count_strings(node, "pins"); 256 if (count > 0) { 257 *npins = count; 258 return "pins"; 259 } 260 261 /* And fall back to our legacy one */ 262 count = of_property_count_strings(node, "allwinner,pins"); 263 if (count > 0) { 264 *npins = count; 265 return "allwinner,pins"; 266 } 267 268 return NULL; 269 } 270 271 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node, 272 unsigned int *len) 273 { 274 unsigned long *pinconfig; 275 unsigned int configlen = 0, idx = 0; 276 int ret; 277 278 if (sunxi_pctrl_has_drive_prop(node)) 279 configlen++; 280 if (sunxi_pctrl_has_bias_prop(node)) 281 configlen++; 282 283 /* 284 * If we don't have any configuration, bail out 285 */ 286 if (!configlen) 287 return NULL; 288 289 pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL); 290 if (!pinconfig) 291 return ERR_PTR(-ENOMEM); 292 293 if (sunxi_pctrl_has_drive_prop(node)) { 294 int drive = sunxi_pctrl_parse_drive_prop(node); 295 if (drive < 0) { 296 ret = drive; 297 goto err_free; 298 } 299 300 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 301 drive); 302 } 303 304 if (sunxi_pctrl_has_bias_prop(node)) { 305 int pull = sunxi_pctrl_parse_bias_prop(node); 306 int arg = 0; 307 if (pull < 0) { 308 ret = pull; 309 goto err_free; 310 } 311 312 if (pull != PIN_CONFIG_BIAS_DISABLE) 313 arg = 1; /* hardware uses weak pull resistors */ 314 315 pinconfig[idx++] = pinconf_to_config_packed(pull, arg); 316 } 317 318 319 *len = configlen; 320 return pinconfig; 321 322 err_free: 323 kfree(pinconfig); 324 return ERR_PTR(ret); 325 } 326 327 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 328 struct device_node *node, 329 struct pinctrl_map **map, 330 unsigned *num_maps) 331 { 332 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 333 unsigned long *pinconfig; 334 struct property *prop; 335 const char *function, *pin_prop; 336 const char *group; 337 int ret, npins, nmaps, configlen = 0, i = 0; 338 339 *map = NULL; 340 *num_maps = 0; 341 342 function = sunxi_pctrl_parse_function_prop(node); 343 if (!function) { 344 dev_err(pctl->dev, "missing function property in node %pOFn\n", 345 node); 346 return -EINVAL; 347 } 348 349 pin_prop = sunxi_pctrl_find_pins_prop(node, &npins); 350 if (!pin_prop) { 351 dev_err(pctl->dev, "missing pins property in node %pOFn\n", 352 node); 353 return -EINVAL; 354 } 355 356 /* 357 * We have two maps for each pin: one for the function, one 358 * for the configuration (bias, strength, etc). 359 * 360 * We might be slightly overshooting, since we might not have 361 * any configuration. 362 */ 363 nmaps = npins * 2; 364 *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL); 365 if (!*map) 366 return -ENOMEM; 367 368 pinconfig = sunxi_pctrl_build_pin_config(node, &configlen); 369 if (IS_ERR(pinconfig)) { 370 ret = PTR_ERR(pinconfig); 371 goto err_free_map; 372 } 373 374 of_property_for_each_string(node, pin_prop, prop, group) { 375 struct sunxi_pinctrl_group *grp = 376 sunxi_pinctrl_find_group_by_name(pctl, group); 377 378 if (!grp) { 379 dev_err(pctl->dev, "unknown pin %s", group); 380 continue; 381 } 382 383 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 384 grp->name, 385 function)) { 386 dev_err(pctl->dev, "unsupported function %s on pin %s", 387 function, group); 388 continue; 389 } 390 391 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 392 (*map)[i].data.mux.group = group; 393 (*map)[i].data.mux.function = function; 394 395 i++; 396 397 if (pinconfig) { 398 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 399 (*map)[i].data.configs.group_or_pin = group; 400 (*map)[i].data.configs.configs = pinconfig; 401 (*map)[i].data.configs.num_configs = configlen; 402 i++; 403 } 404 } 405 406 *num_maps = i; 407 408 /* 409 * We know have the number of maps we need, we can resize our 410 * map array 411 */ 412 *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL); 413 if (!*map) 414 return -ENOMEM; 415 416 return 0; 417 418 err_free_map: 419 kfree(*map); 420 *map = NULL; 421 return ret; 422 } 423 424 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 425 struct pinctrl_map *map, 426 unsigned num_maps) 427 { 428 int i; 429 430 /* pin config is never in the first map */ 431 for (i = 1; i < num_maps; i++) { 432 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP) 433 continue; 434 435 /* 436 * All the maps share the same pin config, 437 * free only the first one we find. 438 */ 439 kfree(map[i].data.configs.configs); 440 break; 441 } 442 443 kfree(map); 444 } 445 446 static const struct pinctrl_ops sunxi_pctrl_ops = { 447 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 448 .dt_free_map = sunxi_pctrl_dt_free_map, 449 .get_groups_count = sunxi_pctrl_get_groups_count, 450 .get_group_name = sunxi_pctrl_get_group_name, 451 .get_group_pins = sunxi_pctrl_get_group_pins, 452 }; 453 454 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param, 455 u32 *offset, u32 *shift, u32 *mask) 456 { 457 switch (param) { 458 case PIN_CONFIG_DRIVE_STRENGTH: 459 *offset = sunxi_dlevel_reg(pin); 460 *shift = sunxi_dlevel_offset(pin); 461 *mask = DLEVEL_PINS_MASK; 462 break; 463 464 case PIN_CONFIG_BIAS_PULL_UP: 465 case PIN_CONFIG_BIAS_PULL_DOWN: 466 case PIN_CONFIG_BIAS_DISABLE: 467 *offset = sunxi_pull_reg(pin); 468 *shift = sunxi_pull_offset(pin); 469 *mask = PULL_PINS_MASK; 470 break; 471 472 default: 473 return -ENOTSUPP; 474 } 475 476 return 0; 477 } 478 479 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin, 480 unsigned long *config) 481 { 482 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 483 enum pin_config_param param = pinconf_to_config_param(*config); 484 u32 offset, shift, mask, val; 485 u16 arg; 486 int ret; 487 488 pin -= pctl->desc->pin_base; 489 490 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); 491 if (ret < 0) 492 return ret; 493 494 val = (readl(pctl->membase + offset) >> shift) & mask; 495 496 switch (pinconf_to_config_param(*config)) { 497 case PIN_CONFIG_DRIVE_STRENGTH: 498 arg = (val + 1) * 10; 499 break; 500 501 case PIN_CONFIG_BIAS_PULL_UP: 502 if (val != SUN4I_PINCTRL_PULL_UP) 503 return -EINVAL; 504 arg = 1; /* hardware is weak pull-up */ 505 break; 506 507 case PIN_CONFIG_BIAS_PULL_DOWN: 508 if (val != SUN4I_PINCTRL_PULL_DOWN) 509 return -EINVAL; 510 arg = 1; /* hardware is weak pull-down */ 511 break; 512 513 case PIN_CONFIG_BIAS_DISABLE: 514 if (val != SUN4I_PINCTRL_NO_PULL) 515 return -EINVAL; 516 arg = 0; 517 break; 518 519 default: 520 /* sunxi_pconf_reg should catch anything unsupported */ 521 WARN_ON(1); 522 return -ENOTSUPP; 523 } 524 525 *config = pinconf_to_config_packed(param, arg); 526 527 return 0; 528 } 529 530 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 531 unsigned group, 532 unsigned long *config) 533 { 534 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 535 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 536 537 /* We only support 1 pin per group. Chain it to the pin callback */ 538 return sunxi_pconf_get(pctldev, g->pin, config); 539 } 540 541 static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin, 542 unsigned long *configs, unsigned num_configs) 543 { 544 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 545 int i; 546 547 for (i = 0; i < num_configs; i++) { 548 enum pin_config_param param; 549 unsigned long flags; 550 u32 offset, shift, mask, reg; 551 u32 arg, val; 552 int ret; 553 554 param = pinconf_to_config_param(configs[i]); 555 arg = pinconf_to_config_argument(configs[i]); 556 557 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); 558 if (ret < 0) 559 return ret; 560 561 switch (param) { 562 case PIN_CONFIG_DRIVE_STRENGTH: 563 if (arg < 10 || arg > 40) 564 return -EINVAL; 565 /* 566 * We convert from mA to what the register expects: 567 * 0: 10mA 568 * 1: 20mA 569 * 2: 30mA 570 * 3: 40mA 571 */ 572 val = arg / 10 - 1; 573 break; 574 case PIN_CONFIG_BIAS_DISABLE: 575 val = 0; 576 break; 577 case PIN_CONFIG_BIAS_PULL_UP: 578 if (arg == 0) 579 return -EINVAL; 580 val = 1; 581 break; 582 case PIN_CONFIG_BIAS_PULL_DOWN: 583 if (arg == 0) 584 return -EINVAL; 585 val = 2; 586 break; 587 default: 588 /* sunxi_pconf_reg should catch anything unsupported */ 589 WARN_ON(1); 590 return -ENOTSUPP; 591 } 592 593 raw_spin_lock_irqsave(&pctl->lock, flags); 594 reg = readl(pctl->membase + offset); 595 reg &= ~(mask << shift); 596 writel(reg | val << shift, pctl->membase + offset); 597 raw_spin_unlock_irqrestore(&pctl->lock, flags); 598 } /* for each config */ 599 600 return 0; 601 } 602 603 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 604 unsigned long *configs, unsigned num_configs) 605 { 606 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 607 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 608 609 /* We only support 1 pin per group. Chain it to the pin callback */ 610 return sunxi_pconf_set(pctldev, g->pin, configs, num_configs); 611 } 612 613 static const struct pinconf_ops sunxi_pconf_ops = { 614 .is_generic = true, 615 .pin_config_get = sunxi_pconf_get, 616 .pin_config_set = sunxi_pconf_set, 617 .pin_config_group_get = sunxi_pconf_group_get, 618 .pin_config_group_set = sunxi_pconf_group_set, 619 }; 620 621 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, 622 unsigned pin, 623 struct regulator *supply) 624 { 625 unsigned short bank = pin / PINS_PER_BANK; 626 unsigned long flags; 627 u32 val, reg; 628 int uV; 629 630 if (!pctl->desc->io_bias_cfg_variant) 631 return 0; 632 633 uV = regulator_get_voltage(supply); 634 if (uV < 0) 635 return uV; 636 637 /* Might be dummy regulator with no voltage set */ 638 if (uV == 0) 639 return 0; 640 641 switch (pctl->desc->io_bias_cfg_variant) { 642 case BIAS_VOLTAGE_GRP_CONFIG: 643 /* 644 * Configured value must be equal or greater to actual 645 * voltage. 646 */ 647 if (uV <= 1800000) 648 val = 0x0; /* 1.8V */ 649 else if (uV <= 2500000) 650 val = 0x6; /* 2.5V */ 651 else if (uV <= 2800000) 652 val = 0x9; /* 2.8V */ 653 else if (uV <= 3000000) 654 val = 0xA; /* 3.0V */ 655 else 656 val = 0xD; /* 3.3V */ 657 658 pin -= pctl->desc->pin_base; 659 660 reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); 661 reg &= ~IO_BIAS_MASK; 662 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); 663 return 0; 664 case BIAS_VOLTAGE_PIO_POW_MODE_SEL: 665 val = uV <= 1800000 ? 1 : 0; 666 667 raw_spin_lock_irqsave(&pctl->lock, flags); 668 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); 669 reg &= ~(1 << bank); 670 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); 671 raw_spin_unlock_irqrestore(&pctl->lock, flags); 672 return 0; 673 default: 674 return -EINVAL; 675 } 676 } 677 678 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 679 { 680 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 681 682 return pctl->nfunctions; 683 } 684 685 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 686 unsigned function) 687 { 688 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 689 690 return pctl->functions[function].name; 691 } 692 693 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 694 unsigned function, 695 const char * const **groups, 696 unsigned * const num_groups) 697 { 698 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 699 700 *groups = pctl->functions[function].groups; 701 *num_groups = pctl->functions[function].ngroups; 702 703 return 0; 704 } 705 706 static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 707 unsigned pin, 708 u8 config) 709 { 710 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 711 unsigned long flags; 712 u32 val, mask; 713 714 raw_spin_lock_irqsave(&pctl->lock, flags); 715 716 pin -= pctl->desc->pin_base; 717 val = readl(pctl->membase + sunxi_mux_reg(pin)); 718 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 719 writel((val & ~mask) | config << sunxi_mux_offset(pin), 720 pctl->membase + sunxi_mux_reg(pin)); 721 722 raw_spin_unlock_irqrestore(&pctl->lock, flags); 723 } 724 725 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, 726 unsigned function, 727 unsigned group) 728 { 729 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 730 struct sunxi_pinctrl_group *g = pctl->groups + group; 731 struct sunxi_pinctrl_function *func = pctl->functions + function; 732 struct sunxi_desc_function *desc = 733 sunxi_pinctrl_desc_find_function_by_name(pctl, 734 g->name, 735 func->name); 736 737 if (!desc) 738 return -EINVAL; 739 740 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 741 742 return 0; 743 } 744 745 static int 746 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 747 struct pinctrl_gpio_range *range, 748 unsigned offset, 749 bool input) 750 { 751 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 752 struct sunxi_desc_function *desc; 753 const char *func; 754 755 if (input) 756 func = "gpio_in"; 757 else 758 func = "gpio_out"; 759 760 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); 761 if (!desc) 762 return -EINVAL; 763 764 sunxi_pmx_set(pctldev, offset, desc->muxval); 765 766 return 0; 767 } 768 769 static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset) 770 { 771 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 772 unsigned short bank = offset / PINS_PER_BANK; 773 unsigned short bank_offset = bank - pctl->desc->pin_base / 774 PINS_PER_BANK; 775 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; 776 struct regulator *reg = s_reg->regulator; 777 char supply[16]; 778 int ret; 779 780 if (reg) { 781 refcount_inc(&s_reg->refcount); 782 return 0; 783 } 784 785 snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank); 786 reg = regulator_get(pctl->dev, supply); 787 if (IS_ERR(reg)) { 788 dev_err(pctl->dev, "Couldn't get bank P%c regulator\n", 789 'A' + bank); 790 return PTR_ERR(reg); 791 } 792 793 ret = regulator_enable(reg); 794 if (ret) { 795 dev_err(pctl->dev, 796 "Couldn't enable bank P%c regulator\n", 'A' + bank); 797 goto out; 798 } 799 800 sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg); 801 802 s_reg->regulator = reg; 803 refcount_set(&s_reg->refcount, 1); 804 805 return 0; 806 807 out: 808 regulator_put(s_reg->regulator); 809 810 return ret; 811 } 812 813 static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset) 814 { 815 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 816 unsigned short bank = offset / PINS_PER_BANK; 817 unsigned short bank_offset = bank - pctl->desc->pin_base / 818 PINS_PER_BANK; 819 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; 820 821 if (!refcount_dec_and_test(&s_reg->refcount)) 822 return 0; 823 824 regulator_disable(s_reg->regulator); 825 regulator_put(s_reg->regulator); 826 s_reg->regulator = NULL; 827 828 return 0; 829 } 830 831 static const struct pinmux_ops sunxi_pmx_ops = { 832 .get_functions_count = sunxi_pmx_get_funcs_cnt, 833 .get_function_name = sunxi_pmx_get_func_name, 834 .get_function_groups = sunxi_pmx_get_func_groups, 835 .set_mux = sunxi_pmx_set_mux, 836 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 837 .request = sunxi_pmx_request, 838 .free = sunxi_pmx_free, 839 .strict = true, 840 }; 841 842 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 843 unsigned offset) 844 { 845 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 846 847 return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL, 848 chip->base + offset, true); 849 } 850 851 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 852 { 853 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 854 u32 reg = sunxi_data_reg(offset); 855 u8 index = sunxi_data_offset(offset); 856 bool set_mux = pctl->desc->irq_read_needs_mux && 857 gpiochip_line_is_irq(chip, offset); 858 u32 pin = offset + chip->base; 859 u32 val; 860 861 if (set_mux) 862 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); 863 864 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; 865 866 if (set_mux) 867 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); 868 869 return !!val; 870 } 871 872 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 873 unsigned offset, int value) 874 { 875 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 876 u32 reg = sunxi_data_reg(offset); 877 u8 index = sunxi_data_offset(offset); 878 unsigned long flags; 879 u32 regval; 880 881 raw_spin_lock_irqsave(&pctl->lock, flags); 882 883 regval = readl(pctl->membase + reg); 884 885 if (value) 886 regval |= BIT(index); 887 else 888 regval &= ~(BIT(index)); 889 890 writel(regval, pctl->membase + reg); 891 892 raw_spin_unlock_irqrestore(&pctl->lock, flags); 893 } 894 895 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 896 unsigned offset, int value) 897 { 898 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 899 900 sunxi_pinctrl_gpio_set(chip, offset, value); 901 return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL, 902 chip->base + offset, false); 903 } 904 905 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 906 const struct of_phandle_args *gpiospec, 907 u32 *flags) 908 { 909 int pin, base; 910 911 base = PINS_PER_BANK * gpiospec->args[0]; 912 pin = base + gpiospec->args[1]; 913 914 if (pin > gc->ngpio) 915 return -EINVAL; 916 917 if (flags) 918 *flags = gpiospec->args[2]; 919 920 return pin; 921 } 922 923 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 924 { 925 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 926 struct sunxi_desc_function *desc; 927 unsigned pinnum = pctl->desc->pin_base + offset; 928 unsigned irqnum; 929 930 if (offset >= chip->ngpio) 931 return -ENXIO; 932 933 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq"); 934 if (!desc) 935 return -EINVAL; 936 937 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum; 938 939 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n", 940 chip->label, offset + chip->base, irqnum); 941 942 return irq_find_mapping(pctl->domain, irqnum); 943 } 944 945 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) 946 { 947 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 948 struct sunxi_desc_function *func; 949 int ret; 950 951 func = sunxi_pinctrl_desc_find_function_by_pin(pctl, 952 pctl->irq_array[d->hwirq], "irq"); 953 if (!func) 954 return -EINVAL; 955 956 ret = gpiochip_lock_as_irq(pctl->chip, 957 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 958 if (ret) { 959 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 960 irqd_to_hwirq(d)); 961 return ret; 962 } 963 964 /* Change muxing to INT mode */ 965 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); 966 967 return 0; 968 } 969 970 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) 971 { 972 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 973 974 gpiochip_unlock_as_irq(pctl->chip, 975 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 976 } 977 978 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) 979 { 980 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 981 u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq); 982 u8 index = sunxi_irq_cfg_offset(d->hwirq); 983 unsigned long flags; 984 u32 regval; 985 u8 mode; 986 987 switch (type) { 988 case IRQ_TYPE_EDGE_RISING: 989 mode = IRQ_EDGE_RISING; 990 break; 991 case IRQ_TYPE_EDGE_FALLING: 992 mode = IRQ_EDGE_FALLING; 993 break; 994 case IRQ_TYPE_EDGE_BOTH: 995 mode = IRQ_EDGE_BOTH; 996 break; 997 case IRQ_TYPE_LEVEL_HIGH: 998 mode = IRQ_LEVEL_HIGH; 999 break; 1000 case IRQ_TYPE_LEVEL_LOW: 1001 mode = IRQ_LEVEL_LOW; 1002 break; 1003 default: 1004 return -EINVAL; 1005 } 1006 1007 raw_spin_lock_irqsave(&pctl->lock, flags); 1008 1009 if (type & IRQ_TYPE_LEVEL_MASK) 1010 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip, 1011 handle_fasteoi_irq, NULL); 1012 else 1013 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip, 1014 handle_edge_irq, NULL); 1015 1016 regval = readl(pctl->membase + reg); 1017 regval &= ~(IRQ_CFG_IRQ_MASK << index); 1018 writel(regval | (mode << index), pctl->membase + reg); 1019 1020 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1021 1022 return 0; 1023 } 1024 1025 static void sunxi_pinctrl_irq_ack(struct irq_data *d) 1026 { 1027 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1028 u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq); 1029 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 1030 1031 /* Clear the IRQ */ 1032 writel(1 << status_idx, pctl->membase + status_reg); 1033 } 1034 1035 static void sunxi_pinctrl_irq_mask(struct irq_data *d) 1036 { 1037 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1038 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); 1039 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 1040 unsigned long flags; 1041 u32 val; 1042 1043 raw_spin_lock_irqsave(&pctl->lock, flags); 1044 1045 /* Mask the IRQ */ 1046 val = readl(pctl->membase + reg); 1047 writel(val & ~(1 << idx), pctl->membase + reg); 1048 1049 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1050 } 1051 1052 static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 1053 { 1054 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1055 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); 1056 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 1057 unsigned long flags; 1058 u32 val; 1059 1060 raw_spin_lock_irqsave(&pctl->lock, flags); 1061 1062 /* Unmask the IRQ */ 1063 val = readl(pctl->membase + reg); 1064 writel(val | (1 << idx), pctl->membase + reg); 1065 1066 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1067 } 1068 1069 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) 1070 { 1071 sunxi_pinctrl_irq_ack(d); 1072 sunxi_pinctrl_irq_unmask(d); 1073 } 1074 1075 static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on) 1076 { 1077 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1078 u8 bank = d->hwirq / IRQ_PER_BANK; 1079 1080 return irq_set_irq_wake(pctl->irq[bank], on); 1081 } 1082 1083 static struct irq_chip sunxi_pinctrl_edge_irq_chip = { 1084 .name = "sunxi_pio_edge", 1085 .irq_ack = sunxi_pinctrl_irq_ack, 1086 .irq_mask = sunxi_pinctrl_irq_mask, 1087 .irq_unmask = sunxi_pinctrl_irq_unmask, 1088 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 1089 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 1090 .irq_set_type = sunxi_pinctrl_irq_set_type, 1091 .irq_set_wake = sunxi_pinctrl_irq_set_wake, 1092 .flags = IRQCHIP_MASK_ON_SUSPEND, 1093 }; 1094 1095 static struct irq_chip sunxi_pinctrl_level_irq_chip = { 1096 .name = "sunxi_pio_level", 1097 .irq_eoi = sunxi_pinctrl_irq_ack, 1098 .irq_mask = sunxi_pinctrl_irq_mask, 1099 .irq_unmask = sunxi_pinctrl_irq_unmask, 1100 /* Define irq_enable / disable to avoid spurious irqs for drivers 1101 * using these to suppress irqs while they clear the irq source */ 1102 .irq_enable = sunxi_pinctrl_irq_ack_unmask, 1103 .irq_disable = sunxi_pinctrl_irq_mask, 1104 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 1105 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 1106 .irq_set_type = sunxi_pinctrl_irq_set_type, 1107 .irq_set_wake = sunxi_pinctrl_irq_set_wake, 1108 .flags = IRQCHIP_EOI_THREADED | 1109 IRQCHIP_MASK_ON_SUSPEND | 1110 IRQCHIP_EOI_IF_HANDLED, 1111 }; 1112 1113 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, 1114 struct device_node *node, 1115 const u32 *intspec, 1116 unsigned int intsize, 1117 unsigned long *out_hwirq, 1118 unsigned int *out_type) 1119 { 1120 struct sunxi_pinctrl *pctl = d->host_data; 1121 struct sunxi_desc_function *desc; 1122 int pin, base; 1123 1124 if (intsize < 3) 1125 return -EINVAL; 1126 1127 base = PINS_PER_BANK * intspec[0]; 1128 pin = pctl->desc->pin_base + base + intspec[1]; 1129 1130 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); 1131 if (!desc) 1132 return -EINVAL; 1133 1134 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum; 1135 *out_type = intspec[2]; 1136 1137 return 0; 1138 } 1139 1140 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = { 1141 .xlate = sunxi_pinctrl_irq_of_xlate, 1142 }; 1143 1144 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) 1145 { 1146 unsigned int irq = irq_desc_get_irq(desc); 1147 struct irq_chip *chip = irq_desc_get_chip(desc); 1148 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc); 1149 unsigned long bank, reg, val; 1150 1151 for (bank = 0; bank < pctl->desc->irq_banks; bank++) 1152 if (irq == pctl->irq[bank]) 1153 break; 1154 1155 WARN_ON(bank == pctl->desc->irq_banks); 1156 1157 chained_irq_enter(chip, desc); 1158 1159 reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); 1160 val = readl(pctl->membase + reg); 1161 1162 if (val) { 1163 int irqoffset; 1164 1165 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) 1166 generic_handle_domain_irq(pctl->domain, 1167 bank * IRQ_PER_BANK + irqoffset); 1168 } 1169 1170 chained_irq_exit(chip, desc); 1171 } 1172 1173 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 1174 const char *name) 1175 { 1176 struct sunxi_pinctrl_function *func = pctl->functions; 1177 1178 while (func->name) { 1179 /* function already there */ 1180 if (strcmp(func->name, name) == 0) { 1181 func->ngroups++; 1182 return -EEXIST; 1183 } 1184 func++; 1185 } 1186 1187 func->name = name; 1188 func->ngroups = 1; 1189 1190 pctl->nfunctions++; 1191 1192 return 0; 1193 } 1194 1195 static int sunxi_pinctrl_build_state(struct platform_device *pdev) 1196 { 1197 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 1198 void *ptr; 1199 int i; 1200 1201 /* 1202 * Allocate groups 1203 * 1204 * We assume that the number of groups is the number of pins 1205 * given in the data array. 1206 1207 * This will not always be true, since some pins might not be 1208 * available in the current variant, but fortunately for us, 1209 * this means that the number of pins is the maximum group 1210 * number we will ever see. 1211 */ 1212 pctl->groups = devm_kcalloc(&pdev->dev, 1213 pctl->desc->npins, sizeof(*pctl->groups), 1214 GFP_KERNEL); 1215 if (!pctl->groups) 1216 return -ENOMEM; 1217 1218 for (i = 0; i < pctl->desc->npins; i++) { 1219 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1220 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups; 1221 1222 if (pin->variant && !(pctl->variant & pin->variant)) 1223 continue; 1224 1225 group->name = pin->pin.name; 1226 group->pin = pin->pin.number; 1227 1228 /* And now we count the actual number of pins / groups */ 1229 pctl->ngroups++; 1230 } 1231 1232 /* 1233 * Find an upper bound for the maximum number of functions: in 1234 * the worst case we have gpio_in, gpio_out, irq and up to four 1235 * special functions per pin, plus one entry for the sentinel. 1236 * We'll reallocate that later anyway. 1237 */ 1238 pctl->functions = kcalloc(4 * pctl->ngroups + 4, 1239 sizeof(*pctl->functions), 1240 GFP_KERNEL); 1241 if (!pctl->functions) 1242 return -ENOMEM; 1243 1244 /* Count functions and their associated groups */ 1245 for (i = 0; i < pctl->desc->npins; i++) { 1246 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1247 struct sunxi_desc_function *func; 1248 1249 if (pin->variant && !(pctl->variant & pin->variant)) 1250 continue; 1251 1252 for (func = pin->functions; func->name; func++) { 1253 if (func->variant && !(pctl->variant & func->variant)) 1254 continue; 1255 1256 /* Create interrupt mapping while we're at it */ 1257 if (!strcmp(func->name, "irq")) { 1258 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; 1259 pctl->irq_array[irqnum] = pin->pin.number; 1260 } 1261 1262 sunxi_pinctrl_add_function(pctl, func->name); 1263 } 1264 } 1265 1266 /* And now allocated and fill the array for real */ 1267 ptr = krealloc(pctl->functions, 1268 pctl->nfunctions * sizeof(*pctl->functions), 1269 GFP_KERNEL); 1270 if (!ptr) { 1271 kfree(pctl->functions); 1272 pctl->functions = NULL; 1273 return -ENOMEM; 1274 } 1275 pctl->functions = ptr; 1276 1277 for (i = 0; i < pctl->desc->npins; i++) { 1278 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1279 struct sunxi_desc_function *func; 1280 1281 if (pin->variant && !(pctl->variant & pin->variant)) 1282 continue; 1283 1284 for (func = pin->functions; func->name; func++) { 1285 struct sunxi_pinctrl_function *func_item; 1286 const char **func_grp; 1287 1288 if (func->variant && !(pctl->variant & func->variant)) 1289 continue; 1290 1291 func_item = sunxi_pinctrl_find_function_by_name(pctl, 1292 func->name); 1293 if (!func_item) { 1294 kfree(pctl->functions); 1295 return -EINVAL; 1296 } 1297 1298 if (!func_item->groups) { 1299 func_item->groups = 1300 devm_kcalloc(&pdev->dev, 1301 func_item->ngroups, 1302 sizeof(*func_item->groups), 1303 GFP_KERNEL); 1304 if (!func_item->groups) { 1305 kfree(pctl->functions); 1306 return -ENOMEM; 1307 } 1308 } 1309 1310 func_grp = func_item->groups; 1311 while (*func_grp) 1312 func_grp++; 1313 1314 *func_grp = pin->pin.name; 1315 } 1316 } 1317 1318 return 0; 1319 } 1320 1321 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff) 1322 { 1323 unsigned long clock = clk_get_rate(clk); 1324 unsigned int best_diff, best_div; 1325 int i; 1326 1327 best_diff = abs(freq - clock); 1328 best_div = 0; 1329 1330 for (i = 1; i < 8; i++) { 1331 int cur_diff = abs(freq - (clock >> i)); 1332 1333 if (cur_diff < best_diff) { 1334 best_diff = cur_diff; 1335 best_div = i; 1336 } 1337 } 1338 1339 *diff = best_diff; 1340 return best_div; 1341 } 1342 1343 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, 1344 struct device_node *node) 1345 { 1346 unsigned int hosc_diff, losc_diff; 1347 unsigned int hosc_div, losc_div; 1348 struct clk *hosc, *losc; 1349 u8 div, src; 1350 int i, ret; 1351 1352 /* Deal with old DTs that didn't have the oscillators */ 1353 if (of_clk_get_parent_count(node) != 3) 1354 return 0; 1355 1356 /* If we don't have any setup, bail out */ 1357 if (!of_find_property(node, "input-debounce", NULL)) 1358 return 0; 1359 1360 losc = devm_clk_get(pctl->dev, "losc"); 1361 if (IS_ERR(losc)) 1362 return PTR_ERR(losc); 1363 1364 hosc = devm_clk_get(pctl->dev, "hosc"); 1365 if (IS_ERR(hosc)) 1366 return PTR_ERR(hosc); 1367 1368 for (i = 0; i < pctl->desc->irq_banks; i++) { 1369 unsigned long debounce_freq; 1370 u32 debounce; 1371 1372 ret = of_property_read_u32_index(node, "input-debounce", 1373 i, &debounce); 1374 if (ret) 1375 return ret; 1376 1377 if (!debounce) 1378 continue; 1379 1380 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce); 1381 losc_div = sunxi_pinctrl_get_debounce_div(losc, 1382 debounce_freq, 1383 &losc_diff); 1384 1385 hosc_div = sunxi_pinctrl_get_debounce_div(hosc, 1386 debounce_freq, 1387 &hosc_diff); 1388 1389 if (hosc_diff < losc_diff) { 1390 div = hosc_div; 1391 src = 1; 1392 } else { 1393 div = losc_div; 1394 src = 0; 1395 } 1396 1397 writel(src | div << 4, 1398 pctl->membase + 1399 sunxi_irq_debounce_reg_from_bank(pctl->desc, i)); 1400 } 1401 1402 return 0; 1403 } 1404 1405 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, 1406 const struct sunxi_pinctrl_desc *desc, 1407 unsigned long variant) 1408 { 1409 struct device_node *node = pdev->dev.of_node; 1410 struct pinctrl_desc *pctrl_desc; 1411 struct pinctrl_pin_desc *pins; 1412 struct sunxi_pinctrl *pctl; 1413 struct pinmux_ops *pmxops; 1414 int i, ret, last_pin, pin_idx; 1415 struct clk *clk; 1416 1417 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1418 if (!pctl) 1419 return -ENOMEM; 1420 platform_set_drvdata(pdev, pctl); 1421 1422 raw_spin_lock_init(&pctl->lock); 1423 1424 pctl->membase = devm_platform_ioremap_resource(pdev, 0); 1425 if (IS_ERR(pctl->membase)) 1426 return PTR_ERR(pctl->membase); 1427 1428 pctl->dev = &pdev->dev; 1429 pctl->desc = desc; 1430 pctl->variant = variant; 1431 1432 pctl->irq_array = devm_kcalloc(&pdev->dev, 1433 IRQ_PER_BANK * pctl->desc->irq_banks, 1434 sizeof(*pctl->irq_array), 1435 GFP_KERNEL); 1436 if (!pctl->irq_array) 1437 return -ENOMEM; 1438 1439 ret = sunxi_pinctrl_build_state(pdev); 1440 if (ret) { 1441 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 1442 return ret; 1443 } 1444 1445 pins = devm_kcalloc(&pdev->dev, 1446 pctl->desc->npins, sizeof(*pins), 1447 GFP_KERNEL); 1448 if (!pins) 1449 return -ENOMEM; 1450 1451 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) { 1452 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1453 1454 if (pin->variant && !(pctl->variant & pin->variant)) 1455 continue; 1456 1457 pins[pin_idx++] = pin->pin; 1458 } 1459 1460 pctrl_desc = devm_kzalloc(&pdev->dev, 1461 sizeof(*pctrl_desc), 1462 GFP_KERNEL); 1463 if (!pctrl_desc) 1464 return -ENOMEM; 1465 1466 pctrl_desc->name = dev_name(&pdev->dev); 1467 pctrl_desc->owner = THIS_MODULE; 1468 pctrl_desc->pins = pins; 1469 pctrl_desc->npins = pctl->ngroups; 1470 pctrl_desc->confops = &sunxi_pconf_ops; 1471 pctrl_desc->pctlops = &sunxi_pctrl_ops; 1472 1473 pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops), 1474 GFP_KERNEL); 1475 if (!pmxops) 1476 return -ENOMEM; 1477 1478 if (desc->disable_strict_mode) 1479 pmxops->strict = false; 1480 1481 pctrl_desc->pmxops = pmxops; 1482 1483 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); 1484 if (IS_ERR(pctl->pctl_dev)) { 1485 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1486 return PTR_ERR(pctl->pctl_dev); 1487 } 1488 1489 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1490 if (!pctl->chip) 1491 return -ENOMEM; 1492 1493 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 1494 pctl->chip->owner = THIS_MODULE; 1495 pctl->chip->request = gpiochip_generic_request; 1496 pctl->chip->free = gpiochip_generic_free; 1497 pctl->chip->set_config = gpiochip_generic_config; 1498 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input; 1499 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output; 1500 pctl->chip->get = sunxi_pinctrl_gpio_get; 1501 pctl->chip->set = sunxi_pinctrl_gpio_set; 1502 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate; 1503 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq; 1504 pctl->chip->of_gpio_n_cells = 3; 1505 pctl->chip->can_sleep = false; 1506 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - 1507 pctl->desc->pin_base; 1508 pctl->chip->label = dev_name(&pdev->dev); 1509 pctl->chip->parent = &pdev->dev; 1510 pctl->chip->base = pctl->desc->pin_base; 1511 1512 ret = gpiochip_add_data(pctl->chip, pctl); 1513 if (ret) 1514 return ret; 1515 1516 for (i = 0; i < pctl->desc->npins; i++) { 1517 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1518 1519 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1520 pin->pin.number - pctl->desc->pin_base, 1521 pin->pin.number, 1); 1522 if (ret) 1523 goto gpiochip_error; 1524 } 1525 1526 ret = of_clk_get_parent_count(node); 1527 clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb"); 1528 if (IS_ERR(clk)) { 1529 ret = PTR_ERR(clk); 1530 goto gpiochip_error; 1531 } 1532 1533 ret = clk_prepare_enable(clk); 1534 if (ret) 1535 goto gpiochip_error; 1536 1537 pctl->irq = devm_kcalloc(&pdev->dev, 1538 pctl->desc->irq_banks, 1539 sizeof(*pctl->irq), 1540 GFP_KERNEL); 1541 if (!pctl->irq) { 1542 ret = -ENOMEM; 1543 goto clk_error; 1544 } 1545 1546 for (i = 0; i < pctl->desc->irq_banks; i++) { 1547 pctl->irq[i] = platform_get_irq(pdev, i); 1548 if (pctl->irq[i] < 0) { 1549 ret = pctl->irq[i]; 1550 goto clk_error; 1551 } 1552 } 1553 1554 pctl->domain = irq_domain_add_linear(node, 1555 pctl->desc->irq_banks * IRQ_PER_BANK, 1556 &sunxi_pinctrl_irq_domain_ops, 1557 pctl); 1558 if (!pctl->domain) { 1559 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 1560 ret = -ENOMEM; 1561 goto clk_error; 1562 } 1563 1564 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { 1565 int irqno = irq_create_mapping(pctl->domain, i); 1566 1567 irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class, 1568 &sunxi_pinctrl_irq_request_class); 1569 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, 1570 handle_edge_irq); 1571 irq_set_chip_data(irqno, pctl); 1572 } 1573 1574 for (i = 0; i < pctl->desc->irq_banks; i++) { 1575 /* Mask and clear all IRQs before registering a handler */ 1576 writel(0, pctl->membase + 1577 sunxi_irq_ctrl_reg_from_bank(pctl->desc, i)); 1578 writel(0xffffffff, 1579 pctl->membase + 1580 sunxi_irq_status_reg_from_bank(pctl->desc, i)); 1581 1582 irq_set_chained_handler_and_data(pctl->irq[i], 1583 sunxi_pinctrl_irq_handler, 1584 pctl); 1585 } 1586 1587 sunxi_pinctrl_setup_debounce(pctl, node); 1588 1589 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1590 1591 return 0; 1592 1593 clk_error: 1594 clk_disable_unprepare(clk); 1595 gpiochip_error: 1596 gpiochip_remove(pctl->chip); 1597 return ret; 1598 } 1599