1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/io.h> 14 #include <linux/clk.h> 15 #include <linux/gpio.h> 16 #include <linux/irqdomain.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_device.h> 22 #include <linux/of_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/machine.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinconf-generic.h> 27 #include <linux/pinctrl/pinmux.h> 28 #include <linux/platform_device.h> 29 #include <linux/slab.h> 30 31 #include "../core.h" 32 #include "pinctrl-sunxi.h" 33 34 static struct sunxi_pinctrl_group * 35 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 36 { 37 int i; 38 39 for (i = 0; i < pctl->ngroups; i++) { 40 struct sunxi_pinctrl_group *grp = pctl->groups + i; 41 42 if (!strcmp(grp->name, group)) 43 return grp; 44 } 45 46 return NULL; 47 } 48 49 static struct sunxi_pinctrl_function * 50 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 51 const char *name) 52 { 53 struct sunxi_pinctrl_function *func = pctl->functions; 54 int i; 55 56 for (i = 0; i < pctl->nfunctions; i++) { 57 if (!func[i].name) 58 break; 59 60 if (!strcmp(func[i].name, name)) 61 return func + i; 62 } 63 64 return NULL; 65 } 66 67 static struct sunxi_desc_function * 68 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 69 const char *pin_name, 70 const char *func_name) 71 { 72 int i; 73 74 for (i = 0; i < pctl->desc->npins; i++) { 75 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 76 77 if (!strcmp(pin->pin.name, pin_name)) { 78 struct sunxi_desc_function *func = pin->functions; 79 80 while (func->name) { 81 if (!strcmp(func->name, func_name)) 82 return func; 83 84 func++; 85 } 86 } 87 } 88 89 return NULL; 90 } 91 92 static struct sunxi_desc_function * 93 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, 94 const u16 pin_num, 95 const char *func_name) 96 { 97 int i; 98 99 for (i = 0; i < pctl->desc->npins; i++) { 100 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 101 102 if (pin->pin.number == pin_num) { 103 struct sunxi_desc_function *func = pin->functions; 104 105 while (func->name) { 106 if (!strcmp(func->name, func_name)) 107 return func; 108 109 func++; 110 } 111 } 112 } 113 114 return NULL; 115 } 116 117 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 118 { 119 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 120 121 return pctl->ngroups; 122 } 123 124 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 125 unsigned group) 126 { 127 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 128 129 return pctl->groups[group].name; 130 } 131 132 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 133 unsigned group, 134 const unsigned **pins, 135 unsigned *num_pins) 136 { 137 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 138 139 *pins = (unsigned *)&pctl->groups[group].pin; 140 *num_pins = 1; 141 142 return 0; 143 } 144 145 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 146 struct device_node *node, 147 struct pinctrl_map **map, 148 unsigned *num_maps) 149 { 150 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 151 unsigned long *pinconfig; 152 struct property *prop; 153 const char *function; 154 const char *group; 155 int ret, nmaps, i = 0; 156 u32 val; 157 158 *map = NULL; 159 *num_maps = 0; 160 161 ret = of_property_read_string(node, "allwinner,function", &function); 162 if (ret) { 163 dev_err(pctl->dev, 164 "missing allwinner,function property in node %s\n", 165 node->name); 166 return -EINVAL; 167 } 168 169 nmaps = of_property_count_strings(node, "allwinner,pins") * 2; 170 if (nmaps < 0) { 171 dev_err(pctl->dev, 172 "missing allwinner,pins property in node %s\n", 173 node->name); 174 return -EINVAL; 175 } 176 177 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); 178 if (!*map) 179 return -ENOMEM; 180 181 of_property_for_each_string(node, "allwinner,pins", prop, group) { 182 struct sunxi_pinctrl_group *grp = 183 sunxi_pinctrl_find_group_by_name(pctl, group); 184 int j = 0, configlen = 0; 185 186 if (!grp) { 187 dev_err(pctl->dev, "unknown pin %s", group); 188 continue; 189 } 190 191 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 192 grp->name, 193 function)) { 194 dev_err(pctl->dev, "unsupported function %s on pin %s", 195 function, group); 196 continue; 197 } 198 199 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 200 (*map)[i].data.mux.group = group; 201 (*map)[i].data.mux.function = function; 202 203 i++; 204 205 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 206 (*map)[i].data.configs.group_or_pin = group; 207 208 if (of_find_property(node, "allwinner,drive", NULL)) 209 configlen++; 210 if (of_find_property(node, "allwinner,pull", NULL)) 211 configlen++; 212 213 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); 214 215 if (!of_property_read_u32(node, "allwinner,drive", &val)) { 216 u16 strength = (val + 1) * 10; 217 pinconfig[j++] = 218 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 219 strength); 220 } 221 222 if (!of_property_read_u32(node, "allwinner,pull", &val)) { 223 enum pin_config_param pull = PIN_CONFIG_END; 224 if (val == 1) 225 pull = PIN_CONFIG_BIAS_PULL_UP; 226 else if (val == 2) 227 pull = PIN_CONFIG_BIAS_PULL_DOWN; 228 pinconfig[j++] = pinconf_to_config_packed(pull, 0); 229 } 230 231 (*map)[i].data.configs.configs = pinconfig; 232 (*map)[i].data.configs.num_configs = configlen; 233 234 i++; 235 } 236 237 *num_maps = nmaps; 238 239 return 0; 240 } 241 242 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 243 struct pinctrl_map *map, 244 unsigned num_maps) 245 { 246 int i; 247 248 for (i = 0; i < num_maps; i++) { 249 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) 250 kfree(map[i].data.configs.configs); 251 } 252 253 kfree(map); 254 } 255 256 static const struct pinctrl_ops sunxi_pctrl_ops = { 257 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 258 .dt_free_map = sunxi_pctrl_dt_free_map, 259 .get_groups_count = sunxi_pctrl_get_groups_count, 260 .get_group_name = sunxi_pctrl_get_group_name, 261 .get_group_pins = sunxi_pctrl_get_group_pins, 262 }; 263 264 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 265 unsigned group, 266 unsigned long *config) 267 { 268 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 269 270 *config = pctl->groups[group].config; 271 272 return 0; 273 } 274 275 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, 276 unsigned group, 277 unsigned long *configs, 278 unsigned num_configs) 279 { 280 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 281 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 282 unsigned long flags; 283 unsigned pin = g->pin - pctl->desc->pin_base; 284 u32 val, mask; 285 u16 strength; 286 u8 dlevel; 287 int i; 288 289 spin_lock_irqsave(&pctl->lock, flags); 290 291 for (i = 0; i < num_configs; i++) { 292 switch (pinconf_to_config_param(configs[i])) { 293 case PIN_CONFIG_DRIVE_STRENGTH: 294 strength = pinconf_to_config_argument(configs[i]); 295 if (strength > 40) { 296 spin_unlock_irqrestore(&pctl->lock, flags); 297 return -EINVAL; 298 } 299 /* 300 * We convert from mA to what the register expects: 301 * 0: 10mA 302 * 1: 20mA 303 * 2: 30mA 304 * 3: 40mA 305 */ 306 dlevel = strength / 10 - 1; 307 val = readl(pctl->membase + sunxi_dlevel_reg(pin)); 308 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin); 309 writel((val & ~mask) 310 | dlevel << sunxi_dlevel_offset(pin), 311 pctl->membase + sunxi_dlevel_reg(pin)); 312 break; 313 case PIN_CONFIG_BIAS_PULL_UP: 314 val = readl(pctl->membase + sunxi_pull_reg(pin)); 315 mask = PULL_PINS_MASK << sunxi_pull_offset(pin); 316 writel((val & ~mask) | 1 << sunxi_pull_offset(pin), 317 pctl->membase + sunxi_pull_reg(pin)); 318 break; 319 case PIN_CONFIG_BIAS_PULL_DOWN: 320 val = readl(pctl->membase + sunxi_pull_reg(pin)); 321 mask = PULL_PINS_MASK << sunxi_pull_offset(pin); 322 writel((val & ~mask) | 2 << sunxi_pull_offset(pin), 323 pctl->membase + sunxi_pull_reg(pin)); 324 break; 325 default: 326 break; 327 } 328 /* cache the config value */ 329 g->config = configs[i]; 330 } /* for each config */ 331 332 spin_unlock_irqrestore(&pctl->lock, flags); 333 334 return 0; 335 } 336 337 static const struct pinconf_ops sunxi_pconf_ops = { 338 .pin_config_group_get = sunxi_pconf_group_get, 339 .pin_config_group_set = sunxi_pconf_group_set, 340 }; 341 342 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 343 { 344 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 345 346 return pctl->nfunctions; 347 } 348 349 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 350 unsigned function) 351 { 352 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 353 354 return pctl->functions[function].name; 355 } 356 357 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 358 unsigned function, 359 const char * const **groups, 360 unsigned * const num_groups) 361 { 362 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 363 364 *groups = pctl->functions[function].groups; 365 *num_groups = pctl->functions[function].ngroups; 366 367 return 0; 368 } 369 370 static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 371 unsigned pin, 372 u8 config) 373 { 374 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 375 unsigned long flags; 376 u32 val, mask; 377 378 spin_lock_irqsave(&pctl->lock, flags); 379 380 pin -= pctl->desc->pin_base; 381 val = readl(pctl->membase + sunxi_mux_reg(pin)); 382 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 383 writel((val & ~mask) | config << sunxi_mux_offset(pin), 384 pctl->membase + sunxi_mux_reg(pin)); 385 386 spin_unlock_irqrestore(&pctl->lock, flags); 387 } 388 389 static int sunxi_pmx_enable(struct pinctrl_dev *pctldev, 390 unsigned function, 391 unsigned group) 392 { 393 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 394 struct sunxi_pinctrl_group *g = pctl->groups + group; 395 struct sunxi_pinctrl_function *func = pctl->functions + function; 396 struct sunxi_desc_function *desc = 397 sunxi_pinctrl_desc_find_function_by_name(pctl, 398 g->name, 399 func->name); 400 401 if (!desc) 402 return -EINVAL; 403 404 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 405 406 return 0; 407 } 408 409 static int 410 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 411 struct pinctrl_gpio_range *range, 412 unsigned offset, 413 bool input) 414 { 415 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 416 struct sunxi_desc_function *desc; 417 const char *func; 418 419 if (input) 420 func = "gpio_in"; 421 else 422 func = "gpio_out"; 423 424 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); 425 if (!desc) 426 return -EINVAL; 427 428 sunxi_pmx_set(pctldev, offset, desc->muxval); 429 430 return 0; 431 } 432 433 static const struct pinmux_ops sunxi_pmx_ops = { 434 .get_functions_count = sunxi_pmx_get_funcs_cnt, 435 .get_function_name = sunxi_pmx_get_func_name, 436 .get_function_groups = sunxi_pmx_get_func_groups, 437 .enable = sunxi_pmx_enable, 438 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 439 }; 440 441 static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset) 442 { 443 return pinctrl_request_gpio(chip->base + offset); 444 } 445 446 static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset) 447 { 448 pinctrl_free_gpio(chip->base + offset); 449 } 450 451 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 452 unsigned offset) 453 { 454 return pinctrl_gpio_direction_input(chip->base + offset); 455 } 456 457 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 458 { 459 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 460 461 u32 reg = sunxi_data_reg(offset); 462 u8 index = sunxi_data_offset(offset); 463 u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; 464 465 return val; 466 } 467 468 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 469 unsigned offset, int value) 470 { 471 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 472 u32 reg = sunxi_data_reg(offset); 473 u8 index = sunxi_data_offset(offset); 474 unsigned long flags; 475 u32 regval; 476 477 spin_lock_irqsave(&pctl->lock, flags); 478 479 regval = readl(pctl->membase + reg); 480 481 if (value) 482 regval |= BIT(index); 483 else 484 regval &= ~(BIT(index)); 485 486 writel(regval, pctl->membase + reg); 487 488 spin_unlock_irqrestore(&pctl->lock, flags); 489 } 490 491 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 492 unsigned offset, int value) 493 { 494 sunxi_pinctrl_gpio_set(chip, offset, value); 495 return pinctrl_gpio_direction_output(chip->base + offset); 496 } 497 498 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 499 const struct of_phandle_args *gpiospec, 500 u32 *flags) 501 { 502 int pin, base; 503 504 base = PINS_PER_BANK * gpiospec->args[0]; 505 pin = base + gpiospec->args[1]; 506 507 if (pin > (gc->base + gc->ngpio)) 508 return -EINVAL; 509 510 if (flags) 511 *flags = gpiospec->args[2]; 512 513 return pin; 514 } 515 516 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 517 { 518 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 519 struct sunxi_desc_function *desc; 520 521 if (offset >= chip->ngpio) 522 return -ENXIO; 523 524 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq"); 525 if (!desc) 526 return -EINVAL; 527 528 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", 529 chip->label, offset + chip->base, desc->irqnum); 530 531 return irq_find_mapping(pctl->domain, desc->irqnum); 532 } 533 534 535 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, 536 unsigned int type) 537 { 538 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 539 u32 reg = sunxi_irq_cfg_reg(d->hwirq); 540 u8 index = sunxi_irq_cfg_offset(d->hwirq); 541 unsigned long flags; 542 u32 regval; 543 u8 mode; 544 545 switch (type) { 546 case IRQ_TYPE_EDGE_RISING: 547 mode = IRQ_EDGE_RISING; 548 break; 549 case IRQ_TYPE_EDGE_FALLING: 550 mode = IRQ_EDGE_FALLING; 551 break; 552 case IRQ_TYPE_EDGE_BOTH: 553 mode = IRQ_EDGE_BOTH; 554 break; 555 case IRQ_TYPE_LEVEL_HIGH: 556 mode = IRQ_LEVEL_HIGH; 557 break; 558 case IRQ_TYPE_LEVEL_LOW: 559 mode = IRQ_LEVEL_LOW; 560 break; 561 default: 562 return -EINVAL; 563 } 564 565 spin_lock_irqsave(&pctl->lock, flags); 566 567 regval = readl(pctl->membase + reg); 568 regval &= ~(IRQ_CFG_IRQ_MASK << index); 569 writel(regval | (mode << index), pctl->membase + reg); 570 571 spin_unlock_irqrestore(&pctl->lock, flags); 572 573 return 0; 574 } 575 576 static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d) 577 { 578 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 579 u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq); 580 u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq); 581 u32 status_reg = sunxi_irq_status_reg(d->hwirq); 582 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 583 unsigned long flags; 584 u32 val; 585 586 spin_lock_irqsave(&pctl->lock, flags); 587 588 /* Mask the IRQ */ 589 val = readl(pctl->membase + ctrl_reg); 590 writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg); 591 592 /* Clear the IRQ */ 593 writel(1 << status_idx, pctl->membase + status_reg); 594 595 spin_unlock_irqrestore(&pctl->lock, flags); 596 } 597 598 static void sunxi_pinctrl_irq_mask(struct irq_data *d) 599 { 600 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 601 u32 reg = sunxi_irq_ctrl_reg(d->hwirq); 602 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 603 unsigned long flags; 604 u32 val; 605 606 spin_lock_irqsave(&pctl->lock, flags); 607 608 /* Mask the IRQ */ 609 val = readl(pctl->membase + reg); 610 writel(val & ~(1 << idx), pctl->membase + reg); 611 612 spin_unlock_irqrestore(&pctl->lock, flags); 613 } 614 615 static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 616 { 617 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 618 struct sunxi_desc_function *func; 619 u32 reg = sunxi_irq_ctrl_reg(d->hwirq); 620 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 621 unsigned long flags; 622 u32 val; 623 624 func = sunxi_pinctrl_desc_find_function_by_pin(pctl, 625 pctl->irq_array[d->hwirq], 626 "irq"); 627 628 /* Change muxing to INT mode */ 629 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); 630 631 spin_lock_irqsave(&pctl->lock, flags); 632 633 /* Unmask the IRQ */ 634 val = readl(pctl->membase + reg); 635 writel(val | (1 << idx), pctl->membase + reg); 636 637 spin_unlock_irqrestore(&pctl->lock, flags); 638 } 639 640 static struct irq_chip sunxi_pinctrl_irq_chip = { 641 .irq_mask = sunxi_pinctrl_irq_mask, 642 .irq_mask_ack = sunxi_pinctrl_irq_mask_ack, 643 .irq_unmask = sunxi_pinctrl_irq_unmask, 644 .irq_set_type = sunxi_pinctrl_irq_set_type, 645 }; 646 647 static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) 648 { 649 struct irq_chip *chip = irq_get_chip(irq); 650 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); 651 const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG); 652 653 /* Clear all interrupts */ 654 writel(reg, pctl->membase + IRQ_STATUS_REG); 655 656 if (reg) { 657 int irqoffset; 658 659 chained_irq_enter(chip, desc); 660 for_each_set_bit(irqoffset, ®, SUNXI_IRQ_NUMBER) { 661 int pin_irq = irq_find_mapping(pctl->domain, irqoffset); 662 generic_handle_irq(pin_irq); 663 } 664 chained_irq_exit(chip, desc); 665 } 666 } 667 668 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 669 const char *name) 670 { 671 struct sunxi_pinctrl_function *func = pctl->functions; 672 673 while (func->name) { 674 /* function already there */ 675 if (strcmp(func->name, name) == 0) { 676 func->ngroups++; 677 return -EEXIST; 678 } 679 func++; 680 } 681 682 func->name = name; 683 func->ngroups = 1; 684 685 pctl->nfunctions++; 686 687 return 0; 688 } 689 690 static int sunxi_pinctrl_build_state(struct platform_device *pdev) 691 { 692 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 693 int i; 694 695 pctl->ngroups = pctl->desc->npins; 696 697 /* Allocate groups */ 698 pctl->groups = devm_kzalloc(&pdev->dev, 699 pctl->ngroups * sizeof(*pctl->groups), 700 GFP_KERNEL); 701 if (!pctl->groups) 702 return -ENOMEM; 703 704 for (i = 0; i < pctl->desc->npins; i++) { 705 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 706 struct sunxi_pinctrl_group *group = pctl->groups + i; 707 708 group->name = pin->pin.name; 709 group->pin = pin->pin.number; 710 } 711 712 /* 713 * We suppose that we won't have any more functions than pins, 714 * we'll reallocate that later anyway 715 */ 716 pctl->functions = devm_kzalloc(&pdev->dev, 717 pctl->desc->npins * sizeof(*pctl->functions), 718 GFP_KERNEL); 719 if (!pctl->functions) 720 return -ENOMEM; 721 722 /* Count functions and their associated groups */ 723 for (i = 0; i < pctl->desc->npins; i++) { 724 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 725 struct sunxi_desc_function *func = pin->functions; 726 727 while (func->name) { 728 /* Create interrupt mapping while we're at it */ 729 if (!strcmp(func->name, "irq")) 730 pctl->irq_array[func->irqnum] = pin->pin.number; 731 sunxi_pinctrl_add_function(pctl, func->name); 732 func++; 733 } 734 } 735 736 pctl->functions = krealloc(pctl->functions, 737 pctl->nfunctions * sizeof(*pctl->functions), 738 GFP_KERNEL); 739 740 for (i = 0; i < pctl->desc->npins; i++) { 741 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 742 struct sunxi_desc_function *func = pin->functions; 743 744 while (func->name) { 745 struct sunxi_pinctrl_function *func_item; 746 const char **func_grp; 747 748 func_item = sunxi_pinctrl_find_function_by_name(pctl, 749 func->name); 750 if (!func_item) 751 return -EINVAL; 752 753 if (!func_item->groups) { 754 func_item->groups = 755 devm_kzalloc(&pdev->dev, 756 func_item->ngroups * sizeof(*func_item->groups), 757 GFP_KERNEL); 758 if (!func_item->groups) 759 return -ENOMEM; 760 } 761 762 func_grp = func_item->groups; 763 while (*func_grp) 764 func_grp++; 765 766 *func_grp = pin->pin.name; 767 func++; 768 } 769 } 770 771 return 0; 772 } 773 774 int sunxi_pinctrl_init(struct platform_device *pdev, 775 const struct sunxi_pinctrl_desc *desc) 776 { 777 struct device_node *node = pdev->dev.of_node; 778 struct pinctrl_desc *pctrl_desc; 779 struct pinctrl_pin_desc *pins; 780 struct sunxi_pinctrl *pctl; 781 struct resource *res; 782 int i, ret, last_pin; 783 struct clk *clk; 784 785 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 786 if (!pctl) 787 return -ENOMEM; 788 platform_set_drvdata(pdev, pctl); 789 790 spin_lock_init(&pctl->lock); 791 792 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 793 pctl->membase = devm_ioremap_resource(&pdev->dev, res); 794 if (IS_ERR(pctl->membase)) 795 return PTR_ERR(pctl->membase); 796 797 pctl->dev = &pdev->dev; 798 pctl->desc = desc; 799 800 ret = sunxi_pinctrl_build_state(pdev); 801 if (ret) { 802 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 803 return ret; 804 } 805 806 pins = devm_kzalloc(&pdev->dev, 807 pctl->desc->npins * sizeof(*pins), 808 GFP_KERNEL); 809 if (!pins) 810 return -ENOMEM; 811 812 for (i = 0; i < pctl->desc->npins; i++) 813 pins[i] = pctl->desc->pins[i].pin; 814 815 pctrl_desc = devm_kzalloc(&pdev->dev, 816 sizeof(*pctrl_desc), 817 GFP_KERNEL); 818 if (!pctrl_desc) 819 return -ENOMEM; 820 821 pctrl_desc->name = dev_name(&pdev->dev); 822 pctrl_desc->owner = THIS_MODULE; 823 pctrl_desc->pins = pins; 824 pctrl_desc->npins = pctl->desc->npins; 825 pctrl_desc->confops = &sunxi_pconf_ops; 826 pctrl_desc->pctlops = &sunxi_pctrl_ops; 827 pctrl_desc->pmxops = &sunxi_pmx_ops; 828 829 pctl->pctl_dev = pinctrl_register(pctrl_desc, 830 &pdev->dev, pctl); 831 if (!pctl->pctl_dev) { 832 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 833 return -EINVAL; 834 } 835 836 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 837 if (!pctl->chip) { 838 ret = -ENOMEM; 839 goto pinctrl_error; 840 } 841 842 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 843 pctl->chip->owner = THIS_MODULE; 844 pctl->chip->request = sunxi_pinctrl_gpio_request, 845 pctl->chip->free = sunxi_pinctrl_gpio_free, 846 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input, 847 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output, 848 pctl->chip->get = sunxi_pinctrl_gpio_get, 849 pctl->chip->set = sunxi_pinctrl_gpio_set, 850 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate, 851 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq, 852 pctl->chip->of_gpio_n_cells = 3, 853 pctl->chip->can_sleep = false, 854 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - 855 pctl->desc->pin_base; 856 pctl->chip->label = dev_name(&pdev->dev); 857 pctl->chip->dev = &pdev->dev; 858 pctl->chip->base = pctl->desc->pin_base; 859 860 ret = gpiochip_add(pctl->chip); 861 if (ret) 862 goto pinctrl_error; 863 864 for (i = 0; i < pctl->desc->npins; i++) { 865 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 866 867 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 868 pin->pin.number, 869 pin->pin.number, 1); 870 if (ret) 871 goto gpiochip_error; 872 } 873 874 clk = devm_clk_get(&pdev->dev, NULL); 875 if (IS_ERR(clk)) { 876 ret = PTR_ERR(clk); 877 goto gpiochip_error; 878 } 879 880 ret = clk_prepare_enable(clk); 881 if (ret) 882 goto gpiochip_error; 883 884 pctl->irq = irq_of_parse_and_map(node, 0); 885 if (!pctl->irq) { 886 ret = -EINVAL; 887 goto clk_error; 888 } 889 890 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER, 891 &irq_domain_simple_ops, NULL); 892 if (!pctl->domain) { 893 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 894 ret = -ENOMEM; 895 goto clk_error; 896 } 897 898 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) { 899 int irqno = irq_create_mapping(pctl->domain, i); 900 901 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip, 902 handle_simple_irq); 903 irq_set_chip_data(irqno, pctl); 904 }; 905 906 irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler); 907 irq_set_handler_data(pctl->irq, pctl); 908 909 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 910 911 return 0; 912 913 clk_error: 914 clk_disable_unprepare(clk); 915 gpiochip_error: 916 if (gpiochip_remove(pctl->chip)) 917 dev_err(&pdev->dev, "failed to remove gpio chip\n"); 918 pinctrl_error: 919 pinctrl_unregister(pctl->pctl_dev); 920 return ret; 921 } 922