1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/io.h> 14 #include <linux/clk.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/irqdomain.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_device.h> 22 #include <linux/of_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/machine.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinconf-generic.h> 27 #include <linux/pinctrl/pinmux.h> 28 #include <linux/platform_device.h> 29 #include <linux/slab.h> 30 31 #include "../core.h" 32 #include "../../gpio/gpiolib.h" 33 #include "pinctrl-sunxi.h" 34 35 static struct irq_chip sunxi_pinctrl_edge_irq_chip; 36 static struct irq_chip sunxi_pinctrl_level_irq_chip; 37 38 static struct sunxi_pinctrl_group * 39 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 40 { 41 int i; 42 43 for (i = 0; i < pctl->ngroups; i++) { 44 struct sunxi_pinctrl_group *grp = pctl->groups + i; 45 46 if (!strcmp(grp->name, group)) 47 return grp; 48 } 49 50 return NULL; 51 } 52 53 static struct sunxi_pinctrl_function * 54 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 55 const char *name) 56 { 57 struct sunxi_pinctrl_function *func = pctl->functions; 58 int i; 59 60 for (i = 0; i < pctl->nfunctions; i++) { 61 if (!func[i].name) 62 break; 63 64 if (!strcmp(func[i].name, name)) 65 return func + i; 66 } 67 68 return NULL; 69 } 70 71 static struct sunxi_desc_function * 72 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 73 const char *pin_name, 74 const char *func_name) 75 { 76 int i; 77 78 for (i = 0; i < pctl->desc->npins; i++) { 79 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 80 81 if (!strcmp(pin->pin.name, pin_name)) { 82 struct sunxi_desc_function *func = pin->functions; 83 84 while (func->name) { 85 if (!strcmp(func->name, func_name)) 86 return func; 87 88 func++; 89 } 90 } 91 } 92 93 return NULL; 94 } 95 96 static struct sunxi_desc_function * 97 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, 98 const u16 pin_num, 99 const char *func_name) 100 { 101 int i; 102 103 for (i = 0; i < pctl->desc->npins; i++) { 104 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 105 106 if (pin->pin.number == pin_num) { 107 struct sunxi_desc_function *func = pin->functions; 108 109 while (func->name) { 110 if (!strcmp(func->name, func_name)) 111 return func; 112 113 func++; 114 } 115 } 116 } 117 118 return NULL; 119 } 120 121 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 122 { 123 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 124 125 return pctl->ngroups; 126 } 127 128 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 129 unsigned group) 130 { 131 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 132 133 return pctl->groups[group].name; 134 } 135 136 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 137 unsigned group, 138 const unsigned **pins, 139 unsigned *num_pins) 140 { 141 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 142 143 *pins = (unsigned *)&pctl->groups[group].pin; 144 *num_pins = 1; 145 146 return 0; 147 } 148 149 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 150 struct device_node *node, 151 struct pinctrl_map **map, 152 unsigned *num_maps) 153 { 154 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 155 unsigned long *pinconfig; 156 struct property *prop; 157 const char *function; 158 const char *group; 159 int ret, nmaps, i = 0; 160 u32 val; 161 162 *map = NULL; 163 *num_maps = 0; 164 165 ret = of_property_read_string(node, "allwinner,function", &function); 166 if (ret) { 167 dev_err(pctl->dev, 168 "missing allwinner,function property in node %s\n", 169 node->name); 170 return -EINVAL; 171 } 172 173 nmaps = of_property_count_strings(node, "allwinner,pins") * 2; 174 if (nmaps < 0) { 175 dev_err(pctl->dev, 176 "missing allwinner,pins property in node %s\n", 177 node->name); 178 return -EINVAL; 179 } 180 181 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); 182 if (!*map) 183 return -ENOMEM; 184 185 of_property_for_each_string(node, "allwinner,pins", prop, group) { 186 struct sunxi_pinctrl_group *grp = 187 sunxi_pinctrl_find_group_by_name(pctl, group); 188 int j = 0, configlen = 0; 189 190 if (!grp) { 191 dev_err(pctl->dev, "unknown pin %s", group); 192 continue; 193 } 194 195 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 196 grp->name, 197 function)) { 198 dev_err(pctl->dev, "unsupported function %s on pin %s", 199 function, group); 200 continue; 201 } 202 203 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 204 (*map)[i].data.mux.group = group; 205 (*map)[i].data.mux.function = function; 206 207 i++; 208 209 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 210 (*map)[i].data.configs.group_or_pin = group; 211 212 if (of_find_property(node, "allwinner,drive", NULL)) 213 configlen++; 214 if (of_find_property(node, "allwinner,pull", NULL)) 215 configlen++; 216 217 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); 218 if (!pinconfig) { 219 kfree(*map); 220 return -ENOMEM; 221 } 222 223 if (!of_property_read_u32(node, "allwinner,drive", &val)) { 224 u16 strength = (val + 1) * 10; 225 pinconfig[j++] = 226 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 227 strength); 228 } 229 230 if (!of_property_read_u32(node, "allwinner,pull", &val)) { 231 enum pin_config_param pull = PIN_CONFIG_END; 232 if (val == 1) 233 pull = PIN_CONFIG_BIAS_PULL_UP; 234 else if (val == 2) 235 pull = PIN_CONFIG_BIAS_PULL_DOWN; 236 pinconfig[j++] = pinconf_to_config_packed(pull, 0); 237 } 238 239 (*map)[i].data.configs.configs = pinconfig; 240 (*map)[i].data.configs.num_configs = configlen; 241 242 i++; 243 } 244 245 *num_maps = nmaps; 246 247 return 0; 248 } 249 250 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 251 struct pinctrl_map *map, 252 unsigned num_maps) 253 { 254 int i; 255 256 for (i = 0; i < num_maps; i++) { 257 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) 258 kfree(map[i].data.configs.configs); 259 } 260 261 kfree(map); 262 } 263 264 static const struct pinctrl_ops sunxi_pctrl_ops = { 265 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 266 .dt_free_map = sunxi_pctrl_dt_free_map, 267 .get_groups_count = sunxi_pctrl_get_groups_count, 268 .get_group_name = sunxi_pctrl_get_group_name, 269 .get_group_pins = sunxi_pctrl_get_group_pins, 270 }; 271 272 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 273 unsigned group, 274 unsigned long *config) 275 { 276 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 277 278 *config = pctl->groups[group].config; 279 280 return 0; 281 } 282 283 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, 284 unsigned group, 285 unsigned long *configs, 286 unsigned num_configs) 287 { 288 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 289 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 290 unsigned long flags; 291 unsigned pin = g->pin - pctl->desc->pin_base; 292 u32 val, mask; 293 u16 strength; 294 u8 dlevel; 295 int i; 296 297 spin_lock_irqsave(&pctl->lock, flags); 298 299 for (i = 0; i < num_configs; i++) { 300 switch (pinconf_to_config_param(configs[i])) { 301 case PIN_CONFIG_DRIVE_STRENGTH: 302 strength = pinconf_to_config_argument(configs[i]); 303 if (strength > 40) { 304 spin_unlock_irqrestore(&pctl->lock, flags); 305 return -EINVAL; 306 } 307 /* 308 * We convert from mA to what the register expects: 309 * 0: 10mA 310 * 1: 20mA 311 * 2: 30mA 312 * 3: 40mA 313 */ 314 dlevel = strength / 10 - 1; 315 val = readl(pctl->membase + sunxi_dlevel_reg(pin)); 316 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin); 317 writel((val & ~mask) 318 | dlevel << sunxi_dlevel_offset(pin), 319 pctl->membase + sunxi_dlevel_reg(pin)); 320 break; 321 case PIN_CONFIG_BIAS_PULL_UP: 322 val = readl(pctl->membase + sunxi_pull_reg(pin)); 323 mask = PULL_PINS_MASK << sunxi_pull_offset(pin); 324 writel((val & ~mask) | 1 << sunxi_pull_offset(pin), 325 pctl->membase + sunxi_pull_reg(pin)); 326 break; 327 case PIN_CONFIG_BIAS_PULL_DOWN: 328 val = readl(pctl->membase + sunxi_pull_reg(pin)); 329 mask = PULL_PINS_MASK << sunxi_pull_offset(pin); 330 writel((val & ~mask) | 2 << sunxi_pull_offset(pin), 331 pctl->membase + sunxi_pull_reg(pin)); 332 break; 333 default: 334 break; 335 } 336 /* cache the config value */ 337 g->config = configs[i]; 338 } /* for each config */ 339 340 spin_unlock_irqrestore(&pctl->lock, flags); 341 342 return 0; 343 } 344 345 static const struct pinconf_ops sunxi_pconf_ops = { 346 .pin_config_group_get = sunxi_pconf_group_get, 347 .pin_config_group_set = sunxi_pconf_group_set, 348 }; 349 350 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 351 { 352 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 353 354 return pctl->nfunctions; 355 } 356 357 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 358 unsigned function) 359 { 360 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 361 362 return pctl->functions[function].name; 363 } 364 365 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 366 unsigned function, 367 const char * const **groups, 368 unsigned * const num_groups) 369 { 370 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 371 372 *groups = pctl->functions[function].groups; 373 *num_groups = pctl->functions[function].ngroups; 374 375 return 0; 376 } 377 378 static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 379 unsigned pin, 380 u8 config) 381 { 382 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 383 unsigned long flags; 384 u32 val, mask; 385 386 spin_lock_irqsave(&pctl->lock, flags); 387 388 pin -= pctl->desc->pin_base; 389 val = readl(pctl->membase + sunxi_mux_reg(pin)); 390 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 391 writel((val & ~mask) | config << sunxi_mux_offset(pin), 392 pctl->membase + sunxi_mux_reg(pin)); 393 394 spin_unlock_irqrestore(&pctl->lock, flags); 395 } 396 397 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, 398 unsigned function, 399 unsigned group) 400 { 401 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 402 struct sunxi_pinctrl_group *g = pctl->groups + group; 403 struct sunxi_pinctrl_function *func = pctl->functions + function; 404 struct sunxi_desc_function *desc = 405 sunxi_pinctrl_desc_find_function_by_name(pctl, 406 g->name, 407 func->name); 408 409 if (!desc) 410 return -EINVAL; 411 412 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 413 414 return 0; 415 } 416 417 static int 418 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 419 struct pinctrl_gpio_range *range, 420 unsigned offset, 421 bool input) 422 { 423 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 424 struct sunxi_desc_function *desc; 425 const char *func; 426 427 if (input) 428 func = "gpio_in"; 429 else 430 func = "gpio_out"; 431 432 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); 433 if (!desc) 434 return -EINVAL; 435 436 sunxi_pmx_set(pctldev, offset, desc->muxval); 437 438 return 0; 439 } 440 441 static const struct pinmux_ops sunxi_pmx_ops = { 442 .get_functions_count = sunxi_pmx_get_funcs_cnt, 443 .get_function_name = sunxi_pmx_get_func_name, 444 .get_function_groups = sunxi_pmx_get_func_groups, 445 .set_mux = sunxi_pmx_set_mux, 446 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 447 }; 448 449 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 450 unsigned offset) 451 { 452 return pinctrl_gpio_direction_input(chip->base + offset); 453 } 454 455 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 456 { 457 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 458 u32 reg = sunxi_data_reg(offset); 459 u8 index = sunxi_data_offset(offset); 460 u32 set_mux = pctl->desc->irq_read_needs_mux && 461 test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags); 462 u32 val; 463 464 if (set_mux) 465 sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT); 466 467 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; 468 469 if (set_mux) 470 sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ); 471 472 return !!val; 473 } 474 475 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 476 unsigned offset, int value) 477 { 478 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 479 u32 reg = sunxi_data_reg(offset); 480 u8 index = sunxi_data_offset(offset); 481 unsigned long flags; 482 u32 regval; 483 484 spin_lock_irqsave(&pctl->lock, flags); 485 486 regval = readl(pctl->membase + reg); 487 488 if (value) 489 regval |= BIT(index); 490 else 491 regval &= ~(BIT(index)); 492 493 writel(regval, pctl->membase + reg); 494 495 spin_unlock_irqrestore(&pctl->lock, flags); 496 } 497 498 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 499 unsigned offset, int value) 500 { 501 sunxi_pinctrl_gpio_set(chip, offset, value); 502 return pinctrl_gpio_direction_output(chip->base + offset); 503 } 504 505 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 506 const struct of_phandle_args *gpiospec, 507 u32 *flags) 508 { 509 int pin, base; 510 511 base = PINS_PER_BANK * gpiospec->args[0]; 512 pin = base + gpiospec->args[1]; 513 514 if (pin > gc->ngpio) 515 return -EINVAL; 516 517 if (flags) 518 *flags = gpiospec->args[2]; 519 520 return pin; 521 } 522 523 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 524 { 525 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 526 struct sunxi_desc_function *desc; 527 unsigned pinnum = pctl->desc->pin_base + offset; 528 unsigned irqnum; 529 530 if (offset >= chip->ngpio) 531 return -ENXIO; 532 533 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq"); 534 if (!desc) 535 return -EINVAL; 536 537 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum; 538 539 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n", 540 chip->label, offset + chip->base, irqnum); 541 542 return irq_find_mapping(pctl->domain, irqnum); 543 } 544 545 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) 546 { 547 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 548 struct sunxi_desc_function *func; 549 int ret; 550 551 func = sunxi_pinctrl_desc_find_function_by_pin(pctl, 552 pctl->irq_array[d->hwirq], "irq"); 553 if (!func) 554 return -EINVAL; 555 556 ret = gpiochip_lock_as_irq(pctl->chip, 557 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 558 if (ret) { 559 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 560 irqd_to_hwirq(d)); 561 return ret; 562 } 563 564 /* Change muxing to INT mode */ 565 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); 566 567 return 0; 568 } 569 570 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) 571 { 572 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 573 574 gpiochip_unlock_as_irq(pctl->chip, 575 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 576 } 577 578 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) 579 { 580 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 581 u32 reg = sunxi_irq_cfg_reg(d->hwirq); 582 u8 index = sunxi_irq_cfg_offset(d->hwirq); 583 unsigned long flags; 584 u32 regval; 585 u8 mode; 586 587 switch (type) { 588 case IRQ_TYPE_EDGE_RISING: 589 mode = IRQ_EDGE_RISING; 590 break; 591 case IRQ_TYPE_EDGE_FALLING: 592 mode = IRQ_EDGE_FALLING; 593 break; 594 case IRQ_TYPE_EDGE_BOTH: 595 mode = IRQ_EDGE_BOTH; 596 break; 597 case IRQ_TYPE_LEVEL_HIGH: 598 mode = IRQ_LEVEL_HIGH; 599 break; 600 case IRQ_TYPE_LEVEL_LOW: 601 mode = IRQ_LEVEL_LOW; 602 break; 603 default: 604 return -EINVAL; 605 } 606 607 spin_lock_irqsave(&pctl->lock, flags); 608 609 if (type & IRQ_TYPE_LEVEL_MASK) 610 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip, 611 handle_fasteoi_irq, NULL); 612 else 613 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip, 614 handle_edge_irq, NULL); 615 616 regval = readl(pctl->membase + reg); 617 regval &= ~(IRQ_CFG_IRQ_MASK << index); 618 writel(regval | (mode << index), pctl->membase + reg); 619 620 spin_unlock_irqrestore(&pctl->lock, flags); 621 622 return 0; 623 } 624 625 static void sunxi_pinctrl_irq_ack(struct irq_data *d) 626 { 627 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 628 u32 status_reg = sunxi_irq_status_reg(d->hwirq); 629 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 630 631 /* Clear the IRQ */ 632 writel(1 << status_idx, pctl->membase + status_reg); 633 } 634 635 static void sunxi_pinctrl_irq_mask(struct irq_data *d) 636 { 637 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 638 u32 reg = sunxi_irq_ctrl_reg(d->hwirq); 639 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 640 unsigned long flags; 641 u32 val; 642 643 spin_lock_irqsave(&pctl->lock, flags); 644 645 /* Mask the IRQ */ 646 val = readl(pctl->membase + reg); 647 writel(val & ~(1 << idx), pctl->membase + reg); 648 649 spin_unlock_irqrestore(&pctl->lock, flags); 650 } 651 652 static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 653 { 654 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 655 u32 reg = sunxi_irq_ctrl_reg(d->hwirq); 656 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 657 unsigned long flags; 658 u32 val; 659 660 spin_lock_irqsave(&pctl->lock, flags); 661 662 /* Unmask the IRQ */ 663 val = readl(pctl->membase + reg); 664 writel(val | (1 << idx), pctl->membase + reg); 665 666 spin_unlock_irqrestore(&pctl->lock, flags); 667 } 668 669 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) 670 { 671 sunxi_pinctrl_irq_ack(d); 672 sunxi_pinctrl_irq_unmask(d); 673 } 674 675 static struct irq_chip sunxi_pinctrl_edge_irq_chip = { 676 .name = "sunxi_pio_edge", 677 .irq_ack = sunxi_pinctrl_irq_ack, 678 .irq_mask = sunxi_pinctrl_irq_mask, 679 .irq_unmask = sunxi_pinctrl_irq_unmask, 680 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 681 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 682 .irq_set_type = sunxi_pinctrl_irq_set_type, 683 .flags = IRQCHIP_SKIP_SET_WAKE, 684 }; 685 686 static struct irq_chip sunxi_pinctrl_level_irq_chip = { 687 .name = "sunxi_pio_level", 688 .irq_eoi = sunxi_pinctrl_irq_ack, 689 .irq_mask = sunxi_pinctrl_irq_mask, 690 .irq_unmask = sunxi_pinctrl_irq_unmask, 691 /* Define irq_enable / disable to avoid spurious irqs for drivers 692 * using these to suppress irqs while they clear the irq source */ 693 .irq_enable = sunxi_pinctrl_irq_ack_unmask, 694 .irq_disable = sunxi_pinctrl_irq_mask, 695 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 696 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 697 .irq_set_type = sunxi_pinctrl_irq_set_type, 698 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED | 699 IRQCHIP_EOI_IF_HANDLED, 700 }; 701 702 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, 703 struct device_node *node, 704 const u32 *intspec, 705 unsigned int intsize, 706 unsigned long *out_hwirq, 707 unsigned int *out_type) 708 { 709 struct sunxi_pinctrl *pctl = d->host_data; 710 struct sunxi_desc_function *desc; 711 int pin, base; 712 713 if (intsize < 3) 714 return -EINVAL; 715 716 base = PINS_PER_BANK * intspec[0]; 717 pin = pctl->desc->pin_base + base + intspec[1]; 718 719 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); 720 if (!desc) 721 return -EINVAL; 722 723 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum; 724 *out_type = intspec[2]; 725 726 return 0; 727 } 728 729 static struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = { 730 .xlate = sunxi_pinctrl_irq_of_xlate, 731 }; 732 733 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) 734 { 735 unsigned int irq = irq_desc_get_irq(desc); 736 struct irq_chip *chip = irq_desc_get_chip(desc); 737 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc); 738 unsigned long bank, reg, val; 739 740 for (bank = 0; bank < pctl->desc->irq_banks; bank++) 741 if (irq == pctl->irq[bank]) 742 break; 743 744 if (bank == pctl->desc->irq_banks) 745 return; 746 747 reg = sunxi_irq_status_reg_from_bank(bank); 748 val = readl(pctl->membase + reg); 749 750 if (val) { 751 int irqoffset; 752 753 chained_irq_enter(chip, desc); 754 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) { 755 int pin_irq = irq_find_mapping(pctl->domain, 756 bank * IRQ_PER_BANK + irqoffset); 757 generic_handle_irq(pin_irq); 758 } 759 chained_irq_exit(chip, desc); 760 } 761 } 762 763 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 764 const char *name) 765 { 766 struct sunxi_pinctrl_function *func = pctl->functions; 767 768 while (func->name) { 769 /* function already there */ 770 if (strcmp(func->name, name) == 0) { 771 func->ngroups++; 772 return -EEXIST; 773 } 774 func++; 775 } 776 777 func->name = name; 778 func->ngroups = 1; 779 780 pctl->nfunctions++; 781 782 return 0; 783 } 784 785 static int sunxi_pinctrl_build_state(struct platform_device *pdev) 786 { 787 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 788 int i; 789 790 pctl->ngroups = pctl->desc->npins; 791 792 /* Allocate groups */ 793 pctl->groups = devm_kzalloc(&pdev->dev, 794 pctl->ngroups * sizeof(*pctl->groups), 795 GFP_KERNEL); 796 if (!pctl->groups) 797 return -ENOMEM; 798 799 for (i = 0; i < pctl->desc->npins; i++) { 800 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 801 struct sunxi_pinctrl_group *group = pctl->groups + i; 802 803 group->name = pin->pin.name; 804 group->pin = pin->pin.number; 805 } 806 807 /* 808 * We suppose that we won't have any more functions than pins, 809 * we'll reallocate that later anyway 810 */ 811 pctl->functions = devm_kzalloc(&pdev->dev, 812 pctl->desc->npins * sizeof(*pctl->functions), 813 GFP_KERNEL); 814 if (!pctl->functions) 815 return -ENOMEM; 816 817 /* Count functions and their associated groups */ 818 for (i = 0; i < pctl->desc->npins; i++) { 819 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 820 struct sunxi_desc_function *func = pin->functions; 821 822 while (func->name) { 823 /* Create interrupt mapping while we're at it */ 824 if (!strcmp(func->name, "irq")) { 825 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; 826 pctl->irq_array[irqnum] = pin->pin.number; 827 } 828 829 sunxi_pinctrl_add_function(pctl, func->name); 830 func++; 831 } 832 } 833 834 pctl->functions = krealloc(pctl->functions, 835 pctl->nfunctions * sizeof(*pctl->functions), 836 GFP_KERNEL); 837 838 for (i = 0; i < pctl->desc->npins; i++) { 839 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 840 struct sunxi_desc_function *func = pin->functions; 841 842 while (func->name) { 843 struct sunxi_pinctrl_function *func_item; 844 const char **func_grp; 845 846 func_item = sunxi_pinctrl_find_function_by_name(pctl, 847 func->name); 848 if (!func_item) 849 return -EINVAL; 850 851 if (!func_item->groups) { 852 func_item->groups = 853 devm_kzalloc(&pdev->dev, 854 func_item->ngroups * sizeof(*func_item->groups), 855 GFP_KERNEL); 856 if (!func_item->groups) 857 return -ENOMEM; 858 } 859 860 func_grp = func_item->groups; 861 while (*func_grp) 862 func_grp++; 863 864 *func_grp = pin->pin.name; 865 func++; 866 } 867 } 868 869 return 0; 870 } 871 872 int sunxi_pinctrl_init(struct platform_device *pdev, 873 const struct sunxi_pinctrl_desc *desc) 874 { 875 struct device_node *node = pdev->dev.of_node; 876 struct pinctrl_desc *pctrl_desc; 877 struct pinctrl_pin_desc *pins; 878 struct sunxi_pinctrl *pctl; 879 struct resource *res; 880 int i, ret, last_pin; 881 struct clk *clk; 882 883 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 884 if (!pctl) 885 return -ENOMEM; 886 platform_set_drvdata(pdev, pctl); 887 888 spin_lock_init(&pctl->lock); 889 890 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 891 pctl->membase = devm_ioremap_resource(&pdev->dev, res); 892 if (IS_ERR(pctl->membase)) 893 return PTR_ERR(pctl->membase); 894 895 pctl->dev = &pdev->dev; 896 pctl->desc = desc; 897 898 pctl->irq_array = devm_kcalloc(&pdev->dev, 899 IRQ_PER_BANK * pctl->desc->irq_banks, 900 sizeof(*pctl->irq_array), 901 GFP_KERNEL); 902 if (!pctl->irq_array) 903 return -ENOMEM; 904 905 ret = sunxi_pinctrl_build_state(pdev); 906 if (ret) { 907 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 908 return ret; 909 } 910 911 pins = devm_kzalloc(&pdev->dev, 912 pctl->desc->npins * sizeof(*pins), 913 GFP_KERNEL); 914 if (!pins) 915 return -ENOMEM; 916 917 for (i = 0; i < pctl->desc->npins; i++) 918 pins[i] = pctl->desc->pins[i].pin; 919 920 pctrl_desc = devm_kzalloc(&pdev->dev, 921 sizeof(*pctrl_desc), 922 GFP_KERNEL); 923 if (!pctrl_desc) 924 return -ENOMEM; 925 926 pctrl_desc->name = dev_name(&pdev->dev); 927 pctrl_desc->owner = THIS_MODULE; 928 pctrl_desc->pins = pins; 929 pctrl_desc->npins = pctl->desc->npins; 930 pctrl_desc->confops = &sunxi_pconf_ops; 931 pctrl_desc->pctlops = &sunxi_pctrl_ops; 932 pctrl_desc->pmxops = &sunxi_pmx_ops; 933 934 pctl->pctl_dev = pinctrl_register(pctrl_desc, 935 &pdev->dev, pctl); 936 if (IS_ERR(pctl->pctl_dev)) { 937 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 938 return PTR_ERR(pctl->pctl_dev); 939 } 940 941 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 942 if (!pctl->chip) { 943 ret = -ENOMEM; 944 goto pinctrl_error; 945 } 946 947 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 948 pctl->chip->owner = THIS_MODULE; 949 pctl->chip->request = gpiochip_generic_request, 950 pctl->chip->free = gpiochip_generic_free, 951 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input, 952 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output, 953 pctl->chip->get = sunxi_pinctrl_gpio_get, 954 pctl->chip->set = sunxi_pinctrl_gpio_set, 955 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate, 956 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq, 957 pctl->chip->of_gpio_n_cells = 3, 958 pctl->chip->can_sleep = false, 959 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - 960 pctl->desc->pin_base; 961 pctl->chip->label = dev_name(&pdev->dev); 962 pctl->chip->parent = &pdev->dev; 963 pctl->chip->base = pctl->desc->pin_base; 964 965 ret = gpiochip_add_data(pctl->chip, pctl); 966 if (ret) 967 goto pinctrl_error; 968 969 for (i = 0; i < pctl->desc->npins; i++) { 970 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 971 972 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 973 pin->pin.number - pctl->desc->pin_base, 974 pin->pin.number, 1); 975 if (ret) 976 goto gpiochip_error; 977 } 978 979 clk = devm_clk_get(&pdev->dev, NULL); 980 if (IS_ERR(clk)) { 981 ret = PTR_ERR(clk); 982 goto gpiochip_error; 983 } 984 985 ret = clk_prepare_enable(clk); 986 if (ret) 987 goto gpiochip_error; 988 989 pctl->irq = devm_kcalloc(&pdev->dev, 990 pctl->desc->irq_banks, 991 sizeof(*pctl->irq), 992 GFP_KERNEL); 993 if (!pctl->irq) { 994 ret = -ENOMEM; 995 goto clk_error; 996 } 997 998 for (i = 0; i < pctl->desc->irq_banks; i++) { 999 pctl->irq[i] = platform_get_irq(pdev, i); 1000 if (pctl->irq[i] < 0) { 1001 ret = pctl->irq[i]; 1002 goto clk_error; 1003 } 1004 } 1005 1006 pctl->domain = irq_domain_add_linear(node, 1007 pctl->desc->irq_banks * IRQ_PER_BANK, 1008 &sunxi_pinctrl_irq_domain_ops, 1009 pctl); 1010 if (!pctl->domain) { 1011 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 1012 ret = -ENOMEM; 1013 goto clk_error; 1014 } 1015 1016 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { 1017 int irqno = irq_create_mapping(pctl->domain, i); 1018 1019 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, 1020 handle_edge_irq); 1021 irq_set_chip_data(irqno, pctl); 1022 } 1023 1024 for (i = 0; i < pctl->desc->irq_banks; i++) { 1025 /* Mask and clear all IRQs before registering a handler */ 1026 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i)); 1027 writel(0xffffffff, 1028 pctl->membase + sunxi_irq_status_reg_from_bank(i)); 1029 1030 irq_set_chained_handler_and_data(pctl->irq[i], 1031 sunxi_pinctrl_irq_handler, 1032 pctl); 1033 } 1034 1035 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1036 1037 return 0; 1038 1039 clk_error: 1040 clk_disable_unprepare(clk); 1041 gpiochip_error: 1042 gpiochip_remove(pctl->chip); 1043 pinctrl_error: 1044 pinctrl_unregister(pctl->pctl_dev); 1045 return ret; 1046 } 1047