1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/io.h> 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/irqdomain.h> 18 #include <linux/irqchip/chained_irq.h> 19 #include <linux/export.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/pinctrl/machine.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinconf-generic.h> 28 #include <linux/pinctrl/pinmux.h> 29 #include <linux/platform_device.h> 30 #include <linux/slab.h> 31 32 #include <dt-bindings/pinctrl/sun4i-a10.h> 33 34 #include "../core.h" 35 #include "pinctrl-sunxi.h" 36 37 static struct irq_chip sunxi_pinctrl_edge_irq_chip; 38 static struct irq_chip sunxi_pinctrl_level_irq_chip; 39 40 static struct sunxi_pinctrl_group * 41 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 42 { 43 int i; 44 45 for (i = 0; i < pctl->ngroups; i++) { 46 struct sunxi_pinctrl_group *grp = pctl->groups + i; 47 48 if (!strcmp(grp->name, group)) 49 return grp; 50 } 51 52 return NULL; 53 } 54 55 static struct sunxi_pinctrl_function * 56 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 57 const char *name) 58 { 59 struct sunxi_pinctrl_function *func = pctl->functions; 60 int i; 61 62 for (i = 0; i < pctl->nfunctions; i++) { 63 if (!func[i].name) 64 break; 65 66 if (!strcmp(func[i].name, name)) 67 return func + i; 68 } 69 70 return NULL; 71 } 72 73 static struct sunxi_desc_function * 74 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 75 const char *pin_name, 76 const char *func_name) 77 { 78 int i; 79 80 for (i = 0; i < pctl->desc->npins; i++) { 81 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 82 83 if (!strcmp(pin->pin.name, pin_name)) { 84 struct sunxi_desc_function *func = pin->functions; 85 86 while (func->name) { 87 if (!strcmp(func->name, func_name) && 88 (!func->variant || 89 func->variant & pctl->variant)) 90 return func; 91 92 func++; 93 } 94 } 95 } 96 97 return NULL; 98 } 99 100 static struct sunxi_desc_function * 101 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, 102 const u16 pin_num, 103 const char *func_name) 104 { 105 int i; 106 107 for (i = 0; i < pctl->desc->npins; i++) { 108 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 109 110 if (pin->pin.number == pin_num) { 111 struct sunxi_desc_function *func = pin->functions; 112 113 while (func->name) { 114 if (!strcmp(func->name, func_name)) 115 return func; 116 117 func++; 118 } 119 } 120 } 121 122 return NULL; 123 } 124 125 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 126 { 127 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 128 129 return pctl->ngroups; 130 } 131 132 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 133 unsigned group) 134 { 135 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 136 137 return pctl->groups[group].name; 138 } 139 140 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 141 unsigned group, 142 const unsigned **pins, 143 unsigned *num_pins) 144 { 145 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 146 147 *pins = (unsigned *)&pctl->groups[group].pin; 148 *num_pins = 1; 149 150 return 0; 151 } 152 153 static bool sunxi_pctrl_has_bias_prop(struct device_node *node) 154 { 155 return of_find_property(node, "bias-pull-up", NULL) || 156 of_find_property(node, "bias-pull-down", NULL) || 157 of_find_property(node, "bias-disable", NULL) || 158 of_find_property(node, "allwinner,pull", NULL); 159 } 160 161 static bool sunxi_pctrl_has_drive_prop(struct device_node *node) 162 { 163 return of_find_property(node, "drive-strength", NULL) || 164 of_find_property(node, "allwinner,drive", NULL); 165 } 166 167 static int sunxi_pctrl_parse_bias_prop(struct device_node *node) 168 { 169 u32 val; 170 171 /* Try the new style binding */ 172 if (of_find_property(node, "bias-pull-up", NULL)) 173 return PIN_CONFIG_BIAS_PULL_UP; 174 175 if (of_find_property(node, "bias-pull-down", NULL)) 176 return PIN_CONFIG_BIAS_PULL_DOWN; 177 178 if (of_find_property(node, "bias-disable", NULL)) 179 return PIN_CONFIG_BIAS_DISABLE; 180 181 /* And fall back to the old binding */ 182 if (of_property_read_u32(node, "allwinner,pull", &val)) 183 return -EINVAL; 184 185 switch (val) { 186 case SUN4I_PINCTRL_NO_PULL: 187 return PIN_CONFIG_BIAS_DISABLE; 188 case SUN4I_PINCTRL_PULL_UP: 189 return PIN_CONFIG_BIAS_PULL_UP; 190 case SUN4I_PINCTRL_PULL_DOWN: 191 return PIN_CONFIG_BIAS_PULL_DOWN; 192 } 193 194 return -EINVAL; 195 } 196 197 static int sunxi_pctrl_parse_drive_prop(struct device_node *node) 198 { 199 u32 val; 200 201 /* Try the new style binding */ 202 if (!of_property_read_u32(node, "drive-strength", &val)) { 203 /* We can't go below 10mA ... */ 204 if (val < 10) 205 return -EINVAL; 206 207 /* ... and only up to 40 mA ... */ 208 if (val > 40) 209 val = 40; 210 211 /* by steps of 10 mA */ 212 return rounddown(val, 10); 213 } 214 215 /* And then fall back to the old binding */ 216 if (of_property_read_u32(node, "allwinner,drive", &val)) 217 return -EINVAL; 218 219 return (val + 1) * 10; 220 } 221 222 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node) 223 { 224 const char *function; 225 int ret; 226 227 /* Try the generic binding */ 228 ret = of_property_read_string(node, "function", &function); 229 if (!ret) 230 return function; 231 232 /* And fall back to our legacy one */ 233 ret = of_property_read_string(node, "allwinner,function", &function); 234 if (!ret) 235 return function; 236 237 return NULL; 238 } 239 240 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node, 241 int *npins) 242 { 243 int count; 244 245 /* Try the generic binding */ 246 count = of_property_count_strings(node, "pins"); 247 if (count > 0) { 248 *npins = count; 249 return "pins"; 250 } 251 252 /* And fall back to our legacy one */ 253 count = of_property_count_strings(node, "allwinner,pins"); 254 if (count > 0) { 255 *npins = count; 256 return "allwinner,pins"; 257 } 258 259 return NULL; 260 } 261 262 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node, 263 unsigned int *len) 264 { 265 unsigned long *pinconfig; 266 unsigned int configlen = 0, idx = 0; 267 int ret; 268 269 if (sunxi_pctrl_has_drive_prop(node)) 270 configlen++; 271 if (sunxi_pctrl_has_bias_prop(node)) 272 configlen++; 273 274 /* 275 * If we don't have any configuration, bail out 276 */ 277 if (!configlen) 278 return NULL; 279 280 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); 281 if (!pinconfig) 282 return ERR_PTR(-ENOMEM); 283 284 if (sunxi_pctrl_has_drive_prop(node)) { 285 int drive = sunxi_pctrl_parse_drive_prop(node); 286 if (drive < 0) { 287 ret = drive; 288 goto err_free; 289 } 290 291 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 292 drive); 293 } 294 295 if (sunxi_pctrl_has_bias_prop(node)) { 296 int pull = sunxi_pctrl_parse_bias_prop(node); 297 int arg = 0; 298 if (pull < 0) { 299 ret = pull; 300 goto err_free; 301 } 302 303 if (pull != PIN_CONFIG_BIAS_DISABLE) 304 arg = 1; /* hardware uses weak pull resistors */ 305 306 pinconfig[idx++] = pinconf_to_config_packed(pull, arg); 307 } 308 309 310 *len = configlen; 311 return pinconfig; 312 313 err_free: 314 kfree(pinconfig); 315 return ERR_PTR(ret); 316 } 317 318 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 319 struct device_node *node, 320 struct pinctrl_map **map, 321 unsigned *num_maps) 322 { 323 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 324 unsigned long *pinconfig; 325 struct property *prop; 326 const char *function, *pin_prop; 327 const char *group; 328 int ret, npins, nmaps, configlen = 0, i = 0; 329 330 *map = NULL; 331 *num_maps = 0; 332 333 function = sunxi_pctrl_parse_function_prop(node); 334 if (!function) { 335 dev_err(pctl->dev, "missing function property in node %s\n", 336 node->name); 337 return -EINVAL; 338 } 339 340 pin_prop = sunxi_pctrl_find_pins_prop(node, &npins); 341 if (!pin_prop) { 342 dev_err(pctl->dev, "missing pins property in node %s\n", 343 node->name); 344 return -EINVAL; 345 } 346 347 /* 348 * We have two maps for each pin: one for the function, one 349 * for the configuration (bias, strength, etc). 350 * 351 * We might be slightly overshooting, since we might not have 352 * any configuration. 353 */ 354 nmaps = npins * 2; 355 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); 356 if (!*map) 357 return -ENOMEM; 358 359 pinconfig = sunxi_pctrl_build_pin_config(node, &configlen); 360 if (IS_ERR(pinconfig)) { 361 ret = PTR_ERR(pinconfig); 362 goto err_free_map; 363 } 364 365 of_property_for_each_string(node, pin_prop, prop, group) { 366 struct sunxi_pinctrl_group *grp = 367 sunxi_pinctrl_find_group_by_name(pctl, group); 368 369 if (!grp) { 370 dev_err(pctl->dev, "unknown pin %s", group); 371 continue; 372 } 373 374 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 375 grp->name, 376 function)) { 377 dev_err(pctl->dev, "unsupported function %s on pin %s", 378 function, group); 379 continue; 380 } 381 382 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 383 (*map)[i].data.mux.group = group; 384 (*map)[i].data.mux.function = function; 385 386 i++; 387 388 if (pinconfig) { 389 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 390 (*map)[i].data.configs.group_or_pin = group; 391 (*map)[i].data.configs.configs = pinconfig; 392 (*map)[i].data.configs.num_configs = configlen; 393 i++; 394 } 395 } 396 397 *num_maps = i; 398 399 /* 400 * We know have the number of maps we need, we can resize our 401 * map array 402 */ 403 *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL); 404 if (!*map) 405 return -ENOMEM; 406 407 return 0; 408 409 err_free_map: 410 kfree(*map); 411 *map = NULL; 412 return ret; 413 } 414 415 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 416 struct pinctrl_map *map, 417 unsigned num_maps) 418 { 419 int i; 420 421 /* pin config is never in the first map */ 422 for (i = 1; i < num_maps; i++) { 423 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP) 424 continue; 425 426 /* 427 * All the maps share the same pin config, 428 * free only the first one we find. 429 */ 430 kfree(map[i].data.configs.configs); 431 break; 432 } 433 434 kfree(map); 435 } 436 437 static const struct pinctrl_ops sunxi_pctrl_ops = { 438 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 439 .dt_free_map = sunxi_pctrl_dt_free_map, 440 .get_groups_count = sunxi_pctrl_get_groups_count, 441 .get_group_name = sunxi_pctrl_get_group_name, 442 .get_group_pins = sunxi_pctrl_get_group_pins, 443 }; 444 445 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param, 446 u32 *offset, u32 *shift, u32 *mask) 447 { 448 switch (param) { 449 case PIN_CONFIG_DRIVE_STRENGTH: 450 *offset = sunxi_dlevel_reg(pin); 451 *shift = sunxi_dlevel_offset(pin); 452 *mask = DLEVEL_PINS_MASK; 453 break; 454 455 case PIN_CONFIG_BIAS_PULL_UP: 456 case PIN_CONFIG_BIAS_PULL_DOWN: 457 case PIN_CONFIG_BIAS_DISABLE: 458 *offset = sunxi_pull_reg(pin); 459 *shift = sunxi_pull_offset(pin); 460 *mask = PULL_PINS_MASK; 461 break; 462 463 default: 464 return -ENOTSUPP; 465 } 466 467 return 0; 468 } 469 470 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin, 471 unsigned long *config) 472 { 473 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 474 enum pin_config_param param = pinconf_to_config_param(*config); 475 u32 offset, shift, mask, val; 476 u16 arg; 477 int ret; 478 479 pin -= pctl->desc->pin_base; 480 481 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); 482 if (ret < 0) 483 return ret; 484 485 val = (readl(pctl->membase + offset) >> shift) & mask; 486 487 switch (pinconf_to_config_param(*config)) { 488 case PIN_CONFIG_DRIVE_STRENGTH: 489 arg = (val + 1) * 10; 490 break; 491 492 case PIN_CONFIG_BIAS_PULL_UP: 493 if (val != SUN4I_PINCTRL_PULL_UP) 494 return -EINVAL; 495 arg = 1; /* hardware is weak pull-up */ 496 break; 497 498 case PIN_CONFIG_BIAS_PULL_DOWN: 499 if (val != SUN4I_PINCTRL_PULL_DOWN) 500 return -EINVAL; 501 arg = 1; /* hardware is weak pull-down */ 502 break; 503 504 case PIN_CONFIG_BIAS_DISABLE: 505 if (val != SUN4I_PINCTRL_NO_PULL) 506 return -EINVAL; 507 arg = 0; 508 break; 509 510 default: 511 /* sunxi_pconf_reg should catch anything unsupported */ 512 WARN_ON(1); 513 return -ENOTSUPP; 514 } 515 516 *config = pinconf_to_config_packed(param, arg); 517 518 return 0; 519 } 520 521 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 522 unsigned group, 523 unsigned long *config) 524 { 525 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 526 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 527 528 /* We only support 1 pin per group. Chain it to the pin callback */ 529 return sunxi_pconf_get(pctldev, g->pin, config); 530 } 531 532 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, 533 unsigned group, 534 unsigned long *configs, 535 unsigned num_configs) 536 { 537 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 538 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 539 unsigned pin = g->pin - pctl->desc->pin_base; 540 int i; 541 542 for (i = 0; i < num_configs; i++) { 543 enum pin_config_param param; 544 unsigned long flags; 545 u32 offset, shift, mask, reg; 546 u32 arg, val; 547 int ret; 548 549 param = pinconf_to_config_param(configs[i]); 550 arg = pinconf_to_config_argument(configs[i]); 551 552 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); 553 if (ret < 0) 554 return ret; 555 556 switch (param) { 557 case PIN_CONFIG_DRIVE_STRENGTH: 558 if (arg < 10 || arg > 40) 559 return -EINVAL; 560 /* 561 * We convert from mA to what the register expects: 562 * 0: 10mA 563 * 1: 20mA 564 * 2: 30mA 565 * 3: 40mA 566 */ 567 val = arg / 10 - 1; 568 break; 569 case PIN_CONFIG_BIAS_DISABLE: 570 val = 0; 571 break; 572 case PIN_CONFIG_BIAS_PULL_UP: 573 if (arg == 0) 574 return -EINVAL; 575 val = 1; 576 break; 577 case PIN_CONFIG_BIAS_PULL_DOWN: 578 if (arg == 0) 579 return -EINVAL; 580 val = 2; 581 break; 582 default: 583 /* sunxi_pconf_reg should catch anything unsupported */ 584 WARN_ON(1); 585 return -ENOTSUPP; 586 } 587 588 raw_spin_lock_irqsave(&pctl->lock, flags); 589 reg = readl(pctl->membase + offset); 590 reg &= ~(mask << shift); 591 writel(reg | val << shift, pctl->membase + offset); 592 raw_spin_unlock_irqrestore(&pctl->lock, flags); 593 } /* for each config */ 594 595 return 0; 596 } 597 598 static const struct pinconf_ops sunxi_pconf_ops = { 599 .is_generic = true, 600 .pin_config_get = sunxi_pconf_get, 601 .pin_config_group_get = sunxi_pconf_group_get, 602 .pin_config_group_set = sunxi_pconf_group_set, 603 }; 604 605 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 606 { 607 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 608 609 return pctl->nfunctions; 610 } 611 612 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 613 unsigned function) 614 { 615 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 616 617 return pctl->functions[function].name; 618 } 619 620 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 621 unsigned function, 622 const char * const **groups, 623 unsigned * const num_groups) 624 { 625 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 626 627 *groups = pctl->functions[function].groups; 628 *num_groups = pctl->functions[function].ngroups; 629 630 return 0; 631 } 632 633 static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 634 unsigned pin, 635 u8 config) 636 { 637 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 638 unsigned long flags; 639 u32 val, mask; 640 641 raw_spin_lock_irqsave(&pctl->lock, flags); 642 643 pin -= pctl->desc->pin_base; 644 val = readl(pctl->membase + sunxi_mux_reg(pin)); 645 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 646 writel((val & ~mask) | config << sunxi_mux_offset(pin), 647 pctl->membase + sunxi_mux_reg(pin)); 648 649 raw_spin_unlock_irqrestore(&pctl->lock, flags); 650 } 651 652 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, 653 unsigned function, 654 unsigned group) 655 { 656 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 657 struct sunxi_pinctrl_group *g = pctl->groups + group; 658 struct sunxi_pinctrl_function *func = pctl->functions + function; 659 struct sunxi_desc_function *desc = 660 sunxi_pinctrl_desc_find_function_by_name(pctl, 661 g->name, 662 func->name); 663 664 if (!desc) 665 return -EINVAL; 666 667 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 668 669 return 0; 670 } 671 672 static int 673 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 674 struct pinctrl_gpio_range *range, 675 unsigned offset, 676 bool input) 677 { 678 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 679 struct sunxi_desc_function *desc; 680 const char *func; 681 682 if (input) 683 func = "gpio_in"; 684 else 685 func = "gpio_out"; 686 687 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); 688 if (!desc) 689 return -EINVAL; 690 691 sunxi_pmx_set(pctldev, offset, desc->muxval); 692 693 return 0; 694 } 695 696 static const struct pinmux_ops sunxi_pmx_ops = { 697 .get_functions_count = sunxi_pmx_get_funcs_cnt, 698 .get_function_name = sunxi_pmx_get_func_name, 699 .get_function_groups = sunxi_pmx_get_func_groups, 700 .set_mux = sunxi_pmx_set_mux, 701 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 702 .strict = true, 703 }; 704 705 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 706 unsigned offset) 707 { 708 return pinctrl_gpio_direction_input(chip->base + offset); 709 } 710 711 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 712 { 713 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 714 u32 reg = sunxi_data_reg(offset); 715 u8 index = sunxi_data_offset(offset); 716 bool set_mux = pctl->desc->irq_read_needs_mux && 717 gpiochip_line_is_irq(chip, offset); 718 u32 pin = offset + chip->base; 719 u32 val; 720 721 if (set_mux) 722 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); 723 724 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; 725 726 if (set_mux) 727 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); 728 729 return !!val; 730 } 731 732 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 733 unsigned offset, int value) 734 { 735 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 736 u32 reg = sunxi_data_reg(offset); 737 u8 index = sunxi_data_offset(offset); 738 unsigned long flags; 739 u32 regval; 740 741 raw_spin_lock_irqsave(&pctl->lock, flags); 742 743 regval = readl(pctl->membase + reg); 744 745 if (value) 746 regval |= BIT(index); 747 else 748 regval &= ~(BIT(index)); 749 750 writel(regval, pctl->membase + reg); 751 752 raw_spin_unlock_irqrestore(&pctl->lock, flags); 753 } 754 755 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 756 unsigned offset, int value) 757 { 758 sunxi_pinctrl_gpio_set(chip, offset, value); 759 return pinctrl_gpio_direction_output(chip->base + offset); 760 } 761 762 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 763 const struct of_phandle_args *gpiospec, 764 u32 *flags) 765 { 766 int pin, base; 767 768 base = PINS_PER_BANK * gpiospec->args[0]; 769 pin = base + gpiospec->args[1]; 770 771 if (pin > gc->ngpio) 772 return -EINVAL; 773 774 if (flags) 775 *flags = gpiospec->args[2]; 776 777 return pin; 778 } 779 780 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 781 { 782 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 783 struct sunxi_desc_function *desc; 784 unsigned pinnum = pctl->desc->pin_base + offset; 785 unsigned irqnum; 786 787 if (offset >= chip->ngpio) 788 return -ENXIO; 789 790 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq"); 791 if (!desc) 792 return -EINVAL; 793 794 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum; 795 796 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n", 797 chip->label, offset + chip->base, irqnum); 798 799 return irq_find_mapping(pctl->domain, irqnum); 800 } 801 802 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) 803 { 804 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 805 struct sunxi_desc_function *func; 806 int ret; 807 808 func = sunxi_pinctrl_desc_find_function_by_pin(pctl, 809 pctl->irq_array[d->hwirq], "irq"); 810 if (!func) 811 return -EINVAL; 812 813 ret = gpiochip_lock_as_irq(pctl->chip, 814 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 815 if (ret) { 816 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 817 irqd_to_hwirq(d)); 818 return ret; 819 } 820 821 /* Change muxing to INT mode */ 822 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); 823 824 return 0; 825 } 826 827 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) 828 { 829 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 830 831 gpiochip_unlock_as_irq(pctl->chip, 832 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 833 } 834 835 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) 836 { 837 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 838 u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq); 839 u8 index = sunxi_irq_cfg_offset(d->hwirq); 840 unsigned long flags; 841 u32 regval; 842 u8 mode; 843 844 switch (type) { 845 case IRQ_TYPE_EDGE_RISING: 846 mode = IRQ_EDGE_RISING; 847 break; 848 case IRQ_TYPE_EDGE_FALLING: 849 mode = IRQ_EDGE_FALLING; 850 break; 851 case IRQ_TYPE_EDGE_BOTH: 852 mode = IRQ_EDGE_BOTH; 853 break; 854 case IRQ_TYPE_LEVEL_HIGH: 855 mode = IRQ_LEVEL_HIGH; 856 break; 857 case IRQ_TYPE_LEVEL_LOW: 858 mode = IRQ_LEVEL_LOW; 859 break; 860 default: 861 return -EINVAL; 862 } 863 864 raw_spin_lock_irqsave(&pctl->lock, flags); 865 866 if (type & IRQ_TYPE_LEVEL_MASK) 867 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip, 868 handle_fasteoi_irq, NULL); 869 else 870 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip, 871 handle_edge_irq, NULL); 872 873 regval = readl(pctl->membase + reg); 874 regval &= ~(IRQ_CFG_IRQ_MASK << index); 875 writel(regval | (mode << index), pctl->membase + reg); 876 877 raw_spin_unlock_irqrestore(&pctl->lock, flags); 878 879 return 0; 880 } 881 882 static void sunxi_pinctrl_irq_ack(struct irq_data *d) 883 { 884 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 885 u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq); 886 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 887 888 /* Clear the IRQ */ 889 writel(1 << status_idx, pctl->membase + status_reg); 890 } 891 892 static void sunxi_pinctrl_irq_mask(struct irq_data *d) 893 { 894 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 895 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); 896 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 897 unsigned long flags; 898 u32 val; 899 900 raw_spin_lock_irqsave(&pctl->lock, flags); 901 902 /* Mask the IRQ */ 903 val = readl(pctl->membase + reg); 904 writel(val & ~(1 << idx), pctl->membase + reg); 905 906 raw_spin_unlock_irqrestore(&pctl->lock, flags); 907 } 908 909 static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 910 { 911 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 912 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); 913 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 914 unsigned long flags; 915 u32 val; 916 917 raw_spin_lock_irqsave(&pctl->lock, flags); 918 919 /* Unmask the IRQ */ 920 val = readl(pctl->membase + reg); 921 writel(val | (1 << idx), pctl->membase + reg); 922 923 raw_spin_unlock_irqrestore(&pctl->lock, flags); 924 } 925 926 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) 927 { 928 sunxi_pinctrl_irq_ack(d); 929 sunxi_pinctrl_irq_unmask(d); 930 } 931 932 static struct irq_chip sunxi_pinctrl_edge_irq_chip = { 933 .name = "sunxi_pio_edge", 934 .irq_ack = sunxi_pinctrl_irq_ack, 935 .irq_mask = sunxi_pinctrl_irq_mask, 936 .irq_unmask = sunxi_pinctrl_irq_unmask, 937 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 938 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 939 .irq_set_type = sunxi_pinctrl_irq_set_type, 940 .flags = IRQCHIP_SKIP_SET_WAKE, 941 }; 942 943 static struct irq_chip sunxi_pinctrl_level_irq_chip = { 944 .name = "sunxi_pio_level", 945 .irq_eoi = sunxi_pinctrl_irq_ack, 946 .irq_mask = sunxi_pinctrl_irq_mask, 947 .irq_unmask = sunxi_pinctrl_irq_unmask, 948 /* Define irq_enable / disable to avoid spurious irqs for drivers 949 * using these to suppress irqs while they clear the irq source */ 950 .irq_enable = sunxi_pinctrl_irq_ack_unmask, 951 .irq_disable = sunxi_pinctrl_irq_mask, 952 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 953 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 954 .irq_set_type = sunxi_pinctrl_irq_set_type, 955 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED | 956 IRQCHIP_EOI_IF_HANDLED, 957 }; 958 959 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, 960 struct device_node *node, 961 const u32 *intspec, 962 unsigned int intsize, 963 unsigned long *out_hwirq, 964 unsigned int *out_type) 965 { 966 struct sunxi_pinctrl *pctl = d->host_data; 967 struct sunxi_desc_function *desc; 968 int pin, base; 969 970 if (intsize < 3) 971 return -EINVAL; 972 973 base = PINS_PER_BANK * intspec[0]; 974 pin = pctl->desc->pin_base + base + intspec[1]; 975 976 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); 977 if (!desc) 978 return -EINVAL; 979 980 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum; 981 *out_type = intspec[2]; 982 983 return 0; 984 } 985 986 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = { 987 .xlate = sunxi_pinctrl_irq_of_xlate, 988 }; 989 990 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) 991 { 992 unsigned int irq = irq_desc_get_irq(desc); 993 struct irq_chip *chip = irq_desc_get_chip(desc); 994 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc); 995 unsigned long bank, reg, val; 996 997 for (bank = 0; bank < pctl->desc->irq_banks; bank++) 998 if (irq == pctl->irq[bank]) 999 break; 1000 1001 if (bank == pctl->desc->irq_banks) 1002 return; 1003 1004 reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); 1005 val = readl(pctl->membase + reg); 1006 1007 if (val) { 1008 int irqoffset; 1009 1010 chained_irq_enter(chip, desc); 1011 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) { 1012 int pin_irq = irq_find_mapping(pctl->domain, 1013 bank * IRQ_PER_BANK + irqoffset); 1014 generic_handle_irq(pin_irq); 1015 } 1016 chained_irq_exit(chip, desc); 1017 } 1018 } 1019 1020 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 1021 const char *name) 1022 { 1023 struct sunxi_pinctrl_function *func = pctl->functions; 1024 1025 while (func->name) { 1026 /* function already there */ 1027 if (strcmp(func->name, name) == 0) { 1028 func->ngroups++; 1029 return -EEXIST; 1030 } 1031 func++; 1032 } 1033 1034 func->name = name; 1035 func->ngroups = 1; 1036 1037 pctl->nfunctions++; 1038 1039 return 0; 1040 } 1041 1042 static int sunxi_pinctrl_build_state(struct platform_device *pdev) 1043 { 1044 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 1045 int i; 1046 1047 /* 1048 * Allocate groups 1049 * 1050 * We assume that the number of groups is the number of pins 1051 * given in the data array. 1052 1053 * This will not always be true, since some pins might not be 1054 * available in the current variant, but fortunately for us, 1055 * this means that the number of pins is the maximum group 1056 * number we will ever see. 1057 */ 1058 pctl->groups = devm_kzalloc(&pdev->dev, 1059 pctl->desc->npins * sizeof(*pctl->groups), 1060 GFP_KERNEL); 1061 if (!pctl->groups) 1062 return -ENOMEM; 1063 1064 for (i = 0; i < pctl->desc->npins; i++) { 1065 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1066 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups; 1067 1068 if (pin->variant && !(pctl->variant & pin->variant)) 1069 continue; 1070 1071 group->name = pin->pin.name; 1072 group->pin = pin->pin.number; 1073 1074 /* And now we count the actual number of pins / groups */ 1075 pctl->ngroups++; 1076 } 1077 1078 /* 1079 * We suppose that we won't have any more functions than pins, 1080 * we'll reallocate that later anyway 1081 */ 1082 pctl->functions = devm_kzalloc(&pdev->dev, 1083 pctl->ngroups * sizeof(*pctl->functions), 1084 GFP_KERNEL); 1085 if (!pctl->functions) 1086 return -ENOMEM; 1087 1088 /* Count functions and their associated groups */ 1089 for (i = 0; i < pctl->desc->npins; i++) { 1090 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1091 struct sunxi_desc_function *func; 1092 1093 if (pin->variant && !(pctl->variant & pin->variant)) 1094 continue; 1095 1096 for (func = pin->functions; func->name; func++) { 1097 if (func->variant && !(pctl->variant & func->variant)) 1098 continue; 1099 1100 /* Create interrupt mapping while we're at it */ 1101 if (!strcmp(func->name, "irq")) { 1102 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; 1103 pctl->irq_array[irqnum] = pin->pin.number; 1104 } 1105 1106 sunxi_pinctrl_add_function(pctl, func->name); 1107 } 1108 } 1109 1110 /* And now allocated and fill the array for real */ 1111 pctl->functions = krealloc(pctl->functions, 1112 pctl->nfunctions * sizeof(*pctl->functions), 1113 GFP_KERNEL); 1114 if (!pctl->functions) { 1115 kfree(pctl->functions); 1116 return -ENOMEM; 1117 } 1118 1119 for (i = 0; i < pctl->desc->npins; i++) { 1120 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1121 struct sunxi_desc_function *func; 1122 1123 if (pin->variant && !(pctl->variant & pin->variant)) 1124 continue; 1125 1126 for (func = pin->functions; func->name; func++) { 1127 struct sunxi_pinctrl_function *func_item; 1128 const char **func_grp; 1129 1130 if (func->variant && !(pctl->variant & func->variant)) 1131 continue; 1132 1133 func_item = sunxi_pinctrl_find_function_by_name(pctl, 1134 func->name); 1135 if (!func_item) 1136 return -EINVAL; 1137 1138 if (!func_item->groups) { 1139 func_item->groups = 1140 devm_kzalloc(&pdev->dev, 1141 func_item->ngroups * sizeof(*func_item->groups), 1142 GFP_KERNEL); 1143 if (!func_item->groups) 1144 return -ENOMEM; 1145 } 1146 1147 func_grp = func_item->groups; 1148 while (*func_grp) 1149 func_grp++; 1150 1151 *func_grp = pin->pin.name; 1152 } 1153 } 1154 1155 return 0; 1156 } 1157 1158 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff) 1159 { 1160 unsigned long clock = clk_get_rate(clk); 1161 unsigned int best_diff, best_div; 1162 int i; 1163 1164 best_diff = abs(freq - clock); 1165 best_div = 0; 1166 1167 for (i = 1; i < 8; i++) { 1168 int cur_diff = abs(freq - (clock >> i)); 1169 1170 if (cur_diff < best_diff) { 1171 best_diff = cur_diff; 1172 best_div = i; 1173 } 1174 } 1175 1176 *diff = best_diff; 1177 return best_div; 1178 } 1179 1180 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, 1181 struct device_node *node) 1182 { 1183 unsigned int hosc_diff, losc_diff; 1184 unsigned int hosc_div, losc_div; 1185 struct clk *hosc, *losc; 1186 u8 div, src; 1187 int i, ret; 1188 1189 /* Deal with old DTs that didn't have the oscillators */ 1190 if (of_clk_get_parent_count(node) != 3) 1191 return 0; 1192 1193 /* If we don't have any setup, bail out */ 1194 if (!of_find_property(node, "input-debounce", NULL)) 1195 return 0; 1196 1197 losc = devm_clk_get(pctl->dev, "losc"); 1198 if (IS_ERR(losc)) 1199 return PTR_ERR(losc); 1200 1201 hosc = devm_clk_get(pctl->dev, "hosc"); 1202 if (IS_ERR(hosc)) 1203 return PTR_ERR(hosc); 1204 1205 for (i = 0; i < pctl->desc->irq_banks; i++) { 1206 unsigned long debounce_freq; 1207 u32 debounce; 1208 1209 ret = of_property_read_u32_index(node, "input-debounce", 1210 i, &debounce); 1211 if (ret) 1212 return ret; 1213 1214 if (!debounce) 1215 continue; 1216 1217 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce); 1218 losc_div = sunxi_pinctrl_get_debounce_div(losc, 1219 debounce_freq, 1220 &losc_diff); 1221 1222 hosc_div = sunxi_pinctrl_get_debounce_div(hosc, 1223 debounce_freq, 1224 &hosc_diff); 1225 1226 if (hosc_diff < losc_diff) { 1227 div = hosc_div; 1228 src = 1; 1229 } else { 1230 div = losc_div; 1231 src = 0; 1232 } 1233 1234 writel(src | div << 4, 1235 pctl->membase + 1236 sunxi_irq_debounce_reg_from_bank(pctl->desc, i)); 1237 } 1238 1239 return 0; 1240 } 1241 1242 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, 1243 const struct sunxi_pinctrl_desc *desc, 1244 unsigned long variant) 1245 { 1246 struct device_node *node = pdev->dev.of_node; 1247 struct pinctrl_desc *pctrl_desc; 1248 struct pinctrl_pin_desc *pins; 1249 struct sunxi_pinctrl *pctl; 1250 struct pinmux_ops *pmxops; 1251 struct resource *res; 1252 int i, ret, last_pin, pin_idx; 1253 struct clk *clk; 1254 1255 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1256 if (!pctl) 1257 return -ENOMEM; 1258 platform_set_drvdata(pdev, pctl); 1259 1260 raw_spin_lock_init(&pctl->lock); 1261 1262 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1263 pctl->membase = devm_ioremap_resource(&pdev->dev, res); 1264 if (IS_ERR(pctl->membase)) 1265 return PTR_ERR(pctl->membase); 1266 1267 pctl->dev = &pdev->dev; 1268 pctl->desc = desc; 1269 pctl->variant = variant; 1270 1271 pctl->irq_array = devm_kcalloc(&pdev->dev, 1272 IRQ_PER_BANK * pctl->desc->irq_banks, 1273 sizeof(*pctl->irq_array), 1274 GFP_KERNEL); 1275 if (!pctl->irq_array) 1276 return -ENOMEM; 1277 1278 ret = sunxi_pinctrl_build_state(pdev); 1279 if (ret) { 1280 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 1281 return ret; 1282 } 1283 1284 pins = devm_kzalloc(&pdev->dev, 1285 pctl->desc->npins * sizeof(*pins), 1286 GFP_KERNEL); 1287 if (!pins) 1288 return -ENOMEM; 1289 1290 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) { 1291 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1292 1293 if (pin->variant && !(pctl->variant & pin->variant)) 1294 continue; 1295 1296 pins[pin_idx++] = pin->pin; 1297 } 1298 1299 pctrl_desc = devm_kzalloc(&pdev->dev, 1300 sizeof(*pctrl_desc), 1301 GFP_KERNEL); 1302 if (!pctrl_desc) 1303 return -ENOMEM; 1304 1305 pctrl_desc->name = dev_name(&pdev->dev); 1306 pctrl_desc->owner = THIS_MODULE; 1307 pctrl_desc->pins = pins; 1308 pctrl_desc->npins = pctl->ngroups; 1309 pctrl_desc->confops = &sunxi_pconf_ops; 1310 pctrl_desc->pctlops = &sunxi_pctrl_ops; 1311 1312 pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops), 1313 GFP_KERNEL); 1314 if (!pmxops) 1315 return -ENOMEM; 1316 1317 if (desc->disable_strict_mode) 1318 pmxops->strict = false; 1319 1320 pctrl_desc->pmxops = pmxops; 1321 1322 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); 1323 if (IS_ERR(pctl->pctl_dev)) { 1324 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1325 return PTR_ERR(pctl->pctl_dev); 1326 } 1327 1328 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1329 if (!pctl->chip) 1330 return -ENOMEM; 1331 1332 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 1333 pctl->chip->owner = THIS_MODULE; 1334 pctl->chip->request = gpiochip_generic_request, 1335 pctl->chip->free = gpiochip_generic_free, 1336 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input, 1337 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output, 1338 pctl->chip->get = sunxi_pinctrl_gpio_get, 1339 pctl->chip->set = sunxi_pinctrl_gpio_set, 1340 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate, 1341 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq, 1342 pctl->chip->of_gpio_n_cells = 3, 1343 pctl->chip->can_sleep = false, 1344 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - 1345 pctl->desc->pin_base; 1346 pctl->chip->label = dev_name(&pdev->dev); 1347 pctl->chip->parent = &pdev->dev; 1348 pctl->chip->base = pctl->desc->pin_base; 1349 1350 ret = gpiochip_add_data(pctl->chip, pctl); 1351 if (ret) 1352 return ret; 1353 1354 for (i = 0; i < pctl->desc->npins; i++) { 1355 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1356 1357 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1358 pin->pin.number - pctl->desc->pin_base, 1359 pin->pin.number, 1); 1360 if (ret) 1361 goto gpiochip_error; 1362 } 1363 1364 ret = of_count_phandle_with_args(node, "clocks", "#clock-cells"); 1365 clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb"); 1366 if (IS_ERR(clk)) { 1367 ret = PTR_ERR(clk); 1368 goto gpiochip_error; 1369 } 1370 1371 ret = clk_prepare_enable(clk); 1372 if (ret) 1373 goto gpiochip_error; 1374 1375 pctl->irq = devm_kcalloc(&pdev->dev, 1376 pctl->desc->irq_banks, 1377 sizeof(*pctl->irq), 1378 GFP_KERNEL); 1379 if (!pctl->irq) { 1380 ret = -ENOMEM; 1381 goto clk_error; 1382 } 1383 1384 for (i = 0; i < pctl->desc->irq_banks; i++) { 1385 pctl->irq[i] = platform_get_irq(pdev, i); 1386 if (pctl->irq[i] < 0) { 1387 ret = pctl->irq[i]; 1388 goto clk_error; 1389 } 1390 } 1391 1392 pctl->domain = irq_domain_add_linear(node, 1393 pctl->desc->irq_banks * IRQ_PER_BANK, 1394 &sunxi_pinctrl_irq_domain_ops, 1395 pctl); 1396 if (!pctl->domain) { 1397 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 1398 ret = -ENOMEM; 1399 goto clk_error; 1400 } 1401 1402 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { 1403 int irqno = irq_create_mapping(pctl->domain, i); 1404 1405 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, 1406 handle_edge_irq); 1407 irq_set_chip_data(irqno, pctl); 1408 } 1409 1410 for (i = 0; i < pctl->desc->irq_banks; i++) { 1411 /* Mask and clear all IRQs before registering a handler */ 1412 writel(0, pctl->membase + 1413 sunxi_irq_ctrl_reg_from_bank(pctl->desc, i)); 1414 writel(0xffffffff, 1415 pctl->membase + 1416 sunxi_irq_status_reg_from_bank(pctl->desc, i)); 1417 1418 irq_set_chained_handler_and_data(pctl->irq[i], 1419 sunxi_pinctrl_irq_handler, 1420 pctl); 1421 } 1422 1423 sunxi_pinctrl_setup_debounce(pctl, node); 1424 1425 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1426 1427 return 0; 1428 1429 clk_error: 1430 clk_disable_unprepare(clk); 1431 gpiochip_error: 1432 gpiochip_remove(pctl->chip); 1433 return ret; 1434 } 1435