1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/io.h> 14 #include <linux/clk.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/interrupt.h> 17 #include <linux/irqdomain.h> 18 #include <linux/irqchip/chained_irq.h> 19 #include <linux/export.h> 20 #include <linux/of.h> 21 #include <linux/of_clk.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/of_irq.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/pinctrl/machine.h> 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinconf-generic.h> 29 #include <linux/pinctrl/pinmux.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/platform_device.h> 32 #include <linux/slab.h> 33 34 #include <dt-bindings/pinctrl/sun4i-a10.h> 35 36 #include "../core.h" 37 #include "pinctrl-sunxi.h" 38 39 /* 40 * These lock classes tell lockdep that GPIO IRQs are in a different 41 * category than their parents, so it won't report false recursion. 42 */ 43 static struct lock_class_key sunxi_pinctrl_irq_lock_class; 44 static struct lock_class_key sunxi_pinctrl_irq_request_class; 45 46 static struct irq_chip sunxi_pinctrl_edge_irq_chip; 47 static struct irq_chip sunxi_pinctrl_level_irq_chip; 48 49 static struct sunxi_pinctrl_group * 50 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 51 { 52 int i; 53 54 for (i = 0; i < pctl->ngroups; i++) { 55 struct sunxi_pinctrl_group *grp = pctl->groups + i; 56 57 if (!strcmp(grp->name, group)) 58 return grp; 59 } 60 61 return NULL; 62 } 63 64 static struct sunxi_pinctrl_function * 65 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 66 const char *name) 67 { 68 struct sunxi_pinctrl_function *func = pctl->functions; 69 int i; 70 71 for (i = 0; i < pctl->nfunctions; i++) { 72 if (!func[i].name) 73 break; 74 75 if (!strcmp(func[i].name, name)) 76 return func + i; 77 } 78 79 return NULL; 80 } 81 82 static struct sunxi_desc_function * 83 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 84 const char *pin_name, 85 const char *func_name) 86 { 87 int i; 88 89 for (i = 0; i < pctl->desc->npins; i++) { 90 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 91 92 if (!strcmp(pin->pin.name, pin_name)) { 93 struct sunxi_desc_function *func = pin->functions; 94 95 while (func->name) { 96 if (!strcmp(func->name, func_name) && 97 (!func->variant || 98 func->variant & pctl->variant)) 99 return func; 100 101 func++; 102 } 103 } 104 } 105 106 return NULL; 107 } 108 109 static struct sunxi_desc_function * 110 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, 111 const u16 pin_num, 112 const char *func_name) 113 { 114 int i; 115 116 for (i = 0; i < pctl->desc->npins; i++) { 117 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 118 119 if (pin->pin.number == pin_num) { 120 struct sunxi_desc_function *func = pin->functions; 121 122 while (func->name) { 123 if (!strcmp(func->name, func_name)) 124 return func; 125 126 func++; 127 } 128 } 129 } 130 131 return NULL; 132 } 133 134 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 135 { 136 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 137 138 return pctl->ngroups; 139 } 140 141 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 142 unsigned group) 143 { 144 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 145 146 return pctl->groups[group].name; 147 } 148 149 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 150 unsigned group, 151 const unsigned **pins, 152 unsigned *num_pins) 153 { 154 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 155 156 *pins = (unsigned *)&pctl->groups[group].pin; 157 *num_pins = 1; 158 159 return 0; 160 } 161 162 static bool sunxi_pctrl_has_bias_prop(struct device_node *node) 163 { 164 return of_find_property(node, "bias-pull-up", NULL) || 165 of_find_property(node, "bias-pull-down", NULL) || 166 of_find_property(node, "bias-disable", NULL) || 167 of_find_property(node, "allwinner,pull", NULL); 168 } 169 170 static bool sunxi_pctrl_has_drive_prop(struct device_node *node) 171 { 172 return of_find_property(node, "drive-strength", NULL) || 173 of_find_property(node, "allwinner,drive", NULL); 174 } 175 176 static int sunxi_pctrl_parse_bias_prop(struct device_node *node) 177 { 178 u32 val; 179 180 /* Try the new style binding */ 181 if (of_find_property(node, "bias-pull-up", NULL)) 182 return PIN_CONFIG_BIAS_PULL_UP; 183 184 if (of_find_property(node, "bias-pull-down", NULL)) 185 return PIN_CONFIG_BIAS_PULL_DOWN; 186 187 if (of_find_property(node, "bias-disable", NULL)) 188 return PIN_CONFIG_BIAS_DISABLE; 189 190 /* And fall back to the old binding */ 191 if (of_property_read_u32(node, "allwinner,pull", &val)) 192 return -EINVAL; 193 194 switch (val) { 195 case SUN4I_PINCTRL_NO_PULL: 196 return PIN_CONFIG_BIAS_DISABLE; 197 case SUN4I_PINCTRL_PULL_UP: 198 return PIN_CONFIG_BIAS_PULL_UP; 199 case SUN4I_PINCTRL_PULL_DOWN: 200 return PIN_CONFIG_BIAS_PULL_DOWN; 201 } 202 203 return -EINVAL; 204 } 205 206 static int sunxi_pctrl_parse_drive_prop(struct device_node *node) 207 { 208 u32 val; 209 210 /* Try the new style binding */ 211 if (!of_property_read_u32(node, "drive-strength", &val)) { 212 /* We can't go below 10mA ... */ 213 if (val < 10) 214 return -EINVAL; 215 216 /* ... and only up to 40 mA ... */ 217 if (val > 40) 218 val = 40; 219 220 /* by steps of 10 mA */ 221 return rounddown(val, 10); 222 } 223 224 /* And then fall back to the old binding */ 225 if (of_property_read_u32(node, "allwinner,drive", &val)) 226 return -EINVAL; 227 228 return (val + 1) * 10; 229 } 230 231 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node) 232 { 233 const char *function; 234 int ret; 235 236 /* Try the generic binding */ 237 ret = of_property_read_string(node, "function", &function); 238 if (!ret) 239 return function; 240 241 /* And fall back to our legacy one */ 242 ret = of_property_read_string(node, "allwinner,function", &function); 243 if (!ret) 244 return function; 245 246 return NULL; 247 } 248 249 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node, 250 int *npins) 251 { 252 int count; 253 254 /* Try the generic binding */ 255 count = of_property_count_strings(node, "pins"); 256 if (count > 0) { 257 *npins = count; 258 return "pins"; 259 } 260 261 /* And fall back to our legacy one */ 262 count = of_property_count_strings(node, "allwinner,pins"); 263 if (count > 0) { 264 *npins = count; 265 return "allwinner,pins"; 266 } 267 268 return NULL; 269 } 270 271 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node, 272 unsigned int *len) 273 { 274 unsigned long *pinconfig; 275 unsigned int configlen = 0, idx = 0; 276 int ret; 277 278 if (sunxi_pctrl_has_drive_prop(node)) 279 configlen++; 280 if (sunxi_pctrl_has_bias_prop(node)) 281 configlen++; 282 283 /* 284 * If we don't have any configuration, bail out 285 */ 286 if (!configlen) 287 return NULL; 288 289 pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL); 290 if (!pinconfig) 291 return ERR_PTR(-ENOMEM); 292 293 if (sunxi_pctrl_has_drive_prop(node)) { 294 int drive = sunxi_pctrl_parse_drive_prop(node); 295 if (drive < 0) { 296 ret = drive; 297 goto err_free; 298 } 299 300 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 301 drive); 302 } 303 304 if (sunxi_pctrl_has_bias_prop(node)) { 305 int pull = sunxi_pctrl_parse_bias_prop(node); 306 int arg = 0; 307 if (pull < 0) { 308 ret = pull; 309 goto err_free; 310 } 311 312 if (pull != PIN_CONFIG_BIAS_DISABLE) 313 arg = 1; /* hardware uses weak pull resistors */ 314 315 pinconfig[idx++] = pinconf_to_config_packed(pull, arg); 316 } 317 318 319 *len = configlen; 320 return pinconfig; 321 322 err_free: 323 kfree(pinconfig); 324 return ERR_PTR(ret); 325 } 326 327 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 328 struct device_node *node, 329 struct pinctrl_map **map, 330 unsigned *num_maps) 331 { 332 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 333 unsigned long *pinconfig; 334 struct property *prop; 335 const char *function, *pin_prop; 336 const char *group; 337 int ret, npins, nmaps, configlen = 0, i = 0; 338 339 *map = NULL; 340 *num_maps = 0; 341 342 function = sunxi_pctrl_parse_function_prop(node); 343 if (!function) { 344 dev_err(pctl->dev, "missing function property in node %pOFn\n", 345 node); 346 return -EINVAL; 347 } 348 349 pin_prop = sunxi_pctrl_find_pins_prop(node, &npins); 350 if (!pin_prop) { 351 dev_err(pctl->dev, "missing pins property in node %pOFn\n", 352 node); 353 return -EINVAL; 354 } 355 356 /* 357 * We have two maps for each pin: one for the function, one 358 * for the configuration (bias, strength, etc). 359 * 360 * We might be slightly overshooting, since we might not have 361 * any configuration. 362 */ 363 nmaps = npins * 2; 364 *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL); 365 if (!*map) 366 return -ENOMEM; 367 368 pinconfig = sunxi_pctrl_build_pin_config(node, &configlen); 369 if (IS_ERR(pinconfig)) { 370 ret = PTR_ERR(pinconfig); 371 goto err_free_map; 372 } 373 374 of_property_for_each_string(node, pin_prop, prop, group) { 375 struct sunxi_pinctrl_group *grp = 376 sunxi_pinctrl_find_group_by_name(pctl, group); 377 378 if (!grp) { 379 dev_err(pctl->dev, "unknown pin %s", group); 380 continue; 381 } 382 383 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 384 grp->name, 385 function)) { 386 dev_err(pctl->dev, "unsupported function %s on pin %s", 387 function, group); 388 continue; 389 } 390 391 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 392 (*map)[i].data.mux.group = group; 393 (*map)[i].data.mux.function = function; 394 395 i++; 396 397 if (pinconfig) { 398 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 399 (*map)[i].data.configs.group_or_pin = group; 400 (*map)[i].data.configs.configs = pinconfig; 401 (*map)[i].data.configs.num_configs = configlen; 402 i++; 403 } 404 } 405 406 *num_maps = i; 407 408 /* 409 * We know have the number of maps we need, we can resize our 410 * map array 411 */ 412 *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL); 413 if (!*map) 414 return -ENOMEM; 415 416 return 0; 417 418 err_free_map: 419 kfree(*map); 420 *map = NULL; 421 return ret; 422 } 423 424 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 425 struct pinctrl_map *map, 426 unsigned num_maps) 427 { 428 int i; 429 430 /* pin config is never in the first map */ 431 for (i = 1; i < num_maps; i++) { 432 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP) 433 continue; 434 435 /* 436 * All the maps share the same pin config, 437 * free only the first one we find. 438 */ 439 kfree(map[i].data.configs.configs); 440 break; 441 } 442 443 kfree(map); 444 } 445 446 static const struct pinctrl_ops sunxi_pctrl_ops = { 447 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 448 .dt_free_map = sunxi_pctrl_dt_free_map, 449 .get_groups_count = sunxi_pctrl_get_groups_count, 450 .get_group_name = sunxi_pctrl_get_group_name, 451 .get_group_pins = sunxi_pctrl_get_group_pins, 452 }; 453 454 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param, 455 u32 *offset, u32 *shift, u32 *mask) 456 { 457 switch (param) { 458 case PIN_CONFIG_DRIVE_STRENGTH: 459 *offset = sunxi_dlevel_reg(pin); 460 *shift = sunxi_dlevel_offset(pin); 461 *mask = DLEVEL_PINS_MASK; 462 break; 463 464 case PIN_CONFIG_BIAS_PULL_UP: 465 case PIN_CONFIG_BIAS_PULL_DOWN: 466 case PIN_CONFIG_BIAS_DISABLE: 467 *offset = sunxi_pull_reg(pin); 468 *shift = sunxi_pull_offset(pin); 469 *mask = PULL_PINS_MASK; 470 break; 471 472 default: 473 return -ENOTSUPP; 474 } 475 476 return 0; 477 } 478 479 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin, 480 unsigned long *config) 481 { 482 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 483 enum pin_config_param param = pinconf_to_config_param(*config); 484 u32 offset, shift, mask, val; 485 u16 arg; 486 int ret; 487 488 pin -= pctl->desc->pin_base; 489 490 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); 491 if (ret < 0) 492 return ret; 493 494 val = (readl(pctl->membase + offset) >> shift) & mask; 495 496 switch (pinconf_to_config_param(*config)) { 497 case PIN_CONFIG_DRIVE_STRENGTH: 498 arg = (val + 1) * 10; 499 break; 500 501 case PIN_CONFIG_BIAS_PULL_UP: 502 if (val != SUN4I_PINCTRL_PULL_UP) 503 return -EINVAL; 504 arg = 1; /* hardware is weak pull-up */ 505 break; 506 507 case PIN_CONFIG_BIAS_PULL_DOWN: 508 if (val != SUN4I_PINCTRL_PULL_DOWN) 509 return -EINVAL; 510 arg = 1; /* hardware is weak pull-down */ 511 break; 512 513 case PIN_CONFIG_BIAS_DISABLE: 514 if (val != SUN4I_PINCTRL_NO_PULL) 515 return -EINVAL; 516 arg = 0; 517 break; 518 519 default: 520 /* sunxi_pconf_reg should catch anything unsupported */ 521 WARN_ON(1); 522 return -ENOTSUPP; 523 } 524 525 *config = pinconf_to_config_packed(param, arg); 526 527 return 0; 528 } 529 530 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 531 unsigned group, 532 unsigned long *config) 533 { 534 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 535 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 536 537 /* We only support 1 pin per group. Chain it to the pin callback */ 538 return sunxi_pconf_get(pctldev, g->pin, config); 539 } 540 541 static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin, 542 unsigned long *configs, unsigned num_configs) 543 { 544 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 545 int i; 546 547 pin -= pctl->desc->pin_base; 548 549 for (i = 0; i < num_configs; i++) { 550 enum pin_config_param param; 551 unsigned long flags; 552 u32 offset, shift, mask, reg; 553 u32 arg, val; 554 int ret; 555 556 param = pinconf_to_config_param(configs[i]); 557 arg = pinconf_to_config_argument(configs[i]); 558 559 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); 560 if (ret < 0) 561 return ret; 562 563 switch (param) { 564 case PIN_CONFIG_DRIVE_STRENGTH: 565 if (arg < 10 || arg > 40) 566 return -EINVAL; 567 /* 568 * We convert from mA to what the register expects: 569 * 0: 10mA 570 * 1: 20mA 571 * 2: 30mA 572 * 3: 40mA 573 */ 574 val = arg / 10 - 1; 575 break; 576 case PIN_CONFIG_BIAS_DISABLE: 577 val = 0; 578 break; 579 case PIN_CONFIG_BIAS_PULL_UP: 580 if (arg == 0) 581 return -EINVAL; 582 val = 1; 583 break; 584 case PIN_CONFIG_BIAS_PULL_DOWN: 585 if (arg == 0) 586 return -EINVAL; 587 val = 2; 588 break; 589 default: 590 /* sunxi_pconf_reg should catch anything unsupported */ 591 WARN_ON(1); 592 return -ENOTSUPP; 593 } 594 595 raw_spin_lock_irqsave(&pctl->lock, flags); 596 reg = readl(pctl->membase + offset); 597 reg &= ~(mask << shift); 598 writel(reg | val << shift, pctl->membase + offset); 599 raw_spin_unlock_irqrestore(&pctl->lock, flags); 600 } /* for each config */ 601 602 return 0; 603 } 604 605 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 606 unsigned long *configs, unsigned num_configs) 607 { 608 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 609 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 610 611 /* We only support 1 pin per group. Chain it to the pin callback */ 612 return sunxi_pconf_set(pctldev, g->pin, configs, num_configs); 613 } 614 615 static const struct pinconf_ops sunxi_pconf_ops = { 616 .is_generic = true, 617 .pin_config_get = sunxi_pconf_get, 618 .pin_config_set = sunxi_pconf_set, 619 .pin_config_group_get = sunxi_pconf_group_get, 620 .pin_config_group_set = sunxi_pconf_group_set, 621 }; 622 623 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, 624 unsigned pin, 625 struct regulator *supply) 626 { 627 unsigned short bank = pin / PINS_PER_BANK; 628 unsigned long flags; 629 u32 val, reg; 630 int uV; 631 632 if (!pctl->desc->io_bias_cfg_variant) 633 return 0; 634 635 uV = regulator_get_voltage(supply); 636 if (uV < 0) 637 return uV; 638 639 /* Might be dummy regulator with no voltage set */ 640 if (uV == 0) 641 return 0; 642 643 switch (pctl->desc->io_bias_cfg_variant) { 644 case BIAS_VOLTAGE_GRP_CONFIG: 645 /* 646 * Configured value must be equal or greater to actual 647 * voltage. 648 */ 649 if (uV <= 1800000) 650 val = 0x0; /* 1.8V */ 651 else if (uV <= 2500000) 652 val = 0x6; /* 2.5V */ 653 else if (uV <= 2800000) 654 val = 0x9; /* 2.8V */ 655 else if (uV <= 3000000) 656 val = 0xA; /* 3.0V */ 657 else 658 val = 0xD; /* 3.3V */ 659 660 pin -= pctl->desc->pin_base; 661 662 reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); 663 reg &= ~IO_BIAS_MASK; 664 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); 665 return 0; 666 case BIAS_VOLTAGE_PIO_POW_MODE_SEL: 667 val = uV <= 1800000 ? 1 : 0; 668 669 raw_spin_lock_irqsave(&pctl->lock, flags); 670 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); 671 reg &= ~(1 << bank); 672 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); 673 raw_spin_unlock_irqrestore(&pctl->lock, flags); 674 return 0; 675 default: 676 return -EINVAL; 677 } 678 } 679 680 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 681 { 682 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 683 684 return pctl->nfunctions; 685 } 686 687 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 688 unsigned function) 689 { 690 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 691 692 return pctl->functions[function].name; 693 } 694 695 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 696 unsigned function, 697 const char * const **groups, 698 unsigned * const num_groups) 699 { 700 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 701 702 *groups = pctl->functions[function].groups; 703 *num_groups = pctl->functions[function].ngroups; 704 705 return 0; 706 } 707 708 static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 709 unsigned pin, 710 u8 config) 711 { 712 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 713 unsigned long flags; 714 u32 val, mask; 715 716 raw_spin_lock_irqsave(&pctl->lock, flags); 717 718 pin -= pctl->desc->pin_base; 719 val = readl(pctl->membase + sunxi_mux_reg(pin)); 720 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 721 writel((val & ~mask) | config << sunxi_mux_offset(pin), 722 pctl->membase + sunxi_mux_reg(pin)); 723 724 raw_spin_unlock_irqrestore(&pctl->lock, flags); 725 } 726 727 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, 728 unsigned function, 729 unsigned group) 730 { 731 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 732 struct sunxi_pinctrl_group *g = pctl->groups + group; 733 struct sunxi_pinctrl_function *func = pctl->functions + function; 734 struct sunxi_desc_function *desc = 735 sunxi_pinctrl_desc_find_function_by_name(pctl, 736 g->name, 737 func->name); 738 739 if (!desc) 740 return -EINVAL; 741 742 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 743 744 return 0; 745 } 746 747 static int 748 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 749 struct pinctrl_gpio_range *range, 750 unsigned offset, 751 bool input) 752 { 753 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 754 struct sunxi_desc_function *desc; 755 const char *func; 756 757 if (input) 758 func = "gpio_in"; 759 else 760 func = "gpio_out"; 761 762 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); 763 if (!desc) 764 return -EINVAL; 765 766 sunxi_pmx_set(pctldev, offset, desc->muxval); 767 768 return 0; 769 } 770 771 static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset) 772 { 773 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 774 unsigned short bank = offset / PINS_PER_BANK; 775 unsigned short bank_offset = bank - pctl->desc->pin_base / 776 PINS_PER_BANK; 777 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; 778 struct regulator *reg = s_reg->regulator; 779 char supply[16]; 780 int ret; 781 782 if (reg) { 783 refcount_inc(&s_reg->refcount); 784 return 0; 785 } 786 787 snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank); 788 reg = regulator_get(pctl->dev, supply); 789 if (IS_ERR(reg)) 790 return dev_err_probe(pctl->dev, PTR_ERR(reg), 791 "Couldn't get bank P%c regulator\n", 792 'A' + bank); 793 794 ret = regulator_enable(reg); 795 if (ret) { 796 dev_err(pctl->dev, 797 "Couldn't enable bank P%c regulator\n", 'A' + bank); 798 goto out; 799 } 800 801 sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg); 802 803 s_reg->regulator = reg; 804 refcount_set(&s_reg->refcount, 1); 805 806 return 0; 807 808 out: 809 regulator_put(s_reg->regulator); 810 811 return ret; 812 } 813 814 static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset) 815 { 816 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 817 unsigned short bank = offset / PINS_PER_BANK; 818 unsigned short bank_offset = bank - pctl->desc->pin_base / 819 PINS_PER_BANK; 820 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; 821 822 if (!refcount_dec_and_test(&s_reg->refcount)) 823 return 0; 824 825 regulator_disable(s_reg->regulator); 826 regulator_put(s_reg->regulator); 827 s_reg->regulator = NULL; 828 829 return 0; 830 } 831 832 static const struct pinmux_ops sunxi_pmx_ops = { 833 .get_functions_count = sunxi_pmx_get_funcs_cnt, 834 .get_function_name = sunxi_pmx_get_func_name, 835 .get_function_groups = sunxi_pmx_get_func_groups, 836 .set_mux = sunxi_pmx_set_mux, 837 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 838 .request = sunxi_pmx_request, 839 .free = sunxi_pmx_free, 840 .strict = true, 841 }; 842 843 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 844 unsigned offset) 845 { 846 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 847 848 return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL, 849 chip->base + offset, true); 850 } 851 852 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 853 { 854 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 855 u32 reg = sunxi_data_reg(offset); 856 u8 index = sunxi_data_offset(offset); 857 bool set_mux = pctl->desc->irq_read_needs_mux && 858 gpiochip_line_is_irq(chip, offset); 859 u32 pin = offset + chip->base; 860 u32 val; 861 862 if (set_mux) 863 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); 864 865 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; 866 867 if (set_mux) 868 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); 869 870 return !!val; 871 } 872 873 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 874 unsigned offset, int value) 875 { 876 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 877 u32 reg = sunxi_data_reg(offset); 878 u8 index = sunxi_data_offset(offset); 879 unsigned long flags; 880 u32 regval; 881 882 raw_spin_lock_irqsave(&pctl->lock, flags); 883 884 regval = readl(pctl->membase + reg); 885 886 if (value) 887 regval |= BIT(index); 888 else 889 regval &= ~(BIT(index)); 890 891 writel(regval, pctl->membase + reg); 892 893 raw_spin_unlock_irqrestore(&pctl->lock, flags); 894 } 895 896 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 897 unsigned offset, int value) 898 { 899 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 900 901 sunxi_pinctrl_gpio_set(chip, offset, value); 902 return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL, 903 chip->base + offset, false); 904 } 905 906 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 907 const struct of_phandle_args *gpiospec, 908 u32 *flags) 909 { 910 int pin, base; 911 912 base = PINS_PER_BANK * gpiospec->args[0]; 913 pin = base + gpiospec->args[1]; 914 915 if (pin > gc->ngpio) 916 return -EINVAL; 917 918 if (flags) 919 *flags = gpiospec->args[2]; 920 921 return pin; 922 } 923 924 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 925 { 926 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 927 struct sunxi_desc_function *desc; 928 unsigned pinnum = pctl->desc->pin_base + offset; 929 unsigned irqnum; 930 931 if (offset >= chip->ngpio) 932 return -ENXIO; 933 934 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq"); 935 if (!desc) 936 return -EINVAL; 937 938 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum; 939 940 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n", 941 chip->label, offset + chip->base, irqnum); 942 943 return irq_find_mapping(pctl->domain, irqnum); 944 } 945 946 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) 947 { 948 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 949 struct sunxi_desc_function *func; 950 int ret; 951 952 func = sunxi_pinctrl_desc_find_function_by_pin(pctl, 953 pctl->irq_array[d->hwirq], "irq"); 954 if (!func) 955 return -EINVAL; 956 957 ret = gpiochip_lock_as_irq(pctl->chip, 958 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 959 if (ret) { 960 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 961 irqd_to_hwirq(d)); 962 return ret; 963 } 964 965 /* Change muxing to INT mode */ 966 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); 967 968 return 0; 969 } 970 971 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) 972 { 973 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 974 975 gpiochip_unlock_as_irq(pctl->chip, 976 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 977 } 978 979 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) 980 { 981 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 982 u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq); 983 u8 index = sunxi_irq_cfg_offset(d->hwirq); 984 unsigned long flags; 985 u32 regval; 986 u8 mode; 987 988 switch (type) { 989 case IRQ_TYPE_EDGE_RISING: 990 mode = IRQ_EDGE_RISING; 991 break; 992 case IRQ_TYPE_EDGE_FALLING: 993 mode = IRQ_EDGE_FALLING; 994 break; 995 case IRQ_TYPE_EDGE_BOTH: 996 mode = IRQ_EDGE_BOTH; 997 break; 998 case IRQ_TYPE_LEVEL_HIGH: 999 mode = IRQ_LEVEL_HIGH; 1000 break; 1001 case IRQ_TYPE_LEVEL_LOW: 1002 mode = IRQ_LEVEL_LOW; 1003 break; 1004 default: 1005 return -EINVAL; 1006 } 1007 1008 raw_spin_lock_irqsave(&pctl->lock, flags); 1009 1010 if (type & IRQ_TYPE_LEVEL_MASK) 1011 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip, 1012 handle_fasteoi_irq, NULL); 1013 else 1014 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip, 1015 handle_edge_irq, NULL); 1016 1017 regval = readl(pctl->membase + reg); 1018 regval &= ~(IRQ_CFG_IRQ_MASK << index); 1019 writel(regval | (mode << index), pctl->membase + reg); 1020 1021 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1022 1023 return 0; 1024 } 1025 1026 static void sunxi_pinctrl_irq_ack(struct irq_data *d) 1027 { 1028 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1029 u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq); 1030 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 1031 1032 /* Clear the IRQ */ 1033 writel(1 << status_idx, pctl->membase + status_reg); 1034 } 1035 1036 static void sunxi_pinctrl_irq_mask(struct irq_data *d) 1037 { 1038 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1039 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); 1040 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 1041 unsigned long flags; 1042 u32 val; 1043 1044 raw_spin_lock_irqsave(&pctl->lock, flags); 1045 1046 /* Mask the IRQ */ 1047 val = readl(pctl->membase + reg); 1048 writel(val & ~(1 << idx), pctl->membase + reg); 1049 1050 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1051 } 1052 1053 static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 1054 { 1055 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1056 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); 1057 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 1058 unsigned long flags; 1059 u32 val; 1060 1061 raw_spin_lock_irqsave(&pctl->lock, flags); 1062 1063 /* Unmask the IRQ */ 1064 val = readl(pctl->membase + reg); 1065 writel(val | (1 << idx), pctl->membase + reg); 1066 1067 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1068 } 1069 1070 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) 1071 { 1072 sunxi_pinctrl_irq_ack(d); 1073 sunxi_pinctrl_irq_unmask(d); 1074 } 1075 1076 static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on) 1077 { 1078 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1079 u8 bank = d->hwirq / IRQ_PER_BANK; 1080 1081 return irq_set_irq_wake(pctl->irq[bank], on); 1082 } 1083 1084 static struct irq_chip sunxi_pinctrl_edge_irq_chip = { 1085 .name = "sunxi_pio_edge", 1086 .irq_ack = sunxi_pinctrl_irq_ack, 1087 .irq_mask = sunxi_pinctrl_irq_mask, 1088 .irq_unmask = sunxi_pinctrl_irq_unmask, 1089 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 1090 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 1091 .irq_set_type = sunxi_pinctrl_irq_set_type, 1092 .irq_set_wake = sunxi_pinctrl_irq_set_wake, 1093 .flags = IRQCHIP_MASK_ON_SUSPEND, 1094 }; 1095 1096 static struct irq_chip sunxi_pinctrl_level_irq_chip = { 1097 .name = "sunxi_pio_level", 1098 .irq_eoi = sunxi_pinctrl_irq_ack, 1099 .irq_mask = sunxi_pinctrl_irq_mask, 1100 .irq_unmask = sunxi_pinctrl_irq_unmask, 1101 /* Define irq_enable / disable to avoid spurious irqs for drivers 1102 * using these to suppress irqs while they clear the irq source */ 1103 .irq_enable = sunxi_pinctrl_irq_ack_unmask, 1104 .irq_disable = sunxi_pinctrl_irq_mask, 1105 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 1106 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 1107 .irq_set_type = sunxi_pinctrl_irq_set_type, 1108 .irq_set_wake = sunxi_pinctrl_irq_set_wake, 1109 .flags = IRQCHIP_EOI_THREADED | 1110 IRQCHIP_MASK_ON_SUSPEND | 1111 IRQCHIP_EOI_IF_HANDLED, 1112 }; 1113 1114 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, 1115 struct device_node *node, 1116 const u32 *intspec, 1117 unsigned int intsize, 1118 unsigned long *out_hwirq, 1119 unsigned int *out_type) 1120 { 1121 struct sunxi_pinctrl *pctl = d->host_data; 1122 struct sunxi_desc_function *desc; 1123 int pin, base; 1124 1125 if (intsize < 3) 1126 return -EINVAL; 1127 1128 base = PINS_PER_BANK * intspec[0]; 1129 pin = pctl->desc->pin_base + base + intspec[1]; 1130 1131 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); 1132 if (!desc) 1133 return -EINVAL; 1134 1135 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum; 1136 *out_type = intspec[2]; 1137 1138 return 0; 1139 } 1140 1141 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = { 1142 .xlate = sunxi_pinctrl_irq_of_xlate, 1143 }; 1144 1145 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) 1146 { 1147 unsigned int irq = irq_desc_get_irq(desc); 1148 struct irq_chip *chip = irq_desc_get_chip(desc); 1149 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc); 1150 unsigned long bank, reg, val; 1151 1152 for (bank = 0; bank < pctl->desc->irq_banks; bank++) 1153 if (irq == pctl->irq[bank]) 1154 break; 1155 1156 WARN_ON(bank == pctl->desc->irq_banks); 1157 1158 chained_irq_enter(chip, desc); 1159 1160 reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); 1161 val = readl(pctl->membase + reg); 1162 1163 if (val) { 1164 int irqoffset; 1165 1166 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) 1167 generic_handle_domain_irq(pctl->domain, 1168 bank * IRQ_PER_BANK + irqoffset); 1169 } 1170 1171 chained_irq_exit(chip, desc); 1172 } 1173 1174 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 1175 const char *name) 1176 { 1177 struct sunxi_pinctrl_function *func = pctl->functions; 1178 1179 while (func->name) { 1180 /* function already there */ 1181 if (strcmp(func->name, name) == 0) { 1182 func->ngroups++; 1183 return -EEXIST; 1184 } 1185 func++; 1186 } 1187 1188 func->name = name; 1189 func->ngroups = 1; 1190 1191 pctl->nfunctions++; 1192 1193 return 0; 1194 } 1195 1196 static int sunxi_pinctrl_build_state(struct platform_device *pdev) 1197 { 1198 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 1199 void *ptr; 1200 int i; 1201 1202 /* 1203 * Allocate groups 1204 * 1205 * We assume that the number of groups is the number of pins 1206 * given in the data array. 1207 1208 * This will not always be true, since some pins might not be 1209 * available in the current variant, but fortunately for us, 1210 * this means that the number of pins is the maximum group 1211 * number we will ever see. 1212 */ 1213 pctl->groups = devm_kcalloc(&pdev->dev, 1214 pctl->desc->npins, sizeof(*pctl->groups), 1215 GFP_KERNEL); 1216 if (!pctl->groups) 1217 return -ENOMEM; 1218 1219 for (i = 0; i < pctl->desc->npins; i++) { 1220 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1221 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups; 1222 1223 if (pin->variant && !(pctl->variant & pin->variant)) 1224 continue; 1225 1226 group->name = pin->pin.name; 1227 group->pin = pin->pin.number; 1228 1229 /* And now we count the actual number of pins / groups */ 1230 pctl->ngroups++; 1231 } 1232 1233 /* 1234 * Find an upper bound for the maximum number of functions: in 1235 * the worst case we have gpio_in, gpio_out, irq and up to four 1236 * special functions per pin, plus one entry for the sentinel. 1237 * We'll reallocate that later anyway. 1238 */ 1239 pctl->functions = kcalloc(4 * pctl->ngroups + 4, 1240 sizeof(*pctl->functions), 1241 GFP_KERNEL); 1242 if (!pctl->functions) 1243 return -ENOMEM; 1244 1245 /* Count functions and their associated groups */ 1246 for (i = 0; i < pctl->desc->npins; i++) { 1247 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1248 struct sunxi_desc_function *func; 1249 1250 if (pin->variant && !(pctl->variant & pin->variant)) 1251 continue; 1252 1253 for (func = pin->functions; func->name; func++) { 1254 if (func->variant && !(pctl->variant & func->variant)) 1255 continue; 1256 1257 /* Create interrupt mapping while we're at it */ 1258 if (!strcmp(func->name, "irq")) { 1259 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; 1260 pctl->irq_array[irqnum] = pin->pin.number; 1261 } 1262 1263 sunxi_pinctrl_add_function(pctl, func->name); 1264 } 1265 } 1266 1267 /* And now allocated and fill the array for real */ 1268 ptr = krealloc(pctl->functions, 1269 pctl->nfunctions * sizeof(*pctl->functions), 1270 GFP_KERNEL); 1271 if (!ptr) { 1272 kfree(pctl->functions); 1273 pctl->functions = NULL; 1274 return -ENOMEM; 1275 } 1276 pctl->functions = ptr; 1277 1278 for (i = 0; i < pctl->desc->npins; i++) { 1279 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1280 struct sunxi_desc_function *func; 1281 1282 if (pin->variant && !(pctl->variant & pin->variant)) 1283 continue; 1284 1285 for (func = pin->functions; func->name; func++) { 1286 struct sunxi_pinctrl_function *func_item; 1287 const char **func_grp; 1288 1289 if (func->variant && !(pctl->variant & func->variant)) 1290 continue; 1291 1292 func_item = sunxi_pinctrl_find_function_by_name(pctl, 1293 func->name); 1294 if (!func_item) { 1295 kfree(pctl->functions); 1296 return -EINVAL; 1297 } 1298 1299 if (!func_item->groups) { 1300 func_item->groups = 1301 devm_kcalloc(&pdev->dev, 1302 func_item->ngroups, 1303 sizeof(*func_item->groups), 1304 GFP_KERNEL); 1305 if (!func_item->groups) { 1306 kfree(pctl->functions); 1307 return -ENOMEM; 1308 } 1309 } 1310 1311 func_grp = func_item->groups; 1312 while (*func_grp) 1313 func_grp++; 1314 1315 *func_grp = pin->pin.name; 1316 } 1317 } 1318 1319 return 0; 1320 } 1321 1322 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff) 1323 { 1324 unsigned long clock = clk_get_rate(clk); 1325 unsigned int best_diff, best_div; 1326 int i; 1327 1328 best_diff = abs(freq - clock); 1329 best_div = 0; 1330 1331 for (i = 1; i < 8; i++) { 1332 int cur_diff = abs(freq - (clock >> i)); 1333 1334 if (cur_diff < best_diff) { 1335 best_diff = cur_diff; 1336 best_div = i; 1337 } 1338 } 1339 1340 *diff = best_diff; 1341 return best_div; 1342 } 1343 1344 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, 1345 struct device_node *node) 1346 { 1347 unsigned int hosc_diff, losc_diff; 1348 unsigned int hosc_div, losc_div; 1349 struct clk *hosc, *losc; 1350 u8 div, src; 1351 int i, ret; 1352 1353 /* Deal with old DTs that didn't have the oscillators */ 1354 if (of_clk_get_parent_count(node) != 3) 1355 return 0; 1356 1357 /* If we don't have any setup, bail out */ 1358 if (!of_find_property(node, "input-debounce", NULL)) 1359 return 0; 1360 1361 losc = devm_clk_get(pctl->dev, "losc"); 1362 if (IS_ERR(losc)) 1363 return PTR_ERR(losc); 1364 1365 hosc = devm_clk_get(pctl->dev, "hosc"); 1366 if (IS_ERR(hosc)) 1367 return PTR_ERR(hosc); 1368 1369 for (i = 0; i < pctl->desc->irq_banks; i++) { 1370 unsigned long debounce_freq; 1371 u32 debounce; 1372 1373 ret = of_property_read_u32_index(node, "input-debounce", 1374 i, &debounce); 1375 if (ret) 1376 return ret; 1377 1378 if (!debounce) 1379 continue; 1380 1381 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce); 1382 losc_div = sunxi_pinctrl_get_debounce_div(losc, 1383 debounce_freq, 1384 &losc_diff); 1385 1386 hosc_div = sunxi_pinctrl_get_debounce_div(hosc, 1387 debounce_freq, 1388 &hosc_diff); 1389 1390 if (hosc_diff < losc_diff) { 1391 div = hosc_div; 1392 src = 1; 1393 } else { 1394 div = losc_div; 1395 src = 0; 1396 } 1397 1398 writel(src | div << 4, 1399 pctl->membase + 1400 sunxi_irq_debounce_reg_from_bank(pctl->desc, i)); 1401 } 1402 1403 return 0; 1404 } 1405 1406 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, 1407 const struct sunxi_pinctrl_desc *desc, 1408 unsigned long variant) 1409 { 1410 struct device_node *node = pdev->dev.of_node; 1411 struct pinctrl_desc *pctrl_desc; 1412 struct pinctrl_pin_desc *pins; 1413 struct sunxi_pinctrl *pctl; 1414 struct pinmux_ops *pmxops; 1415 int i, ret, last_pin, pin_idx; 1416 struct clk *clk; 1417 1418 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1419 if (!pctl) 1420 return -ENOMEM; 1421 platform_set_drvdata(pdev, pctl); 1422 1423 raw_spin_lock_init(&pctl->lock); 1424 1425 pctl->membase = devm_platform_ioremap_resource(pdev, 0); 1426 if (IS_ERR(pctl->membase)) 1427 return PTR_ERR(pctl->membase); 1428 1429 pctl->dev = &pdev->dev; 1430 pctl->desc = desc; 1431 pctl->variant = variant; 1432 1433 pctl->irq_array = devm_kcalloc(&pdev->dev, 1434 IRQ_PER_BANK * pctl->desc->irq_banks, 1435 sizeof(*pctl->irq_array), 1436 GFP_KERNEL); 1437 if (!pctl->irq_array) 1438 return -ENOMEM; 1439 1440 ret = sunxi_pinctrl_build_state(pdev); 1441 if (ret) { 1442 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 1443 return ret; 1444 } 1445 1446 pins = devm_kcalloc(&pdev->dev, 1447 pctl->desc->npins, sizeof(*pins), 1448 GFP_KERNEL); 1449 if (!pins) 1450 return -ENOMEM; 1451 1452 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) { 1453 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1454 1455 if (pin->variant && !(pctl->variant & pin->variant)) 1456 continue; 1457 1458 pins[pin_idx++] = pin->pin; 1459 } 1460 1461 pctrl_desc = devm_kzalloc(&pdev->dev, 1462 sizeof(*pctrl_desc), 1463 GFP_KERNEL); 1464 if (!pctrl_desc) 1465 return -ENOMEM; 1466 1467 pctrl_desc->name = dev_name(&pdev->dev); 1468 pctrl_desc->owner = THIS_MODULE; 1469 pctrl_desc->pins = pins; 1470 pctrl_desc->npins = pctl->ngroups; 1471 pctrl_desc->confops = &sunxi_pconf_ops; 1472 pctrl_desc->pctlops = &sunxi_pctrl_ops; 1473 1474 pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops), 1475 GFP_KERNEL); 1476 if (!pmxops) 1477 return -ENOMEM; 1478 1479 if (desc->disable_strict_mode) 1480 pmxops->strict = false; 1481 1482 pctrl_desc->pmxops = pmxops; 1483 1484 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); 1485 if (IS_ERR(pctl->pctl_dev)) { 1486 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1487 return PTR_ERR(pctl->pctl_dev); 1488 } 1489 1490 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1491 if (!pctl->chip) 1492 return -ENOMEM; 1493 1494 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 1495 pctl->chip->owner = THIS_MODULE; 1496 pctl->chip->request = gpiochip_generic_request; 1497 pctl->chip->free = gpiochip_generic_free; 1498 pctl->chip->set_config = gpiochip_generic_config; 1499 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input; 1500 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output; 1501 pctl->chip->get = sunxi_pinctrl_gpio_get; 1502 pctl->chip->set = sunxi_pinctrl_gpio_set; 1503 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate; 1504 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq; 1505 pctl->chip->of_gpio_n_cells = 3; 1506 pctl->chip->can_sleep = false; 1507 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - 1508 pctl->desc->pin_base; 1509 pctl->chip->label = dev_name(&pdev->dev); 1510 pctl->chip->parent = &pdev->dev; 1511 pctl->chip->base = pctl->desc->pin_base; 1512 1513 ret = gpiochip_add_data(pctl->chip, pctl); 1514 if (ret) 1515 return ret; 1516 1517 for (i = 0; i < pctl->desc->npins; i++) { 1518 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1519 1520 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1521 pin->pin.number - pctl->desc->pin_base, 1522 pin->pin.number, 1); 1523 if (ret) 1524 goto gpiochip_error; 1525 } 1526 1527 ret = of_clk_get_parent_count(node); 1528 clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb"); 1529 if (IS_ERR(clk)) { 1530 ret = PTR_ERR(clk); 1531 goto gpiochip_error; 1532 } 1533 1534 ret = clk_prepare_enable(clk); 1535 if (ret) 1536 goto gpiochip_error; 1537 1538 pctl->irq = devm_kcalloc(&pdev->dev, 1539 pctl->desc->irq_banks, 1540 sizeof(*pctl->irq), 1541 GFP_KERNEL); 1542 if (!pctl->irq) { 1543 ret = -ENOMEM; 1544 goto clk_error; 1545 } 1546 1547 for (i = 0; i < pctl->desc->irq_banks; i++) { 1548 pctl->irq[i] = platform_get_irq(pdev, i); 1549 if (pctl->irq[i] < 0) { 1550 ret = pctl->irq[i]; 1551 goto clk_error; 1552 } 1553 } 1554 1555 pctl->domain = irq_domain_add_linear(node, 1556 pctl->desc->irq_banks * IRQ_PER_BANK, 1557 &sunxi_pinctrl_irq_domain_ops, 1558 pctl); 1559 if (!pctl->domain) { 1560 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 1561 ret = -ENOMEM; 1562 goto clk_error; 1563 } 1564 1565 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { 1566 int irqno = irq_create_mapping(pctl->domain, i); 1567 1568 irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class, 1569 &sunxi_pinctrl_irq_request_class); 1570 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, 1571 handle_edge_irq); 1572 irq_set_chip_data(irqno, pctl); 1573 } 1574 1575 for (i = 0; i < pctl->desc->irq_banks; i++) { 1576 /* Mask and clear all IRQs before registering a handler */ 1577 writel(0, pctl->membase + 1578 sunxi_irq_ctrl_reg_from_bank(pctl->desc, i)); 1579 writel(0xffffffff, 1580 pctl->membase + 1581 sunxi_irq_status_reg_from_bank(pctl->desc, i)); 1582 1583 irq_set_chained_handler_and_data(pctl->irq[i], 1584 sunxi_pinctrl_irq_handler, 1585 pctl); 1586 } 1587 1588 sunxi_pinctrl_setup_debounce(pctl, node); 1589 1590 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1591 1592 return 0; 1593 1594 clk_error: 1595 clk_disable_unprepare(clk); 1596 gpiochip_error: 1597 gpiochip_remove(pctl->chip); 1598 return ret; 1599 } 1600