1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/io.h> 14 #include <linux/clk.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/irqdomain.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/export.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_device.h> 22 #include <linux/of_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/machine.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinconf-generic.h> 27 #include <linux/pinctrl/pinmux.h> 28 #include <linux/platform_device.h> 29 #include <linux/slab.h> 30 31 #include "../core.h" 32 #include "../../gpio/gpiolib.h" 33 #include "pinctrl-sunxi.h" 34 35 static struct irq_chip sunxi_pinctrl_edge_irq_chip; 36 static struct irq_chip sunxi_pinctrl_level_irq_chip; 37 38 static struct sunxi_pinctrl_group * 39 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 40 { 41 int i; 42 43 for (i = 0; i < pctl->ngroups; i++) { 44 struct sunxi_pinctrl_group *grp = pctl->groups + i; 45 46 if (!strcmp(grp->name, group)) 47 return grp; 48 } 49 50 return NULL; 51 } 52 53 static struct sunxi_pinctrl_function * 54 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 55 const char *name) 56 { 57 struct sunxi_pinctrl_function *func = pctl->functions; 58 int i; 59 60 for (i = 0; i < pctl->nfunctions; i++) { 61 if (!func[i].name) 62 break; 63 64 if (!strcmp(func[i].name, name)) 65 return func + i; 66 } 67 68 return NULL; 69 } 70 71 static struct sunxi_desc_function * 72 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 73 const char *pin_name, 74 const char *func_name) 75 { 76 int i; 77 78 for (i = 0; i < pctl->desc->npins; i++) { 79 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 80 81 if (!strcmp(pin->pin.name, pin_name)) { 82 struct sunxi_desc_function *func = pin->functions; 83 84 while (func->name) { 85 if (!strcmp(func->name, func_name)) 86 return func; 87 88 func++; 89 } 90 } 91 } 92 93 return NULL; 94 } 95 96 static struct sunxi_desc_function * 97 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, 98 const u16 pin_num, 99 const char *func_name) 100 { 101 int i; 102 103 for (i = 0; i < pctl->desc->npins; i++) { 104 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 105 106 if (pin->pin.number == pin_num) { 107 struct sunxi_desc_function *func = pin->functions; 108 109 while (func->name) { 110 if (!strcmp(func->name, func_name)) 111 return func; 112 113 func++; 114 } 115 } 116 } 117 118 return NULL; 119 } 120 121 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 122 { 123 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 124 125 return pctl->ngroups; 126 } 127 128 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 129 unsigned group) 130 { 131 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 132 133 return pctl->groups[group].name; 134 } 135 136 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 137 unsigned group, 138 const unsigned **pins, 139 unsigned *num_pins) 140 { 141 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 142 143 *pins = (unsigned *)&pctl->groups[group].pin; 144 *num_pins = 1; 145 146 return 0; 147 } 148 149 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 150 struct device_node *node, 151 struct pinctrl_map **map, 152 unsigned *num_maps) 153 { 154 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 155 unsigned long *pinconfig; 156 struct property *prop; 157 const char *function; 158 const char *group; 159 int ret, nmaps, i = 0; 160 u32 val; 161 162 *map = NULL; 163 *num_maps = 0; 164 165 ret = of_property_read_string(node, "allwinner,function", &function); 166 if (ret) { 167 dev_err(pctl->dev, 168 "missing allwinner,function property in node %s\n", 169 node->name); 170 return -EINVAL; 171 } 172 173 nmaps = of_property_count_strings(node, "allwinner,pins") * 2; 174 if (nmaps < 0) { 175 dev_err(pctl->dev, 176 "missing allwinner,pins property in node %s\n", 177 node->name); 178 return -EINVAL; 179 } 180 181 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); 182 if (!*map) 183 return -ENOMEM; 184 185 of_property_for_each_string(node, "allwinner,pins", prop, group) { 186 struct sunxi_pinctrl_group *grp = 187 sunxi_pinctrl_find_group_by_name(pctl, group); 188 int j = 0, configlen = 0; 189 190 if (!grp) { 191 dev_err(pctl->dev, "unknown pin %s", group); 192 continue; 193 } 194 195 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 196 grp->name, 197 function)) { 198 dev_err(pctl->dev, "unsupported function %s on pin %s", 199 function, group); 200 continue; 201 } 202 203 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 204 (*map)[i].data.mux.group = group; 205 (*map)[i].data.mux.function = function; 206 207 i++; 208 209 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 210 (*map)[i].data.configs.group_or_pin = group; 211 212 if (of_find_property(node, "allwinner,drive", NULL)) 213 configlen++; 214 if (of_find_property(node, "allwinner,pull", NULL)) 215 configlen++; 216 217 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); 218 if (!pinconfig) { 219 kfree(*map); 220 return -ENOMEM; 221 } 222 223 if (!of_property_read_u32(node, "allwinner,drive", &val)) { 224 u16 strength = (val + 1) * 10; 225 pinconfig[j++] = 226 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 227 strength); 228 } 229 230 if (!of_property_read_u32(node, "allwinner,pull", &val)) { 231 enum pin_config_param pull = PIN_CONFIG_END; 232 if (val == 1) 233 pull = PIN_CONFIG_BIAS_PULL_UP; 234 else if (val == 2) 235 pull = PIN_CONFIG_BIAS_PULL_DOWN; 236 pinconfig[j++] = pinconf_to_config_packed(pull, 0); 237 } 238 239 (*map)[i].data.configs.configs = pinconfig; 240 (*map)[i].data.configs.num_configs = configlen; 241 242 i++; 243 } 244 245 *num_maps = nmaps; 246 247 return 0; 248 } 249 250 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 251 struct pinctrl_map *map, 252 unsigned num_maps) 253 { 254 int i; 255 256 for (i = 0; i < num_maps; i++) { 257 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) 258 kfree(map[i].data.configs.configs); 259 } 260 261 kfree(map); 262 } 263 264 static const struct pinctrl_ops sunxi_pctrl_ops = { 265 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 266 .dt_free_map = sunxi_pctrl_dt_free_map, 267 .get_groups_count = sunxi_pctrl_get_groups_count, 268 .get_group_name = sunxi_pctrl_get_group_name, 269 .get_group_pins = sunxi_pctrl_get_group_pins, 270 }; 271 272 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 273 unsigned group, 274 unsigned long *config) 275 { 276 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 277 278 *config = pctl->groups[group].config; 279 280 return 0; 281 } 282 283 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, 284 unsigned group, 285 unsigned long *configs, 286 unsigned num_configs) 287 { 288 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 289 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 290 unsigned long flags; 291 unsigned pin = g->pin - pctl->desc->pin_base; 292 u32 val, mask; 293 u16 strength; 294 u8 dlevel; 295 int i; 296 297 spin_lock_irqsave(&pctl->lock, flags); 298 299 for (i = 0; i < num_configs; i++) { 300 switch (pinconf_to_config_param(configs[i])) { 301 case PIN_CONFIG_DRIVE_STRENGTH: 302 strength = pinconf_to_config_argument(configs[i]); 303 if (strength > 40) { 304 spin_unlock_irqrestore(&pctl->lock, flags); 305 return -EINVAL; 306 } 307 /* 308 * We convert from mA to what the register expects: 309 * 0: 10mA 310 * 1: 20mA 311 * 2: 30mA 312 * 3: 40mA 313 */ 314 dlevel = strength / 10 - 1; 315 val = readl(pctl->membase + sunxi_dlevel_reg(pin)); 316 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin); 317 writel((val & ~mask) 318 | dlevel << sunxi_dlevel_offset(pin), 319 pctl->membase + sunxi_dlevel_reg(pin)); 320 break; 321 case PIN_CONFIG_BIAS_PULL_UP: 322 val = readl(pctl->membase + sunxi_pull_reg(pin)); 323 mask = PULL_PINS_MASK << sunxi_pull_offset(pin); 324 writel((val & ~mask) | 1 << sunxi_pull_offset(pin), 325 pctl->membase + sunxi_pull_reg(pin)); 326 break; 327 case PIN_CONFIG_BIAS_PULL_DOWN: 328 val = readl(pctl->membase + sunxi_pull_reg(pin)); 329 mask = PULL_PINS_MASK << sunxi_pull_offset(pin); 330 writel((val & ~mask) | 2 << sunxi_pull_offset(pin), 331 pctl->membase + sunxi_pull_reg(pin)); 332 break; 333 default: 334 break; 335 } 336 /* cache the config value */ 337 g->config = configs[i]; 338 } /* for each config */ 339 340 spin_unlock_irqrestore(&pctl->lock, flags); 341 342 return 0; 343 } 344 345 static const struct pinconf_ops sunxi_pconf_ops = { 346 .pin_config_group_get = sunxi_pconf_group_get, 347 .pin_config_group_set = sunxi_pconf_group_set, 348 }; 349 350 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 351 { 352 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 353 354 return pctl->nfunctions; 355 } 356 357 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 358 unsigned function) 359 { 360 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 361 362 return pctl->functions[function].name; 363 } 364 365 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 366 unsigned function, 367 const char * const **groups, 368 unsigned * const num_groups) 369 { 370 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 371 372 *groups = pctl->functions[function].groups; 373 *num_groups = pctl->functions[function].ngroups; 374 375 return 0; 376 } 377 378 static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 379 unsigned pin, 380 u8 config) 381 { 382 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 383 unsigned long flags; 384 u32 val, mask; 385 386 spin_lock_irqsave(&pctl->lock, flags); 387 388 pin -= pctl->desc->pin_base; 389 val = readl(pctl->membase + sunxi_mux_reg(pin)); 390 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 391 writel((val & ~mask) | config << sunxi_mux_offset(pin), 392 pctl->membase + sunxi_mux_reg(pin)); 393 394 spin_unlock_irqrestore(&pctl->lock, flags); 395 } 396 397 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, 398 unsigned function, 399 unsigned group) 400 { 401 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 402 struct sunxi_pinctrl_group *g = pctl->groups + group; 403 struct sunxi_pinctrl_function *func = pctl->functions + function; 404 struct sunxi_desc_function *desc = 405 sunxi_pinctrl_desc_find_function_by_name(pctl, 406 g->name, 407 func->name); 408 409 if (!desc) 410 return -EINVAL; 411 412 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 413 414 return 0; 415 } 416 417 static int 418 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 419 struct pinctrl_gpio_range *range, 420 unsigned offset, 421 bool input) 422 { 423 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 424 struct sunxi_desc_function *desc; 425 const char *func; 426 427 if (input) 428 func = "gpio_in"; 429 else 430 func = "gpio_out"; 431 432 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); 433 if (!desc) 434 return -EINVAL; 435 436 sunxi_pmx_set(pctldev, offset, desc->muxval); 437 438 return 0; 439 } 440 441 static const struct pinmux_ops sunxi_pmx_ops = { 442 .get_functions_count = sunxi_pmx_get_funcs_cnt, 443 .get_function_name = sunxi_pmx_get_func_name, 444 .get_function_groups = sunxi_pmx_get_func_groups, 445 .set_mux = sunxi_pmx_set_mux, 446 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 447 }; 448 449 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 450 unsigned offset) 451 { 452 return pinctrl_gpio_direction_input(chip->base + offset); 453 } 454 455 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 456 { 457 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 458 u32 reg = sunxi_data_reg(offset); 459 u8 index = sunxi_data_offset(offset); 460 bool set_mux = pctl->desc->irq_read_needs_mux && 461 gpiochip_line_is_irq(chip, offset); 462 u32 pin = offset + chip->base; 463 u32 val; 464 465 if (set_mux) 466 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); 467 468 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; 469 470 if (set_mux) 471 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); 472 473 return !!val; 474 } 475 476 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 477 unsigned offset, int value) 478 { 479 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 480 u32 reg = sunxi_data_reg(offset); 481 u8 index = sunxi_data_offset(offset); 482 unsigned long flags; 483 u32 regval; 484 485 spin_lock_irqsave(&pctl->lock, flags); 486 487 regval = readl(pctl->membase + reg); 488 489 if (value) 490 regval |= BIT(index); 491 else 492 regval &= ~(BIT(index)); 493 494 writel(regval, pctl->membase + reg); 495 496 spin_unlock_irqrestore(&pctl->lock, flags); 497 } 498 499 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 500 unsigned offset, int value) 501 { 502 sunxi_pinctrl_gpio_set(chip, offset, value); 503 return pinctrl_gpio_direction_output(chip->base + offset); 504 } 505 506 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 507 const struct of_phandle_args *gpiospec, 508 u32 *flags) 509 { 510 int pin, base; 511 512 base = PINS_PER_BANK * gpiospec->args[0]; 513 pin = base + gpiospec->args[1]; 514 515 if (pin > gc->ngpio) 516 return -EINVAL; 517 518 if (flags) 519 *flags = gpiospec->args[2]; 520 521 return pin; 522 } 523 524 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 525 { 526 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 527 struct sunxi_desc_function *desc; 528 unsigned pinnum = pctl->desc->pin_base + offset; 529 unsigned irqnum; 530 531 if (offset >= chip->ngpio) 532 return -ENXIO; 533 534 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq"); 535 if (!desc) 536 return -EINVAL; 537 538 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum; 539 540 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n", 541 chip->label, offset + chip->base, irqnum); 542 543 return irq_find_mapping(pctl->domain, irqnum); 544 } 545 546 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) 547 { 548 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 549 struct sunxi_desc_function *func; 550 int ret; 551 552 func = sunxi_pinctrl_desc_find_function_by_pin(pctl, 553 pctl->irq_array[d->hwirq], "irq"); 554 if (!func) 555 return -EINVAL; 556 557 ret = gpiochip_lock_as_irq(pctl->chip, 558 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 559 if (ret) { 560 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 561 irqd_to_hwirq(d)); 562 return ret; 563 } 564 565 /* Change muxing to INT mode */ 566 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); 567 568 return 0; 569 } 570 571 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) 572 { 573 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 574 575 gpiochip_unlock_as_irq(pctl->chip, 576 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 577 } 578 579 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) 580 { 581 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 582 u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base); 583 u8 index = sunxi_irq_cfg_offset(d->hwirq); 584 unsigned long flags; 585 u32 regval; 586 u8 mode; 587 588 switch (type) { 589 case IRQ_TYPE_EDGE_RISING: 590 mode = IRQ_EDGE_RISING; 591 break; 592 case IRQ_TYPE_EDGE_FALLING: 593 mode = IRQ_EDGE_FALLING; 594 break; 595 case IRQ_TYPE_EDGE_BOTH: 596 mode = IRQ_EDGE_BOTH; 597 break; 598 case IRQ_TYPE_LEVEL_HIGH: 599 mode = IRQ_LEVEL_HIGH; 600 break; 601 case IRQ_TYPE_LEVEL_LOW: 602 mode = IRQ_LEVEL_LOW; 603 break; 604 default: 605 return -EINVAL; 606 } 607 608 spin_lock_irqsave(&pctl->lock, flags); 609 610 if (type & IRQ_TYPE_LEVEL_MASK) 611 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip, 612 handle_fasteoi_irq, NULL); 613 else 614 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip, 615 handle_edge_irq, NULL); 616 617 regval = readl(pctl->membase + reg); 618 regval &= ~(IRQ_CFG_IRQ_MASK << index); 619 writel(regval | (mode << index), pctl->membase + reg); 620 621 spin_unlock_irqrestore(&pctl->lock, flags); 622 623 return 0; 624 } 625 626 static void sunxi_pinctrl_irq_ack(struct irq_data *d) 627 { 628 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 629 u32 status_reg = sunxi_irq_status_reg(d->hwirq, 630 pctl->desc->irq_bank_base); 631 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 632 633 /* Clear the IRQ */ 634 writel(1 << status_idx, pctl->membase + status_reg); 635 } 636 637 static void sunxi_pinctrl_irq_mask(struct irq_data *d) 638 { 639 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 640 u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base); 641 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 642 unsigned long flags; 643 u32 val; 644 645 spin_lock_irqsave(&pctl->lock, flags); 646 647 /* Mask the IRQ */ 648 val = readl(pctl->membase + reg); 649 writel(val & ~(1 << idx), pctl->membase + reg); 650 651 spin_unlock_irqrestore(&pctl->lock, flags); 652 } 653 654 static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 655 { 656 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 657 u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base); 658 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 659 unsigned long flags; 660 u32 val; 661 662 spin_lock_irqsave(&pctl->lock, flags); 663 664 /* Unmask the IRQ */ 665 val = readl(pctl->membase + reg); 666 writel(val | (1 << idx), pctl->membase + reg); 667 668 spin_unlock_irqrestore(&pctl->lock, flags); 669 } 670 671 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) 672 { 673 sunxi_pinctrl_irq_ack(d); 674 sunxi_pinctrl_irq_unmask(d); 675 } 676 677 static struct irq_chip sunxi_pinctrl_edge_irq_chip = { 678 .name = "sunxi_pio_edge", 679 .irq_ack = sunxi_pinctrl_irq_ack, 680 .irq_mask = sunxi_pinctrl_irq_mask, 681 .irq_unmask = sunxi_pinctrl_irq_unmask, 682 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 683 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 684 .irq_set_type = sunxi_pinctrl_irq_set_type, 685 .flags = IRQCHIP_SKIP_SET_WAKE, 686 }; 687 688 static struct irq_chip sunxi_pinctrl_level_irq_chip = { 689 .name = "sunxi_pio_level", 690 .irq_eoi = sunxi_pinctrl_irq_ack, 691 .irq_mask = sunxi_pinctrl_irq_mask, 692 .irq_unmask = sunxi_pinctrl_irq_unmask, 693 /* Define irq_enable / disable to avoid spurious irqs for drivers 694 * using these to suppress irqs while they clear the irq source */ 695 .irq_enable = sunxi_pinctrl_irq_ack_unmask, 696 .irq_disable = sunxi_pinctrl_irq_mask, 697 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 698 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 699 .irq_set_type = sunxi_pinctrl_irq_set_type, 700 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED | 701 IRQCHIP_EOI_IF_HANDLED, 702 }; 703 704 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, 705 struct device_node *node, 706 const u32 *intspec, 707 unsigned int intsize, 708 unsigned long *out_hwirq, 709 unsigned int *out_type) 710 { 711 struct sunxi_pinctrl *pctl = d->host_data; 712 struct sunxi_desc_function *desc; 713 int pin, base; 714 715 if (intsize < 3) 716 return -EINVAL; 717 718 base = PINS_PER_BANK * intspec[0]; 719 pin = pctl->desc->pin_base + base + intspec[1]; 720 721 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); 722 if (!desc) 723 return -EINVAL; 724 725 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum; 726 *out_type = intspec[2]; 727 728 return 0; 729 } 730 731 static struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = { 732 .xlate = sunxi_pinctrl_irq_of_xlate, 733 }; 734 735 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) 736 { 737 unsigned int irq = irq_desc_get_irq(desc); 738 struct irq_chip *chip = irq_desc_get_chip(desc); 739 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc); 740 unsigned long bank, reg, val; 741 742 for (bank = 0; bank < pctl->desc->irq_banks; bank++) 743 if (irq == pctl->irq[bank]) 744 break; 745 746 if (bank == pctl->desc->irq_banks) 747 return; 748 749 reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base); 750 val = readl(pctl->membase + reg); 751 752 if (val) { 753 int irqoffset; 754 755 chained_irq_enter(chip, desc); 756 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) { 757 int pin_irq = irq_find_mapping(pctl->domain, 758 bank * IRQ_PER_BANK + irqoffset); 759 generic_handle_irq(pin_irq); 760 } 761 chained_irq_exit(chip, desc); 762 } 763 } 764 765 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 766 const char *name) 767 { 768 struct sunxi_pinctrl_function *func = pctl->functions; 769 770 while (func->name) { 771 /* function already there */ 772 if (strcmp(func->name, name) == 0) { 773 func->ngroups++; 774 return -EEXIST; 775 } 776 func++; 777 } 778 779 func->name = name; 780 func->ngroups = 1; 781 782 pctl->nfunctions++; 783 784 return 0; 785 } 786 787 static int sunxi_pinctrl_build_state(struct platform_device *pdev) 788 { 789 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 790 int i; 791 792 pctl->ngroups = pctl->desc->npins; 793 794 /* Allocate groups */ 795 pctl->groups = devm_kzalloc(&pdev->dev, 796 pctl->ngroups * sizeof(*pctl->groups), 797 GFP_KERNEL); 798 if (!pctl->groups) 799 return -ENOMEM; 800 801 for (i = 0; i < pctl->desc->npins; i++) { 802 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 803 struct sunxi_pinctrl_group *group = pctl->groups + i; 804 805 group->name = pin->pin.name; 806 group->pin = pin->pin.number; 807 } 808 809 /* 810 * We suppose that we won't have any more functions than pins, 811 * we'll reallocate that later anyway 812 */ 813 pctl->functions = devm_kzalloc(&pdev->dev, 814 pctl->desc->npins * sizeof(*pctl->functions), 815 GFP_KERNEL); 816 if (!pctl->functions) 817 return -ENOMEM; 818 819 /* Count functions and their associated groups */ 820 for (i = 0; i < pctl->desc->npins; i++) { 821 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 822 struct sunxi_desc_function *func = pin->functions; 823 824 while (func->name) { 825 /* Create interrupt mapping while we're at it */ 826 if (!strcmp(func->name, "irq")) { 827 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; 828 pctl->irq_array[irqnum] = pin->pin.number; 829 } 830 831 sunxi_pinctrl_add_function(pctl, func->name); 832 func++; 833 } 834 } 835 836 pctl->functions = krealloc(pctl->functions, 837 pctl->nfunctions * sizeof(*pctl->functions), 838 GFP_KERNEL); 839 840 for (i = 0; i < pctl->desc->npins; i++) { 841 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 842 struct sunxi_desc_function *func = pin->functions; 843 844 while (func->name) { 845 struct sunxi_pinctrl_function *func_item; 846 const char **func_grp; 847 848 func_item = sunxi_pinctrl_find_function_by_name(pctl, 849 func->name); 850 if (!func_item) 851 return -EINVAL; 852 853 if (!func_item->groups) { 854 func_item->groups = 855 devm_kzalloc(&pdev->dev, 856 func_item->ngroups * sizeof(*func_item->groups), 857 GFP_KERNEL); 858 if (!func_item->groups) 859 return -ENOMEM; 860 } 861 862 func_grp = func_item->groups; 863 while (*func_grp) 864 func_grp++; 865 866 *func_grp = pin->pin.name; 867 func++; 868 } 869 } 870 871 return 0; 872 } 873 874 int sunxi_pinctrl_init(struct platform_device *pdev, 875 const struct sunxi_pinctrl_desc *desc) 876 { 877 struct device_node *node = pdev->dev.of_node; 878 struct pinctrl_desc *pctrl_desc; 879 struct pinctrl_pin_desc *pins; 880 struct sunxi_pinctrl *pctl; 881 struct resource *res; 882 int i, ret, last_pin; 883 struct clk *clk; 884 885 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 886 if (!pctl) 887 return -ENOMEM; 888 platform_set_drvdata(pdev, pctl); 889 890 spin_lock_init(&pctl->lock); 891 892 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 893 pctl->membase = devm_ioremap_resource(&pdev->dev, res); 894 if (IS_ERR(pctl->membase)) 895 return PTR_ERR(pctl->membase); 896 897 pctl->dev = &pdev->dev; 898 pctl->desc = desc; 899 900 pctl->irq_array = devm_kcalloc(&pdev->dev, 901 IRQ_PER_BANK * pctl->desc->irq_banks, 902 sizeof(*pctl->irq_array), 903 GFP_KERNEL); 904 if (!pctl->irq_array) 905 return -ENOMEM; 906 907 ret = sunxi_pinctrl_build_state(pdev); 908 if (ret) { 909 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 910 return ret; 911 } 912 913 pins = devm_kzalloc(&pdev->dev, 914 pctl->desc->npins * sizeof(*pins), 915 GFP_KERNEL); 916 if (!pins) 917 return -ENOMEM; 918 919 for (i = 0; i < pctl->desc->npins; i++) 920 pins[i] = pctl->desc->pins[i].pin; 921 922 pctrl_desc = devm_kzalloc(&pdev->dev, 923 sizeof(*pctrl_desc), 924 GFP_KERNEL); 925 if (!pctrl_desc) 926 return -ENOMEM; 927 928 pctrl_desc->name = dev_name(&pdev->dev); 929 pctrl_desc->owner = THIS_MODULE; 930 pctrl_desc->pins = pins; 931 pctrl_desc->npins = pctl->desc->npins; 932 pctrl_desc->confops = &sunxi_pconf_ops; 933 pctrl_desc->pctlops = &sunxi_pctrl_ops; 934 pctrl_desc->pmxops = &sunxi_pmx_ops; 935 936 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); 937 if (IS_ERR(pctl->pctl_dev)) { 938 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 939 return PTR_ERR(pctl->pctl_dev); 940 } 941 942 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 943 if (!pctl->chip) 944 return -ENOMEM; 945 946 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 947 pctl->chip->owner = THIS_MODULE; 948 pctl->chip->request = gpiochip_generic_request, 949 pctl->chip->free = gpiochip_generic_free, 950 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input, 951 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output, 952 pctl->chip->get = sunxi_pinctrl_gpio_get, 953 pctl->chip->set = sunxi_pinctrl_gpio_set, 954 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate, 955 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq, 956 pctl->chip->of_gpio_n_cells = 3, 957 pctl->chip->can_sleep = false, 958 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - 959 pctl->desc->pin_base; 960 pctl->chip->label = dev_name(&pdev->dev); 961 pctl->chip->parent = &pdev->dev; 962 pctl->chip->base = pctl->desc->pin_base; 963 964 ret = gpiochip_add_data(pctl->chip, pctl); 965 if (ret) 966 return ret; 967 968 for (i = 0; i < pctl->desc->npins; i++) { 969 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 970 971 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 972 pin->pin.number - pctl->desc->pin_base, 973 pin->pin.number, 1); 974 if (ret) 975 goto gpiochip_error; 976 } 977 978 clk = devm_clk_get(&pdev->dev, NULL); 979 if (IS_ERR(clk)) { 980 ret = PTR_ERR(clk); 981 goto gpiochip_error; 982 } 983 984 ret = clk_prepare_enable(clk); 985 if (ret) 986 goto gpiochip_error; 987 988 pctl->irq = devm_kcalloc(&pdev->dev, 989 pctl->desc->irq_banks, 990 sizeof(*pctl->irq), 991 GFP_KERNEL); 992 if (!pctl->irq) { 993 ret = -ENOMEM; 994 goto clk_error; 995 } 996 997 for (i = 0; i < pctl->desc->irq_banks; i++) { 998 pctl->irq[i] = platform_get_irq(pdev, i); 999 if (pctl->irq[i] < 0) { 1000 ret = pctl->irq[i]; 1001 goto clk_error; 1002 } 1003 } 1004 1005 pctl->domain = irq_domain_add_linear(node, 1006 pctl->desc->irq_banks * IRQ_PER_BANK, 1007 &sunxi_pinctrl_irq_domain_ops, 1008 pctl); 1009 if (!pctl->domain) { 1010 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 1011 ret = -ENOMEM; 1012 goto clk_error; 1013 } 1014 1015 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { 1016 int irqno = irq_create_mapping(pctl->domain, i); 1017 1018 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, 1019 handle_edge_irq); 1020 irq_set_chip_data(irqno, pctl); 1021 } 1022 1023 for (i = 0; i < pctl->desc->irq_banks; i++) { 1024 /* Mask and clear all IRQs before registering a handler */ 1025 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i, 1026 pctl->desc->irq_bank_base)); 1027 writel(0xffffffff, 1028 pctl->membase + sunxi_irq_status_reg_from_bank(i, 1029 pctl->desc->irq_bank_base)); 1030 1031 irq_set_chained_handler_and_data(pctl->irq[i], 1032 sunxi_pinctrl_irq_handler, 1033 pctl); 1034 } 1035 1036 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1037 1038 return 0; 1039 1040 clk_error: 1041 clk_disable_unprepare(clk); 1042 gpiochip_error: 1043 gpiochip_remove(pctl->chip); 1044 return ret; 1045 } 1046