1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/io.h> 14 #include <linux/clk.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/irqdomain.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/export.h> 19 #include <linux/of.h> 20 #include <linux/of_clk.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/pinctrl/machine.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinconf-generic.h> 28 #include <linux/pinctrl/pinmux.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/platform_device.h> 31 #include <linux/slab.h> 32 33 #include <dt-bindings/pinctrl/sun4i-a10.h> 34 35 #include "../core.h" 36 #include "pinctrl-sunxi.h" 37 38 static struct irq_chip sunxi_pinctrl_edge_irq_chip; 39 static struct irq_chip sunxi_pinctrl_level_irq_chip; 40 41 static struct sunxi_pinctrl_group * 42 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 43 { 44 int i; 45 46 for (i = 0; i < pctl->ngroups; i++) { 47 struct sunxi_pinctrl_group *grp = pctl->groups + i; 48 49 if (!strcmp(grp->name, group)) 50 return grp; 51 } 52 53 return NULL; 54 } 55 56 static struct sunxi_pinctrl_function * 57 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 58 const char *name) 59 { 60 struct sunxi_pinctrl_function *func = pctl->functions; 61 int i; 62 63 for (i = 0; i < pctl->nfunctions; i++) { 64 if (!func[i].name) 65 break; 66 67 if (!strcmp(func[i].name, name)) 68 return func + i; 69 } 70 71 return NULL; 72 } 73 74 static struct sunxi_desc_function * 75 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 76 const char *pin_name, 77 const char *func_name) 78 { 79 int i; 80 81 for (i = 0; i < pctl->desc->npins; i++) { 82 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 83 84 if (!strcmp(pin->pin.name, pin_name)) { 85 struct sunxi_desc_function *func = pin->functions; 86 87 while (func->name) { 88 if (!strcmp(func->name, func_name) && 89 (!func->variant || 90 func->variant & pctl->variant)) 91 return func; 92 93 func++; 94 } 95 } 96 } 97 98 return NULL; 99 } 100 101 static struct sunxi_desc_function * 102 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, 103 const u16 pin_num, 104 const char *func_name) 105 { 106 int i; 107 108 for (i = 0; i < pctl->desc->npins; i++) { 109 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 110 111 if (pin->pin.number == pin_num) { 112 struct sunxi_desc_function *func = pin->functions; 113 114 while (func->name) { 115 if (!strcmp(func->name, func_name)) 116 return func; 117 118 func++; 119 } 120 } 121 } 122 123 return NULL; 124 } 125 126 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 127 { 128 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 129 130 return pctl->ngroups; 131 } 132 133 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 134 unsigned group) 135 { 136 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 137 138 return pctl->groups[group].name; 139 } 140 141 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 142 unsigned group, 143 const unsigned **pins, 144 unsigned *num_pins) 145 { 146 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 147 148 *pins = (unsigned *)&pctl->groups[group].pin; 149 *num_pins = 1; 150 151 return 0; 152 } 153 154 static bool sunxi_pctrl_has_bias_prop(struct device_node *node) 155 { 156 return of_find_property(node, "bias-pull-up", NULL) || 157 of_find_property(node, "bias-pull-down", NULL) || 158 of_find_property(node, "bias-disable", NULL) || 159 of_find_property(node, "allwinner,pull", NULL); 160 } 161 162 static bool sunxi_pctrl_has_drive_prop(struct device_node *node) 163 { 164 return of_find_property(node, "drive-strength", NULL) || 165 of_find_property(node, "allwinner,drive", NULL); 166 } 167 168 static int sunxi_pctrl_parse_bias_prop(struct device_node *node) 169 { 170 u32 val; 171 172 /* Try the new style binding */ 173 if (of_find_property(node, "bias-pull-up", NULL)) 174 return PIN_CONFIG_BIAS_PULL_UP; 175 176 if (of_find_property(node, "bias-pull-down", NULL)) 177 return PIN_CONFIG_BIAS_PULL_DOWN; 178 179 if (of_find_property(node, "bias-disable", NULL)) 180 return PIN_CONFIG_BIAS_DISABLE; 181 182 /* And fall back to the old binding */ 183 if (of_property_read_u32(node, "allwinner,pull", &val)) 184 return -EINVAL; 185 186 switch (val) { 187 case SUN4I_PINCTRL_NO_PULL: 188 return PIN_CONFIG_BIAS_DISABLE; 189 case SUN4I_PINCTRL_PULL_UP: 190 return PIN_CONFIG_BIAS_PULL_UP; 191 case SUN4I_PINCTRL_PULL_DOWN: 192 return PIN_CONFIG_BIAS_PULL_DOWN; 193 } 194 195 return -EINVAL; 196 } 197 198 static int sunxi_pctrl_parse_drive_prop(struct device_node *node) 199 { 200 u32 val; 201 202 /* Try the new style binding */ 203 if (!of_property_read_u32(node, "drive-strength", &val)) { 204 /* We can't go below 10mA ... */ 205 if (val < 10) 206 return -EINVAL; 207 208 /* ... and only up to 40 mA ... */ 209 if (val > 40) 210 val = 40; 211 212 /* by steps of 10 mA */ 213 return rounddown(val, 10); 214 } 215 216 /* And then fall back to the old binding */ 217 if (of_property_read_u32(node, "allwinner,drive", &val)) 218 return -EINVAL; 219 220 return (val + 1) * 10; 221 } 222 223 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node) 224 { 225 const char *function; 226 int ret; 227 228 /* Try the generic binding */ 229 ret = of_property_read_string(node, "function", &function); 230 if (!ret) 231 return function; 232 233 /* And fall back to our legacy one */ 234 ret = of_property_read_string(node, "allwinner,function", &function); 235 if (!ret) 236 return function; 237 238 return NULL; 239 } 240 241 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node, 242 int *npins) 243 { 244 int count; 245 246 /* Try the generic binding */ 247 count = of_property_count_strings(node, "pins"); 248 if (count > 0) { 249 *npins = count; 250 return "pins"; 251 } 252 253 /* And fall back to our legacy one */ 254 count = of_property_count_strings(node, "allwinner,pins"); 255 if (count > 0) { 256 *npins = count; 257 return "allwinner,pins"; 258 } 259 260 return NULL; 261 } 262 263 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node, 264 unsigned int *len) 265 { 266 unsigned long *pinconfig; 267 unsigned int configlen = 0, idx = 0; 268 int ret; 269 270 if (sunxi_pctrl_has_drive_prop(node)) 271 configlen++; 272 if (sunxi_pctrl_has_bias_prop(node)) 273 configlen++; 274 275 /* 276 * If we don't have any configuration, bail out 277 */ 278 if (!configlen) 279 return NULL; 280 281 pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL); 282 if (!pinconfig) 283 return ERR_PTR(-ENOMEM); 284 285 if (sunxi_pctrl_has_drive_prop(node)) { 286 int drive = sunxi_pctrl_parse_drive_prop(node); 287 if (drive < 0) { 288 ret = drive; 289 goto err_free; 290 } 291 292 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 293 drive); 294 } 295 296 if (sunxi_pctrl_has_bias_prop(node)) { 297 int pull = sunxi_pctrl_parse_bias_prop(node); 298 int arg = 0; 299 if (pull < 0) { 300 ret = pull; 301 goto err_free; 302 } 303 304 if (pull != PIN_CONFIG_BIAS_DISABLE) 305 arg = 1; /* hardware uses weak pull resistors */ 306 307 pinconfig[idx++] = pinconf_to_config_packed(pull, arg); 308 } 309 310 311 *len = configlen; 312 return pinconfig; 313 314 err_free: 315 kfree(pinconfig); 316 return ERR_PTR(ret); 317 } 318 319 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 320 struct device_node *node, 321 struct pinctrl_map **map, 322 unsigned *num_maps) 323 { 324 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 325 unsigned long *pinconfig; 326 struct property *prop; 327 const char *function, *pin_prop; 328 const char *group; 329 int ret, npins, nmaps, configlen = 0, i = 0; 330 331 *map = NULL; 332 *num_maps = 0; 333 334 function = sunxi_pctrl_parse_function_prop(node); 335 if (!function) { 336 dev_err(pctl->dev, "missing function property in node %pOFn\n", 337 node); 338 return -EINVAL; 339 } 340 341 pin_prop = sunxi_pctrl_find_pins_prop(node, &npins); 342 if (!pin_prop) { 343 dev_err(pctl->dev, "missing pins property in node %pOFn\n", 344 node); 345 return -EINVAL; 346 } 347 348 /* 349 * We have two maps for each pin: one for the function, one 350 * for the configuration (bias, strength, etc). 351 * 352 * We might be slightly overshooting, since we might not have 353 * any configuration. 354 */ 355 nmaps = npins * 2; 356 *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL); 357 if (!*map) 358 return -ENOMEM; 359 360 pinconfig = sunxi_pctrl_build_pin_config(node, &configlen); 361 if (IS_ERR(pinconfig)) { 362 ret = PTR_ERR(pinconfig); 363 goto err_free_map; 364 } 365 366 of_property_for_each_string(node, pin_prop, prop, group) { 367 struct sunxi_pinctrl_group *grp = 368 sunxi_pinctrl_find_group_by_name(pctl, group); 369 370 if (!grp) { 371 dev_err(pctl->dev, "unknown pin %s", group); 372 continue; 373 } 374 375 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 376 grp->name, 377 function)) { 378 dev_err(pctl->dev, "unsupported function %s on pin %s", 379 function, group); 380 continue; 381 } 382 383 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 384 (*map)[i].data.mux.group = group; 385 (*map)[i].data.mux.function = function; 386 387 i++; 388 389 if (pinconfig) { 390 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 391 (*map)[i].data.configs.group_or_pin = group; 392 (*map)[i].data.configs.configs = pinconfig; 393 (*map)[i].data.configs.num_configs = configlen; 394 i++; 395 } 396 } 397 398 *num_maps = i; 399 400 /* 401 * We know have the number of maps we need, we can resize our 402 * map array 403 */ 404 *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL); 405 if (!*map) 406 return -ENOMEM; 407 408 return 0; 409 410 err_free_map: 411 kfree(*map); 412 *map = NULL; 413 return ret; 414 } 415 416 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 417 struct pinctrl_map *map, 418 unsigned num_maps) 419 { 420 int i; 421 422 /* pin config is never in the first map */ 423 for (i = 1; i < num_maps; i++) { 424 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP) 425 continue; 426 427 /* 428 * All the maps share the same pin config, 429 * free only the first one we find. 430 */ 431 kfree(map[i].data.configs.configs); 432 break; 433 } 434 435 kfree(map); 436 } 437 438 static const struct pinctrl_ops sunxi_pctrl_ops = { 439 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 440 .dt_free_map = sunxi_pctrl_dt_free_map, 441 .get_groups_count = sunxi_pctrl_get_groups_count, 442 .get_group_name = sunxi_pctrl_get_group_name, 443 .get_group_pins = sunxi_pctrl_get_group_pins, 444 }; 445 446 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param, 447 u32 *offset, u32 *shift, u32 *mask) 448 { 449 switch (param) { 450 case PIN_CONFIG_DRIVE_STRENGTH: 451 *offset = sunxi_dlevel_reg(pin); 452 *shift = sunxi_dlevel_offset(pin); 453 *mask = DLEVEL_PINS_MASK; 454 break; 455 456 case PIN_CONFIG_BIAS_PULL_UP: 457 case PIN_CONFIG_BIAS_PULL_DOWN: 458 case PIN_CONFIG_BIAS_DISABLE: 459 *offset = sunxi_pull_reg(pin); 460 *shift = sunxi_pull_offset(pin); 461 *mask = PULL_PINS_MASK; 462 break; 463 464 default: 465 return -ENOTSUPP; 466 } 467 468 return 0; 469 } 470 471 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin, 472 unsigned long *config) 473 { 474 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 475 enum pin_config_param param = pinconf_to_config_param(*config); 476 u32 offset, shift, mask, val; 477 u16 arg; 478 int ret; 479 480 pin -= pctl->desc->pin_base; 481 482 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); 483 if (ret < 0) 484 return ret; 485 486 val = (readl(pctl->membase + offset) >> shift) & mask; 487 488 switch (pinconf_to_config_param(*config)) { 489 case PIN_CONFIG_DRIVE_STRENGTH: 490 arg = (val + 1) * 10; 491 break; 492 493 case PIN_CONFIG_BIAS_PULL_UP: 494 if (val != SUN4I_PINCTRL_PULL_UP) 495 return -EINVAL; 496 arg = 1; /* hardware is weak pull-up */ 497 break; 498 499 case PIN_CONFIG_BIAS_PULL_DOWN: 500 if (val != SUN4I_PINCTRL_PULL_DOWN) 501 return -EINVAL; 502 arg = 1; /* hardware is weak pull-down */ 503 break; 504 505 case PIN_CONFIG_BIAS_DISABLE: 506 if (val != SUN4I_PINCTRL_NO_PULL) 507 return -EINVAL; 508 arg = 0; 509 break; 510 511 default: 512 /* sunxi_pconf_reg should catch anything unsupported */ 513 WARN_ON(1); 514 return -ENOTSUPP; 515 } 516 517 *config = pinconf_to_config_packed(param, arg); 518 519 return 0; 520 } 521 522 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 523 unsigned group, 524 unsigned long *config) 525 { 526 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 527 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 528 529 /* We only support 1 pin per group. Chain it to the pin callback */ 530 return sunxi_pconf_get(pctldev, g->pin, config); 531 } 532 533 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, 534 unsigned group, 535 unsigned long *configs, 536 unsigned num_configs) 537 { 538 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 539 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 540 unsigned pin = g->pin - pctl->desc->pin_base; 541 int i; 542 543 for (i = 0; i < num_configs; i++) { 544 enum pin_config_param param; 545 unsigned long flags; 546 u32 offset, shift, mask, reg; 547 u32 arg, val; 548 int ret; 549 550 param = pinconf_to_config_param(configs[i]); 551 arg = pinconf_to_config_argument(configs[i]); 552 553 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); 554 if (ret < 0) 555 return ret; 556 557 switch (param) { 558 case PIN_CONFIG_DRIVE_STRENGTH: 559 if (arg < 10 || arg > 40) 560 return -EINVAL; 561 /* 562 * We convert from mA to what the register expects: 563 * 0: 10mA 564 * 1: 20mA 565 * 2: 30mA 566 * 3: 40mA 567 */ 568 val = arg / 10 - 1; 569 break; 570 case PIN_CONFIG_BIAS_DISABLE: 571 val = 0; 572 break; 573 case PIN_CONFIG_BIAS_PULL_UP: 574 if (arg == 0) 575 return -EINVAL; 576 val = 1; 577 break; 578 case PIN_CONFIG_BIAS_PULL_DOWN: 579 if (arg == 0) 580 return -EINVAL; 581 val = 2; 582 break; 583 default: 584 /* sunxi_pconf_reg should catch anything unsupported */ 585 WARN_ON(1); 586 return -ENOTSUPP; 587 } 588 589 raw_spin_lock_irqsave(&pctl->lock, flags); 590 reg = readl(pctl->membase + offset); 591 reg &= ~(mask << shift); 592 writel(reg | val << shift, pctl->membase + offset); 593 raw_spin_unlock_irqrestore(&pctl->lock, flags); 594 } /* for each config */ 595 596 return 0; 597 } 598 599 static const struct pinconf_ops sunxi_pconf_ops = { 600 .is_generic = true, 601 .pin_config_get = sunxi_pconf_get, 602 .pin_config_group_get = sunxi_pconf_group_get, 603 .pin_config_group_set = sunxi_pconf_group_set, 604 }; 605 606 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, 607 unsigned pin, 608 struct regulator *supply) 609 { 610 u32 val, reg; 611 int uV; 612 613 if (!pctl->desc->has_io_bias_cfg) 614 return 0; 615 616 uV = regulator_get_voltage(supply); 617 if (uV < 0) 618 return uV; 619 620 /* Might be dummy regulator with no voltage set */ 621 if (uV == 0) 622 return 0; 623 624 /* Configured value must be equal or greater to actual voltage */ 625 if (uV <= 1800000) 626 val = 0x0; /* 1.8V */ 627 else if (uV <= 2500000) 628 val = 0x6; /* 2.5V */ 629 else if (uV <= 2800000) 630 val = 0x9; /* 2.8V */ 631 else if (uV <= 3000000) 632 val = 0xA; /* 3.0V */ 633 else 634 val = 0xD; /* 3.3V */ 635 636 pin -= pctl->desc->pin_base; 637 638 reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); 639 reg &= ~IO_BIAS_MASK; 640 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); 641 642 return 0; 643 } 644 645 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 646 { 647 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 648 649 return pctl->nfunctions; 650 } 651 652 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 653 unsigned function) 654 { 655 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 656 657 return pctl->functions[function].name; 658 } 659 660 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 661 unsigned function, 662 const char * const **groups, 663 unsigned * const num_groups) 664 { 665 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 666 667 *groups = pctl->functions[function].groups; 668 *num_groups = pctl->functions[function].ngroups; 669 670 return 0; 671 } 672 673 static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 674 unsigned pin, 675 u8 config) 676 { 677 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 678 unsigned long flags; 679 u32 val, mask; 680 681 raw_spin_lock_irqsave(&pctl->lock, flags); 682 683 pin -= pctl->desc->pin_base; 684 val = readl(pctl->membase + sunxi_mux_reg(pin)); 685 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 686 writel((val & ~mask) | config << sunxi_mux_offset(pin), 687 pctl->membase + sunxi_mux_reg(pin)); 688 689 raw_spin_unlock_irqrestore(&pctl->lock, flags); 690 } 691 692 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, 693 unsigned function, 694 unsigned group) 695 { 696 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 697 struct sunxi_pinctrl_group *g = pctl->groups + group; 698 struct sunxi_pinctrl_function *func = pctl->functions + function; 699 struct sunxi_desc_function *desc = 700 sunxi_pinctrl_desc_find_function_by_name(pctl, 701 g->name, 702 func->name); 703 704 if (!desc) 705 return -EINVAL; 706 707 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 708 709 return 0; 710 } 711 712 static int 713 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 714 struct pinctrl_gpio_range *range, 715 unsigned offset, 716 bool input) 717 { 718 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 719 struct sunxi_desc_function *desc; 720 const char *func; 721 722 if (input) 723 func = "gpio_in"; 724 else 725 func = "gpio_out"; 726 727 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); 728 if (!desc) 729 return -EINVAL; 730 731 sunxi_pmx_set(pctldev, offset, desc->muxval); 732 733 return 0; 734 } 735 736 static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset) 737 { 738 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 739 unsigned short bank = offset / PINS_PER_BANK; 740 unsigned short bank_offset = bank - pctl->desc->pin_base / 741 PINS_PER_BANK; 742 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; 743 struct regulator *reg = s_reg->regulator; 744 char supply[16]; 745 int ret; 746 747 if (reg) { 748 refcount_inc(&s_reg->refcount); 749 return 0; 750 } 751 752 snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank); 753 reg = regulator_get(pctl->dev, supply); 754 if (IS_ERR(reg)) { 755 dev_err(pctl->dev, "Couldn't get bank P%c regulator\n", 756 'A' + bank); 757 return PTR_ERR(reg); 758 } 759 760 ret = regulator_enable(reg); 761 if (ret) { 762 dev_err(pctl->dev, 763 "Couldn't enable bank P%c regulator\n", 'A' + bank); 764 goto out; 765 } 766 767 sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg); 768 769 s_reg->regulator = reg; 770 refcount_set(&s_reg->refcount, 1); 771 772 return 0; 773 774 out: 775 regulator_put(s_reg->regulator); 776 777 return ret; 778 } 779 780 static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset) 781 { 782 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 783 unsigned short bank = offset / PINS_PER_BANK; 784 unsigned short bank_offset = bank - pctl->desc->pin_base / 785 PINS_PER_BANK; 786 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; 787 788 if (!refcount_dec_and_test(&s_reg->refcount)) 789 return 0; 790 791 regulator_disable(s_reg->regulator); 792 regulator_put(s_reg->regulator); 793 s_reg->regulator = NULL; 794 795 return 0; 796 } 797 798 static const struct pinmux_ops sunxi_pmx_ops = { 799 .get_functions_count = sunxi_pmx_get_funcs_cnt, 800 .get_function_name = sunxi_pmx_get_func_name, 801 .get_function_groups = sunxi_pmx_get_func_groups, 802 .set_mux = sunxi_pmx_set_mux, 803 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 804 .request = sunxi_pmx_request, 805 .free = sunxi_pmx_free, 806 .strict = true, 807 }; 808 809 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 810 unsigned offset) 811 { 812 return pinctrl_gpio_direction_input(chip->base + offset); 813 } 814 815 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 816 { 817 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 818 u32 reg = sunxi_data_reg(offset); 819 u8 index = sunxi_data_offset(offset); 820 bool set_mux = pctl->desc->irq_read_needs_mux && 821 gpiochip_line_is_irq(chip, offset); 822 u32 pin = offset + chip->base; 823 u32 val; 824 825 if (set_mux) 826 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); 827 828 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; 829 830 if (set_mux) 831 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); 832 833 return !!val; 834 } 835 836 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 837 unsigned offset, int value) 838 { 839 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 840 u32 reg = sunxi_data_reg(offset); 841 u8 index = sunxi_data_offset(offset); 842 unsigned long flags; 843 u32 regval; 844 845 raw_spin_lock_irqsave(&pctl->lock, flags); 846 847 regval = readl(pctl->membase + reg); 848 849 if (value) 850 regval |= BIT(index); 851 else 852 regval &= ~(BIT(index)); 853 854 writel(regval, pctl->membase + reg); 855 856 raw_spin_unlock_irqrestore(&pctl->lock, flags); 857 } 858 859 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 860 unsigned offset, int value) 861 { 862 sunxi_pinctrl_gpio_set(chip, offset, value); 863 return pinctrl_gpio_direction_output(chip->base + offset); 864 } 865 866 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 867 const struct of_phandle_args *gpiospec, 868 u32 *flags) 869 { 870 int pin, base; 871 872 base = PINS_PER_BANK * gpiospec->args[0]; 873 pin = base + gpiospec->args[1]; 874 875 if (pin > gc->ngpio) 876 return -EINVAL; 877 878 if (flags) 879 *flags = gpiospec->args[2]; 880 881 return pin; 882 } 883 884 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 885 { 886 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 887 struct sunxi_desc_function *desc; 888 unsigned pinnum = pctl->desc->pin_base + offset; 889 unsigned irqnum; 890 891 if (offset >= chip->ngpio) 892 return -ENXIO; 893 894 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq"); 895 if (!desc) 896 return -EINVAL; 897 898 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum; 899 900 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n", 901 chip->label, offset + chip->base, irqnum); 902 903 return irq_find_mapping(pctl->domain, irqnum); 904 } 905 906 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) 907 { 908 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 909 struct sunxi_desc_function *func; 910 int ret; 911 912 func = sunxi_pinctrl_desc_find_function_by_pin(pctl, 913 pctl->irq_array[d->hwirq], "irq"); 914 if (!func) 915 return -EINVAL; 916 917 ret = gpiochip_lock_as_irq(pctl->chip, 918 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 919 if (ret) { 920 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 921 irqd_to_hwirq(d)); 922 return ret; 923 } 924 925 /* Change muxing to INT mode */ 926 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); 927 928 return 0; 929 } 930 931 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) 932 { 933 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 934 935 gpiochip_unlock_as_irq(pctl->chip, 936 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 937 } 938 939 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) 940 { 941 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 942 u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq); 943 u8 index = sunxi_irq_cfg_offset(d->hwirq); 944 unsigned long flags; 945 u32 regval; 946 u8 mode; 947 948 switch (type) { 949 case IRQ_TYPE_EDGE_RISING: 950 mode = IRQ_EDGE_RISING; 951 break; 952 case IRQ_TYPE_EDGE_FALLING: 953 mode = IRQ_EDGE_FALLING; 954 break; 955 case IRQ_TYPE_EDGE_BOTH: 956 mode = IRQ_EDGE_BOTH; 957 break; 958 case IRQ_TYPE_LEVEL_HIGH: 959 mode = IRQ_LEVEL_HIGH; 960 break; 961 case IRQ_TYPE_LEVEL_LOW: 962 mode = IRQ_LEVEL_LOW; 963 break; 964 default: 965 return -EINVAL; 966 } 967 968 raw_spin_lock_irqsave(&pctl->lock, flags); 969 970 if (type & IRQ_TYPE_LEVEL_MASK) 971 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip, 972 handle_fasteoi_irq, NULL); 973 else 974 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip, 975 handle_edge_irq, NULL); 976 977 regval = readl(pctl->membase + reg); 978 regval &= ~(IRQ_CFG_IRQ_MASK << index); 979 writel(regval | (mode << index), pctl->membase + reg); 980 981 raw_spin_unlock_irqrestore(&pctl->lock, flags); 982 983 return 0; 984 } 985 986 static void sunxi_pinctrl_irq_ack(struct irq_data *d) 987 { 988 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 989 u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq); 990 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 991 992 /* Clear the IRQ */ 993 writel(1 << status_idx, pctl->membase + status_reg); 994 } 995 996 static void sunxi_pinctrl_irq_mask(struct irq_data *d) 997 { 998 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 999 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); 1000 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 1001 unsigned long flags; 1002 u32 val; 1003 1004 raw_spin_lock_irqsave(&pctl->lock, flags); 1005 1006 /* Mask the IRQ */ 1007 val = readl(pctl->membase + reg); 1008 writel(val & ~(1 << idx), pctl->membase + reg); 1009 1010 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1011 } 1012 1013 static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 1014 { 1015 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1016 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); 1017 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 1018 unsigned long flags; 1019 u32 val; 1020 1021 raw_spin_lock_irqsave(&pctl->lock, flags); 1022 1023 /* Unmask the IRQ */ 1024 val = readl(pctl->membase + reg); 1025 writel(val | (1 << idx), pctl->membase + reg); 1026 1027 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1028 } 1029 1030 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) 1031 { 1032 sunxi_pinctrl_irq_ack(d); 1033 sunxi_pinctrl_irq_unmask(d); 1034 } 1035 1036 static struct irq_chip sunxi_pinctrl_edge_irq_chip = { 1037 .name = "sunxi_pio_edge", 1038 .irq_ack = sunxi_pinctrl_irq_ack, 1039 .irq_mask = sunxi_pinctrl_irq_mask, 1040 .irq_unmask = sunxi_pinctrl_irq_unmask, 1041 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 1042 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 1043 .irq_set_type = sunxi_pinctrl_irq_set_type, 1044 .flags = IRQCHIP_SKIP_SET_WAKE, 1045 }; 1046 1047 static struct irq_chip sunxi_pinctrl_level_irq_chip = { 1048 .name = "sunxi_pio_level", 1049 .irq_eoi = sunxi_pinctrl_irq_ack, 1050 .irq_mask = sunxi_pinctrl_irq_mask, 1051 .irq_unmask = sunxi_pinctrl_irq_unmask, 1052 /* Define irq_enable / disable to avoid spurious irqs for drivers 1053 * using these to suppress irqs while they clear the irq source */ 1054 .irq_enable = sunxi_pinctrl_irq_ack_unmask, 1055 .irq_disable = sunxi_pinctrl_irq_mask, 1056 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 1057 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 1058 .irq_set_type = sunxi_pinctrl_irq_set_type, 1059 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED | 1060 IRQCHIP_EOI_IF_HANDLED, 1061 }; 1062 1063 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, 1064 struct device_node *node, 1065 const u32 *intspec, 1066 unsigned int intsize, 1067 unsigned long *out_hwirq, 1068 unsigned int *out_type) 1069 { 1070 struct sunxi_pinctrl *pctl = d->host_data; 1071 struct sunxi_desc_function *desc; 1072 int pin, base; 1073 1074 if (intsize < 3) 1075 return -EINVAL; 1076 1077 base = PINS_PER_BANK * intspec[0]; 1078 pin = pctl->desc->pin_base + base + intspec[1]; 1079 1080 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); 1081 if (!desc) 1082 return -EINVAL; 1083 1084 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum; 1085 *out_type = intspec[2]; 1086 1087 return 0; 1088 } 1089 1090 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = { 1091 .xlate = sunxi_pinctrl_irq_of_xlate, 1092 }; 1093 1094 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) 1095 { 1096 unsigned int irq = irq_desc_get_irq(desc); 1097 struct irq_chip *chip = irq_desc_get_chip(desc); 1098 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc); 1099 unsigned long bank, reg, val; 1100 1101 for (bank = 0; bank < pctl->desc->irq_banks; bank++) 1102 if (irq == pctl->irq[bank]) 1103 break; 1104 1105 if (bank == pctl->desc->irq_banks) 1106 return; 1107 1108 reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); 1109 val = readl(pctl->membase + reg); 1110 1111 if (val) { 1112 int irqoffset; 1113 1114 chained_irq_enter(chip, desc); 1115 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) { 1116 int pin_irq = irq_find_mapping(pctl->domain, 1117 bank * IRQ_PER_BANK + irqoffset); 1118 generic_handle_irq(pin_irq); 1119 } 1120 chained_irq_exit(chip, desc); 1121 } 1122 } 1123 1124 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 1125 const char *name) 1126 { 1127 struct sunxi_pinctrl_function *func = pctl->functions; 1128 1129 while (func->name) { 1130 /* function already there */ 1131 if (strcmp(func->name, name) == 0) { 1132 func->ngroups++; 1133 return -EEXIST; 1134 } 1135 func++; 1136 } 1137 1138 func->name = name; 1139 func->ngroups = 1; 1140 1141 pctl->nfunctions++; 1142 1143 return 0; 1144 } 1145 1146 static int sunxi_pinctrl_build_state(struct platform_device *pdev) 1147 { 1148 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 1149 void *ptr; 1150 int i; 1151 1152 /* 1153 * Allocate groups 1154 * 1155 * We assume that the number of groups is the number of pins 1156 * given in the data array. 1157 1158 * This will not always be true, since some pins might not be 1159 * available in the current variant, but fortunately for us, 1160 * this means that the number of pins is the maximum group 1161 * number we will ever see. 1162 */ 1163 pctl->groups = devm_kcalloc(&pdev->dev, 1164 pctl->desc->npins, sizeof(*pctl->groups), 1165 GFP_KERNEL); 1166 if (!pctl->groups) 1167 return -ENOMEM; 1168 1169 for (i = 0; i < pctl->desc->npins; i++) { 1170 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1171 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups; 1172 1173 if (pin->variant && !(pctl->variant & pin->variant)) 1174 continue; 1175 1176 group->name = pin->pin.name; 1177 group->pin = pin->pin.number; 1178 1179 /* And now we count the actual number of pins / groups */ 1180 pctl->ngroups++; 1181 } 1182 1183 /* 1184 * We suppose that we won't have any more functions than pins, 1185 * we'll reallocate that later anyway 1186 */ 1187 pctl->functions = kcalloc(pctl->ngroups, 1188 sizeof(*pctl->functions), 1189 GFP_KERNEL); 1190 if (!pctl->functions) 1191 return -ENOMEM; 1192 1193 /* Count functions and their associated groups */ 1194 for (i = 0; i < pctl->desc->npins; i++) { 1195 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1196 struct sunxi_desc_function *func; 1197 1198 if (pin->variant && !(pctl->variant & pin->variant)) 1199 continue; 1200 1201 for (func = pin->functions; func->name; func++) { 1202 if (func->variant && !(pctl->variant & func->variant)) 1203 continue; 1204 1205 /* Create interrupt mapping while we're at it */ 1206 if (!strcmp(func->name, "irq")) { 1207 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; 1208 pctl->irq_array[irqnum] = pin->pin.number; 1209 } 1210 1211 sunxi_pinctrl_add_function(pctl, func->name); 1212 } 1213 } 1214 1215 /* And now allocated and fill the array for real */ 1216 ptr = krealloc(pctl->functions, 1217 pctl->nfunctions * sizeof(*pctl->functions), 1218 GFP_KERNEL); 1219 if (!ptr) { 1220 kfree(pctl->functions); 1221 pctl->functions = NULL; 1222 return -ENOMEM; 1223 } 1224 pctl->functions = ptr; 1225 1226 for (i = 0; i < pctl->desc->npins; i++) { 1227 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1228 struct sunxi_desc_function *func; 1229 1230 if (pin->variant && !(pctl->variant & pin->variant)) 1231 continue; 1232 1233 for (func = pin->functions; func->name; func++) { 1234 struct sunxi_pinctrl_function *func_item; 1235 const char **func_grp; 1236 1237 if (func->variant && !(pctl->variant & func->variant)) 1238 continue; 1239 1240 func_item = sunxi_pinctrl_find_function_by_name(pctl, 1241 func->name); 1242 if (!func_item) { 1243 kfree(pctl->functions); 1244 return -EINVAL; 1245 } 1246 1247 if (!func_item->groups) { 1248 func_item->groups = 1249 devm_kcalloc(&pdev->dev, 1250 func_item->ngroups, 1251 sizeof(*func_item->groups), 1252 GFP_KERNEL); 1253 if (!func_item->groups) { 1254 kfree(pctl->functions); 1255 return -ENOMEM; 1256 } 1257 } 1258 1259 func_grp = func_item->groups; 1260 while (*func_grp) 1261 func_grp++; 1262 1263 *func_grp = pin->pin.name; 1264 } 1265 } 1266 1267 return 0; 1268 } 1269 1270 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff) 1271 { 1272 unsigned long clock = clk_get_rate(clk); 1273 unsigned int best_diff, best_div; 1274 int i; 1275 1276 best_diff = abs(freq - clock); 1277 best_div = 0; 1278 1279 for (i = 1; i < 8; i++) { 1280 int cur_diff = abs(freq - (clock >> i)); 1281 1282 if (cur_diff < best_diff) { 1283 best_diff = cur_diff; 1284 best_div = i; 1285 } 1286 } 1287 1288 *diff = best_diff; 1289 return best_div; 1290 } 1291 1292 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, 1293 struct device_node *node) 1294 { 1295 unsigned int hosc_diff, losc_diff; 1296 unsigned int hosc_div, losc_div; 1297 struct clk *hosc, *losc; 1298 u8 div, src; 1299 int i, ret; 1300 1301 /* Deal with old DTs that didn't have the oscillators */ 1302 if (of_clk_get_parent_count(node) != 3) 1303 return 0; 1304 1305 /* If we don't have any setup, bail out */ 1306 if (!of_find_property(node, "input-debounce", NULL)) 1307 return 0; 1308 1309 losc = devm_clk_get(pctl->dev, "losc"); 1310 if (IS_ERR(losc)) 1311 return PTR_ERR(losc); 1312 1313 hosc = devm_clk_get(pctl->dev, "hosc"); 1314 if (IS_ERR(hosc)) 1315 return PTR_ERR(hosc); 1316 1317 for (i = 0; i < pctl->desc->irq_banks; i++) { 1318 unsigned long debounce_freq; 1319 u32 debounce; 1320 1321 ret = of_property_read_u32_index(node, "input-debounce", 1322 i, &debounce); 1323 if (ret) 1324 return ret; 1325 1326 if (!debounce) 1327 continue; 1328 1329 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce); 1330 losc_div = sunxi_pinctrl_get_debounce_div(losc, 1331 debounce_freq, 1332 &losc_diff); 1333 1334 hosc_div = sunxi_pinctrl_get_debounce_div(hosc, 1335 debounce_freq, 1336 &hosc_diff); 1337 1338 if (hosc_diff < losc_diff) { 1339 div = hosc_div; 1340 src = 1; 1341 } else { 1342 div = losc_div; 1343 src = 0; 1344 } 1345 1346 writel(src | div << 4, 1347 pctl->membase + 1348 sunxi_irq_debounce_reg_from_bank(pctl->desc, i)); 1349 } 1350 1351 return 0; 1352 } 1353 1354 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, 1355 const struct sunxi_pinctrl_desc *desc, 1356 unsigned long variant) 1357 { 1358 struct device_node *node = pdev->dev.of_node; 1359 struct pinctrl_desc *pctrl_desc; 1360 struct pinctrl_pin_desc *pins; 1361 struct sunxi_pinctrl *pctl; 1362 struct pinmux_ops *pmxops; 1363 struct resource *res; 1364 int i, ret, last_pin, pin_idx; 1365 struct clk *clk; 1366 1367 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1368 if (!pctl) 1369 return -ENOMEM; 1370 platform_set_drvdata(pdev, pctl); 1371 1372 raw_spin_lock_init(&pctl->lock); 1373 1374 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1375 pctl->membase = devm_ioremap_resource(&pdev->dev, res); 1376 if (IS_ERR(pctl->membase)) 1377 return PTR_ERR(pctl->membase); 1378 1379 pctl->dev = &pdev->dev; 1380 pctl->desc = desc; 1381 pctl->variant = variant; 1382 1383 pctl->irq_array = devm_kcalloc(&pdev->dev, 1384 IRQ_PER_BANK * pctl->desc->irq_banks, 1385 sizeof(*pctl->irq_array), 1386 GFP_KERNEL); 1387 if (!pctl->irq_array) 1388 return -ENOMEM; 1389 1390 ret = sunxi_pinctrl_build_state(pdev); 1391 if (ret) { 1392 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 1393 return ret; 1394 } 1395 1396 pins = devm_kcalloc(&pdev->dev, 1397 pctl->desc->npins, sizeof(*pins), 1398 GFP_KERNEL); 1399 if (!pins) 1400 return -ENOMEM; 1401 1402 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) { 1403 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1404 1405 if (pin->variant && !(pctl->variant & pin->variant)) 1406 continue; 1407 1408 pins[pin_idx++] = pin->pin; 1409 } 1410 1411 pctrl_desc = devm_kzalloc(&pdev->dev, 1412 sizeof(*pctrl_desc), 1413 GFP_KERNEL); 1414 if (!pctrl_desc) 1415 return -ENOMEM; 1416 1417 pctrl_desc->name = dev_name(&pdev->dev); 1418 pctrl_desc->owner = THIS_MODULE; 1419 pctrl_desc->pins = pins; 1420 pctrl_desc->npins = pctl->ngroups; 1421 pctrl_desc->confops = &sunxi_pconf_ops; 1422 pctrl_desc->pctlops = &sunxi_pctrl_ops; 1423 1424 pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops), 1425 GFP_KERNEL); 1426 if (!pmxops) 1427 return -ENOMEM; 1428 1429 if (desc->disable_strict_mode) 1430 pmxops->strict = false; 1431 1432 pctrl_desc->pmxops = pmxops; 1433 1434 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); 1435 if (IS_ERR(pctl->pctl_dev)) { 1436 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1437 return PTR_ERR(pctl->pctl_dev); 1438 } 1439 1440 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1441 if (!pctl->chip) 1442 return -ENOMEM; 1443 1444 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 1445 pctl->chip->owner = THIS_MODULE; 1446 pctl->chip->request = gpiochip_generic_request, 1447 pctl->chip->free = gpiochip_generic_free, 1448 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input, 1449 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output, 1450 pctl->chip->get = sunxi_pinctrl_gpio_get, 1451 pctl->chip->set = sunxi_pinctrl_gpio_set, 1452 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate, 1453 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq, 1454 pctl->chip->of_gpio_n_cells = 3, 1455 pctl->chip->can_sleep = false, 1456 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - 1457 pctl->desc->pin_base; 1458 pctl->chip->label = dev_name(&pdev->dev); 1459 pctl->chip->parent = &pdev->dev; 1460 pctl->chip->base = pctl->desc->pin_base; 1461 1462 ret = gpiochip_add_data(pctl->chip, pctl); 1463 if (ret) 1464 return ret; 1465 1466 for (i = 0; i < pctl->desc->npins; i++) { 1467 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1468 1469 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1470 pin->pin.number - pctl->desc->pin_base, 1471 pin->pin.number, 1); 1472 if (ret) 1473 goto gpiochip_error; 1474 } 1475 1476 ret = of_clk_get_parent_count(node); 1477 clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb"); 1478 if (IS_ERR(clk)) { 1479 ret = PTR_ERR(clk); 1480 goto gpiochip_error; 1481 } 1482 1483 ret = clk_prepare_enable(clk); 1484 if (ret) 1485 goto gpiochip_error; 1486 1487 pctl->irq = devm_kcalloc(&pdev->dev, 1488 pctl->desc->irq_banks, 1489 sizeof(*pctl->irq), 1490 GFP_KERNEL); 1491 if (!pctl->irq) { 1492 ret = -ENOMEM; 1493 goto clk_error; 1494 } 1495 1496 for (i = 0; i < pctl->desc->irq_banks; i++) { 1497 pctl->irq[i] = platform_get_irq(pdev, i); 1498 if (pctl->irq[i] < 0) { 1499 ret = pctl->irq[i]; 1500 goto clk_error; 1501 } 1502 } 1503 1504 pctl->domain = irq_domain_add_linear(node, 1505 pctl->desc->irq_banks * IRQ_PER_BANK, 1506 &sunxi_pinctrl_irq_domain_ops, 1507 pctl); 1508 if (!pctl->domain) { 1509 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 1510 ret = -ENOMEM; 1511 goto clk_error; 1512 } 1513 1514 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { 1515 int irqno = irq_create_mapping(pctl->domain, i); 1516 1517 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, 1518 handle_edge_irq); 1519 irq_set_chip_data(irqno, pctl); 1520 } 1521 1522 for (i = 0; i < pctl->desc->irq_banks; i++) { 1523 /* Mask and clear all IRQs before registering a handler */ 1524 writel(0, pctl->membase + 1525 sunxi_irq_ctrl_reg_from_bank(pctl->desc, i)); 1526 writel(0xffffffff, 1527 pctl->membase + 1528 sunxi_irq_status_reg_from_bank(pctl->desc, i)); 1529 1530 irq_set_chained_handler_and_data(pctl->irq[i], 1531 sunxi_pinctrl_irq_handler, 1532 pctl); 1533 } 1534 1535 sunxi_pinctrl_setup_debounce(pctl, node); 1536 1537 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1538 1539 return 0; 1540 1541 clk_error: 1542 clk_disable_unprepare(clk); 1543 gpiochip_error: 1544 gpiochip_remove(pctl->chip); 1545 return ret; 1546 } 1547