1 /*
2  * Allwinner new F-series F1C100s SoC (suniv) pinctrl driver.
3  *
4  * Copyright (C) 2018 Icenowy Zheng
5  *
6  * Icenowy Zheng <icenowy@aosc.io>
7  *
8  * Copyright (C) 2014 Jackie Hwang
9  *
10  * Jackie Hwang <huangshr@allwinnertech.com>
11  *
12  * Copyright (C) 2014 Chen-Yu Tsai
13  *
14  * Chen-Yu Tsai <wens@csie.org>
15  *
16  * Copyright (C) 2014 Maxime Ripard
17  *
18  * Maxime Ripard <maxime.ripard@free-electrons.com>
19  *
20  * This file is licensed under the terms of the GNU General Public
21  * License version 2.  This program is licensed "as is" without any
22  * warranty of any kind, whether express or implied.
23  */
24 
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/pinctrl/pinctrl.h>
30 
31 #include "pinctrl-sunxi.h"
32 static const struct sunxi_desc_pin suniv_f1c100s_pins[] = {
33 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
34 		  SUNXI_FUNCTION(0x0, "gpio_in"),
35 		  SUNXI_FUNCTION(0x1, "gpio_out"),
36 		  SUNXI_FUNCTION(0x2, "rtp"),		/* X1 */
37 		  SUNXI_FUNCTION(0x4, "i2s"),		/* BCLK */
38 		  SUNXI_FUNCTION(0x5, "uart1"),		/* RTS */
39 		  SUNXI_FUNCTION(0x6, "spi1")),		/* CS */
40 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
41 		  SUNXI_FUNCTION(0x0, "gpio_in"),
42 		  SUNXI_FUNCTION(0x1, "gpio_out"),
43 		  SUNXI_FUNCTION(0x2, "rtp"),		/* X2 */
44 		  SUNXI_FUNCTION(0x4, "i2s"),		/* LRCK */
45 		  SUNXI_FUNCTION(0x5, "uart1"),		/* CTS */
46 		  SUNXI_FUNCTION(0x6, "spi1")),		/* MOSI */
47 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
48 		  SUNXI_FUNCTION(0x0, "gpio_in"),
49 		  SUNXI_FUNCTION(0x1, "gpio_out"),
50 		  SUNXI_FUNCTION(0x2, "rtp"),		/* Y1 */
51 		  SUNXI_FUNCTION(0x3, "pwm0"),		/* PWM0 */
52 		  SUNXI_FUNCTION(0x4, "i2s"),		/* IN */
53 		  SUNXI_FUNCTION(0x5, "uart1"),		/* RX */
54 		  SUNXI_FUNCTION(0x6, "spi1")),		/* MOSI */
55 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
56 		  SUNXI_FUNCTION(0x0, "gpio_in"),
57 		  SUNXI_FUNCTION(0x1, "gpio_out"),
58 		  SUNXI_FUNCTION(0x2, "rtp"),		/* Y2 */
59 		  SUNXI_FUNCTION(0x3, "ir0"),		/* RX */
60 		  SUNXI_FUNCTION(0x4, "i2s"),		/* OUT */
61 		  SUNXI_FUNCTION(0x5, "uart1"),		/* TX */
62 		  SUNXI_FUNCTION(0x6, "spi1")),		/* MISO */
63 	/* Hole */
64 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
65 		  SUNXI_FUNCTION(0x0, "gpio_in"),
66 		  SUNXI_FUNCTION(0x1, "gpio_out"),
67 		  SUNXI_FUNCTION(0x2, "dram"),		/* DQS0 */
68 		  SUNXI_FUNCTION(0x3, "i2c1"),		/* SCK */
69 		  SUNXI_FUNCTION(0x4, "i2s"),		/* BCLK */
70 		  SUNXI_FUNCTION(0x5, "uart1"),		/* RTS */
71 		  SUNXI_FUNCTION(0x6, "spi1")),		/* CS */
72 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
73 		  SUNXI_FUNCTION(0x0, "gpio_in"),
74 		  SUNXI_FUNCTION(0x1, "gpio_out"),
75 		  SUNXI_FUNCTION(0x2, "dram"),		/* DQS1 */
76 		  SUNXI_FUNCTION(0x3, "i2c1"),		/* SDA */
77 		  SUNXI_FUNCTION(0x4, "i2s"),		/* LRCK */
78 		  SUNXI_FUNCTION(0x5, "uart1"),		/* CTS */
79 		  SUNXI_FUNCTION(0x6, "spi1")),		/* MOSI */
80 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
81 		  SUNXI_FUNCTION(0x0, "gpio_in"),
82 		  SUNXI_FUNCTION(0x1, "gpio_out"),
83 		  SUNXI_FUNCTION(0x2, "dram"),		/* CKE */
84 		  SUNXI_FUNCTION(0x3, "pwm0"),		/* PWM0 */
85 		  SUNXI_FUNCTION(0x4, "i2s"),		/* IN */
86 		  SUNXI_FUNCTION(0x5, "uart1"),		/* RX */
87 		  SUNXI_FUNCTION(0x6, "spi1")),		/* CLK */
88 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
89 		  SUNXI_FUNCTION(0x0, "gpio_in"),
90 		  SUNXI_FUNCTION(0x1, "gpio_out"),
91 		  SUNXI_FUNCTION(0x2, "dram"),		/* DDR_REF_D */
92 		  SUNXI_FUNCTION(0x3, "ir0"),		/* RX */
93 		  SUNXI_FUNCTION(0x4, "i2s"),		/* OUT */
94 		  SUNXI_FUNCTION(0x5, "uart1"),		/* TX */
95 		  SUNXI_FUNCTION(0x6, "spi1")),		/* MISO */
96 	/* Hole */
97 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
98 		  SUNXI_FUNCTION(0x1, "gpio_out"),
99 		  SUNXI_FUNCTION(0x2, "spi0"),		/* CLK */
100 		  SUNXI_FUNCTION(0x3, "mmc1")),		/* CLK */
101 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
102 		  SUNXI_FUNCTION(0x0, "gpio_in"),
103 		  SUNXI_FUNCTION(0x1, "gpio_out"),
104 		  SUNXI_FUNCTION(0x2, "spi0"),		/* CS */
105 		  SUNXI_FUNCTION(0x3, "mmc1")),		/* CMD */
106 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
107 		  SUNXI_FUNCTION(0x0, "gpio_in"),
108 		  SUNXI_FUNCTION(0x1, "gpio_out"),
109 		  SUNXI_FUNCTION(0x2, "spi0"),		/* MISO */
110 		  SUNXI_FUNCTION(0x3, "mmc1")),		/* D0 */
111 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
112 		  SUNXI_FUNCTION(0x0, "gpio_in"),
113 		  SUNXI_FUNCTION(0x1, "gpio_out"),
114 		  SUNXI_FUNCTION(0x2, "spi0"),		/* MOSI */
115 		  SUNXI_FUNCTION(0x3, "uart0")),	/* TX */
116 	/* Hole */
117 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
118 		  SUNXI_FUNCTION(0x0, "gpio_in"),
119 		  SUNXI_FUNCTION(0x1, "gpio_out"),
120 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D2 */
121 		  SUNXI_FUNCTION(0x3, "i2c0"),		/* SDA */
122 		  SUNXI_FUNCTION(0x4, "rsb"),		/* SDA */
123 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
124 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
125 		  SUNXI_FUNCTION(0x0, "gpio_in"),
126 		  SUNXI_FUNCTION(0x1, "gpio_out"),
127 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D3 */
128 		  SUNXI_FUNCTION(0x3, "uart1"),		/* RTS */
129 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
130 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
131 		  SUNXI_FUNCTION(0x0, "gpio_in"),
132 		  SUNXI_FUNCTION(0x1, "gpio_out"),
133 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D4*/
134 		  SUNXI_FUNCTION(0x3, "uart1"),		/* CTS */
135 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
136 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
137 		  SUNXI_FUNCTION(0x0, "gpio_in"),
138 		  SUNXI_FUNCTION(0x1, "gpio_out"),
139 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D5 */
140 		  SUNXI_FUNCTION(0x3, "uart1"),		/* RX */
141 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
142 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
143 		  SUNXI_FUNCTION(0x0, "gpio_in"),
144 		  SUNXI_FUNCTION(0x1, "gpio_out"),
145 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D6 */
146 		  SUNXI_FUNCTION(0x3, "uart1"),		/* TX */
147 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
148 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
149 		  SUNXI_FUNCTION(0x0, "gpio_in"),
150 		  SUNXI_FUNCTION(0x1, "gpio_out"),
151 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D7 */
152 		  SUNXI_FUNCTION(0x3, "i2c1"),		/* SCK */
153 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
154 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
155 		  SUNXI_FUNCTION(0x0, "gpio_in"),
156 		  SUNXI_FUNCTION(0x1, "gpio_out"),
157 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D10 */
158 		  SUNXI_FUNCTION(0x3, "i2c1"),		/* SDA */
159 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
160 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
161 		  SUNXI_FUNCTION(0x0, "gpio_in"),
162 		  SUNXI_FUNCTION(0x1, "gpio_out"),
163 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D11 */
164 		  SUNXI_FUNCTION(0x3, "i2s"),		/* MCLK */
165 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
166 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
167 		  SUNXI_FUNCTION(0x0, "gpio_in"),
168 		  SUNXI_FUNCTION(0x1, "gpio_out"),
169 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D12 */
170 		  SUNXI_FUNCTION(0x3, "i2s"),		/* BCLK */
171 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
172 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
173 		  SUNXI_FUNCTION(0x0, "gpio_in"),
174 		  SUNXI_FUNCTION(0x1, "gpio_out"),
175 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D13 */
176 		  SUNXI_FUNCTION(0x3, "i2s"),		/* LRCK */
177 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
178 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
179 		  SUNXI_FUNCTION(0x0, "gpio_in"),
180 		  SUNXI_FUNCTION(0x1, "gpio_out"),
181 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D14 */
182 		  SUNXI_FUNCTION(0x3, "i2s"),		/* IN */
183 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
184 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
185 		  SUNXI_FUNCTION(0x0, "gpio_in"),
186 		  SUNXI_FUNCTION(0x1, "gpio_out"),
187 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D15 */
188 		  SUNXI_FUNCTION(0x3, "i2s"),		/* OUT */
189 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
190 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
191 		  SUNXI_FUNCTION(0x0, "gpio_in"),
192 		  SUNXI_FUNCTION(0x1, "gpio_out"),
193 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D18 */
194 		  SUNXI_FUNCTION(0x3, "i2c0"),		/* SCK */
195 		  SUNXI_FUNCTION(0x4, "rsb"),		/* SCK */
196 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
197 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
198 		  SUNXI_FUNCTION(0x0, "gpio_in"),
199 		  SUNXI_FUNCTION(0x1, "gpio_out"),
200 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D19 */
201 		  SUNXI_FUNCTION(0x3, "uart2"),		/* TX */
202 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
203 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
204 		  SUNXI_FUNCTION(0x0, "gpio_in"),
205 		  SUNXI_FUNCTION(0x1, "gpio_out"),
206 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D20 */
207 		  SUNXI_FUNCTION(0x3, "lvds1"),		/* RX */
208 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
209 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
210 		  SUNXI_FUNCTION(0x0, "gpio_in"),
211 		  SUNXI_FUNCTION(0x1, "gpio_out"),
212 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D21 */
213 		  SUNXI_FUNCTION(0x3, "uart2"),		/* RTS */
214 		  SUNXI_FUNCTION(0x4, "i2c2"),		/* SCK */
215 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
216 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
217 		  SUNXI_FUNCTION(0x0, "gpio_in"),
218 		  SUNXI_FUNCTION(0x1, "gpio_out"),
219 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D22 */
220 		  SUNXI_FUNCTION(0x3, "uart2"),		/* CTS */
221 		  SUNXI_FUNCTION(0x4, "i2c2"),		/* SDA */
222 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
223 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
224 		  SUNXI_FUNCTION(0x0, "gpio_in"),
225 		  SUNXI_FUNCTION(0x1, "gpio_out"),
226 		  SUNXI_FUNCTION(0x2, "lcd"),		/* D23 */
227 		  SUNXI_FUNCTION(0x3, "spdif"),		/* OUT */
228 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
229 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
230 		  SUNXI_FUNCTION(0x0, "gpio_in"),
231 		  SUNXI_FUNCTION(0x1, "gpio_out"),
232 		  SUNXI_FUNCTION(0x2, "lcd"),		/* CLK */
233 		  SUNXI_FUNCTION(0x3, "spi0"),		/* CS */
234 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
235 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
236 		  SUNXI_FUNCTION(0x0, "gpio_in"),
237 		  SUNXI_FUNCTION(0x1, "gpio_out"),
238 		  SUNXI_FUNCTION(0x2, "lcd"),		/* DE */
239 		  SUNXI_FUNCTION(0x3, "spi0"),		/* MOSI */
240 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
241 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
242 		  SUNXI_FUNCTION(0x0, "gpio_in"),
243 		  SUNXI_FUNCTION(0x1, "gpio_out"),
244 		  SUNXI_FUNCTION(0x2, "lcd"),		/* HYSNC */
245 		  SUNXI_FUNCTION(0x3, "spi0"),		/* CLK */
246 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
247 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
248 		  SUNXI_FUNCTION(0x0, "gpio_in"),
249 		  SUNXI_FUNCTION(0x1, "gpio_out"),
250 		  SUNXI_FUNCTION(0x2, "lcd"),		/* VSYNC */
251 		  SUNXI_FUNCTION(0x3, "spi0"),		/* MISO */
252 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)),
253 	/* Hole */
254 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
255 		  SUNXI_FUNCTION(0x0, "gpio_in"),
256 		  SUNXI_FUNCTION(0x1, "gpio_out"),
257 		  SUNXI_FUNCTION(0x2, "csi"),		/* HSYNC */
258 		  SUNXI_FUNCTION(0x3, "lcd"),		/* D0 */
259 		  SUNXI_FUNCTION(0x4, "i2c2"),		/* SCK */
260 		  SUNXI_FUNCTION(0x5, "uart0"),		/* RX */
261 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
262 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
263 		  SUNXI_FUNCTION(0x0, "gpio_in"),
264 		  SUNXI_FUNCTION(0x1, "gpio_out"),
265 		  SUNXI_FUNCTION(0x2, "csi"),		/* VSYNC */
266 		  SUNXI_FUNCTION(0x3, "lcd"),		/* D1 */
267 		  SUNXI_FUNCTION(0x4, "i2c2"),		/* SDA */
268 		  SUNXI_FUNCTION(0x5, "uart0"),		/* TX */
269 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
270 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
271 		  SUNXI_FUNCTION(0x0, "gpio_in"),
272 		  SUNXI_FUNCTION(0x1, "gpio_out"),
273 		  SUNXI_FUNCTION(0x2, "csi"),		/* PCLK */
274 		  SUNXI_FUNCTION(0x3, "lcd"),		/* D8 */
275 		  SUNXI_FUNCTION(0x4, "clk"),		/* OUT */
276 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
277 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
278 		  SUNXI_FUNCTION(0x0, "gpio_in"),
279 		  SUNXI_FUNCTION(0x1, "gpio_out"),
280 		  SUNXI_FUNCTION(0x2, "csi"),		/* D0 */
281 		  SUNXI_FUNCTION(0x3, "lcd"),		/* D9 */
282 		  SUNXI_FUNCTION(0x4, "i2s"),		/* BCLK */
283 		  SUNXI_FUNCTION(0x5, "rsb"),		/* SCK */
284 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
285 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
286 		  SUNXI_FUNCTION(0x0, "gpio_in"),
287 		  SUNXI_FUNCTION(0x1, "gpio_out"),
288 		  SUNXI_FUNCTION(0x2, "csi"),		/* D1 */
289 		  SUNXI_FUNCTION(0x3, "lcd"),		/* D16 */
290 		  SUNXI_FUNCTION(0x4, "i2s"),		/* LRCK */
291 		  SUNXI_FUNCTION(0x5, "rsb"),		/* SDA */
292 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
293 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
294 		  SUNXI_FUNCTION(0x0, "gpio_in"),
295 		  SUNXI_FUNCTION(0x1, "gpio_out"),
296 		  SUNXI_FUNCTION(0x2, "csi"),		/* D2 */
297 		  SUNXI_FUNCTION(0x3, "lcd"),		/* D17 */
298 		  SUNXI_FUNCTION(0x4, "i2s"),		/* IN */
299 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
300 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
301 		  SUNXI_FUNCTION(0x0, "gpio_in"),
302 		  SUNXI_FUNCTION(0x1, "gpio_out"),
303 		  SUNXI_FUNCTION(0x2, "csi"),		/* D3 */
304 		  SUNXI_FUNCTION(0x3, "pwm1"),		/* PWM1 */
305 		  SUNXI_FUNCTION(0x4, "i2s"),		/* OUT */
306 		  SUNXI_FUNCTION(0x5, "spdif"),		/* OUT */
307 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
308 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
309 		  SUNXI_FUNCTION(0x0, "gpio_in"),
310 		  SUNXI_FUNCTION(0x1, "gpio_out"),
311 		  SUNXI_FUNCTION(0x2, "csi"),		/* D4 */
312 		  SUNXI_FUNCTION(0x3, "uart2"),		/* TX */
313 		  SUNXI_FUNCTION(0x4, "spi1"),		/* CS */
314 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
315 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
316 		  SUNXI_FUNCTION(0x0, "gpio_in"),
317 		  SUNXI_FUNCTION(0x1, "gpio_out"),
318 		  SUNXI_FUNCTION(0x2, "csi"),		/* D5 */
319 		  SUNXI_FUNCTION(0x3, "uart2"),		/* RX */
320 		  SUNXI_FUNCTION(0x4, "spi1"),		/* MOSI */
321 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
322 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
323 		  SUNXI_FUNCTION(0x0, "gpio_in"),
324 		  SUNXI_FUNCTION(0x1, "gpio_out"),
325 		  SUNXI_FUNCTION(0x2, "csi"),		/* D6 */
326 		  SUNXI_FUNCTION(0x3, "uart2"),		/* RTS */
327 		  SUNXI_FUNCTION(0x4, "spi1"),		/* CLK */
328 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
329 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
330 		  SUNXI_FUNCTION(0x0, "gpio_in"),
331 		  SUNXI_FUNCTION(0x1, "gpio_out"),
332 		  SUNXI_FUNCTION(0x2, "csi"),		/* D7 */
333 		  SUNXI_FUNCTION(0x3, "uart2"),		/* CTS */
334 		  SUNXI_FUNCTION(0x4, "spi1"),		/* MISO */
335 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
336 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
337 		  SUNXI_FUNCTION(0x0, "gpio_in"),
338 		  SUNXI_FUNCTION(0x1, "gpio_out"),
339 		  SUNXI_FUNCTION(0x2, "clk0"),		/* OUT */
340 		  SUNXI_FUNCTION(0x3, "i2c0"),		/* SCK */
341 		  SUNXI_FUNCTION(0x4, "ir"),		/* RX */
342 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
343 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
344 		  SUNXI_FUNCTION(0x0, "gpio_in"),
345 		  SUNXI_FUNCTION(0x1, "gpio_out"),
346 		  SUNXI_FUNCTION(0x2, "i2s"),		/* MCLK */
347 		  SUNXI_FUNCTION(0x3, "i2c0"),		/* SDA */
348 		  SUNXI_FUNCTION(0x4, "pwm0"),		/* PWM0 */
349 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
350 
351 	/* Hole */
352 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
353 		  SUNXI_FUNCTION(0x0, "gpio_in"),
354 		  SUNXI_FUNCTION(0x1, "gpio_out"),
355 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D1 */
356 		  SUNXI_FUNCTION(0x3, "jtag"),		/* MS */
357 		  SUNXI_FUNCTION(0x4, "ir0"),		/* MS */
358 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
359 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
360 		  SUNXI_FUNCTION(0x0, "gpio_in"),
361 		  SUNXI_FUNCTION(0x1, "gpio_out"),
362 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D0 */
363 		  SUNXI_FUNCTION(0x3, "dgb0"),		/* DI */
364 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
365 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
366 		  SUNXI_FUNCTION(0x0, "gpio_in"),
367 		  SUNXI_FUNCTION(0x1, "gpio_out"),
368 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CLK */
369 		  SUNXI_FUNCTION(0x3, "uart0"),		/* TX */
370 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
371 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
372 		  SUNXI_FUNCTION(0x0, "gpio_in"),
373 		  SUNXI_FUNCTION(0x1, "gpio_out"),
374 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CMD */
375 		  SUNXI_FUNCTION(0x3, "jtag"),		/* DO */
376 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
377 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
378 		  SUNXI_FUNCTION(0x0, "gpio_in"),
379 		  SUNXI_FUNCTION(0x1, "gpio_out"),
380 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D3 */
381 		  SUNXI_FUNCTION(0x3, "uart0"),		/* TX */
382 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
383 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
384 		  SUNXI_FUNCTION(0x0, "gpio_in"),
385 		  SUNXI_FUNCTION(0x1, "gpio_out"),
386 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D2 */
387 		  SUNXI_FUNCTION(0x3, "jtag"),		/* CK */
388 		  SUNXI_FUNCTION(0x4, "pwm1"),		/* PWM1 */
389 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
390 };
391 
392 static const struct sunxi_pinctrl_desc suniv_f1c100s_pinctrl_data = {
393 	.pins = suniv_f1c100s_pins,
394 	.npins = ARRAY_SIZE(suniv_f1c100s_pins),
395 	.irq_banks = 3,
396 };
397 
398 static int suniv_pinctrl_probe(struct platform_device *pdev)
399 {
400 	return sunxi_pinctrl_init(pdev,
401 				  &suniv_f1c100s_pinctrl_data);
402 }
403 
404 static const struct of_device_id suniv_f1c100s_pinctrl_match[] = {
405 	{ .compatible = "allwinner,suniv-f1c100s-pinctrl", },
406 	{}
407 };
408 
409 static struct platform_driver suniv_f1c100s_pinctrl_driver = {
410 	.probe	= suniv_pinctrl_probe,
411 	.driver	= {
412 		.name		= "suniv-f1c100s-pinctrl",
413 		.of_match_table	= suniv_f1c100s_pinctrl_match,
414 	},
415 };
416 builtin_platform_driver(suniv_f1c100s_pinctrl_driver);
417