1 /*
2  * Allwinner A80 SoCs special pins pinctrl driver.
3  *
4  * Copyright (C) 2014 Maxime Ripard
5  * Maxime Ripard <maxime.ripard@free-electrons.com>
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2.  This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11 
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/of.h>
15 #include <linux/of_device.h>
16 #include <linux/pinctrl/pinctrl.h>
17 #include <linux/reset.h>
18 
19 #include "pinctrl-sunxi.h"
20 
21 static const struct sunxi_desc_pin sun9i_a80_r_pins[] = {
22 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
23 		  SUNXI_FUNCTION(0x0, "gpio_in"),
24 		  SUNXI_FUNCTION(0x1, "gpio_out"),
25 		  SUNXI_FUNCTION(0x3, "s_uart"),	/* TX */
26 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* PL_EINT0 */
27 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
28 		  SUNXI_FUNCTION(0x0, "gpio_in"),
29 		  SUNXI_FUNCTION(0x1, "gpio_out"),
30 		  SUNXI_FUNCTION(0x3, "s_uart"),	/* RX */
31 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),	/* PL_EINT1 */
32 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
33 		  SUNXI_FUNCTION(0x0, "gpio_in"),
34 		  SUNXI_FUNCTION(0x1, "gpio_out"),
35 		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* TMS */
36 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),	/* PL_EINT2 */
37 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
38 		  SUNXI_FUNCTION(0x0, "gpio_in"),
39 		  SUNXI_FUNCTION(0x1, "gpio_out"),
40 		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* TCK */
41 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PL_EINT3 */
42 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
43 		  SUNXI_FUNCTION(0x0, "gpio_in"),
44 		  SUNXI_FUNCTION(0x1, "gpio_out"),
45 		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* TDO */
46 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),	/* PL_EINT4 */
47 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
48 		  SUNXI_FUNCTION(0x0, "gpio_in"),
49 		  SUNXI_FUNCTION(0x1, "gpio_out"),
50 		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* TDI */
51 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),	/* PL_EINT5 */
52 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
53 		  SUNXI_FUNCTION(0x0, "gpio_in"),
54 		  SUNXI_FUNCTION(0x1, "gpio_out"),
55 		  SUNXI_FUNCTION(0x3, "s_cir_rx"),
56 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),	/* PL_EINT6 */
57 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
58 		  SUNXI_FUNCTION(0x0, "gpio_in"),
59 		  SUNXI_FUNCTION(0x1, "gpio_out"),
60 		  SUNXI_FUNCTION(0x3, "1wire"),
61 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),	/* PL_EINT7 */
62 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
63 		  SUNXI_FUNCTION(0x0, "gpio_in"),
64 		  SUNXI_FUNCTION(0x1, "gpio_out"),
65 		  SUNXI_FUNCTION(0x2, "s_ps2"),		/* SCK1 */
66 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),	/* PL_EINT8 */
67 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
68 		  SUNXI_FUNCTION(0x0, "gpio_in"),
69 		  SUNXI_FUNCTION(0x1, "gpio_out"),
70 		  SUNXI_FUNCTION(0x2, "s_ps2"),		/* SDA1 */
71 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),	/* PL_EINT9 */
72 
73 	/* Hole */
74 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
75 		  SUNXI_FUNCTION(0x0, "gpio_in"),
76 		  SUNXI_FUNCTION(0x1, "gpio_out"),
77 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),	/* PM_EINT0 */
78 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
79 		  SUNXI_FUNCTION(0x0, "gpio_in"),
80 		  SUNXI_FUNCTION(0x1, "gpio_out"),
81 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),	/* PM_EINT1 */
82 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
83 		  SUNXI_FUNCTION(0x0, "gpio_in"),
84 		  SUNXI_FUNCTION(0x1, "gpio_out"),
85 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),	/* PM_EINT2 */
86 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
87 		  SUNXI_FUNCTION(0x0, "gpio_in"),
88 		  SUNXI_FUNCTION(0x1, "gpio_out"),
89 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),	/* PM_EINT3 */
90 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
91 		  SUNXI_FUNCTION(0x0, "gpio_in"),
92 		  SUNXI_FUNCTION(0x1, "gpio_out"),
93 		  SUNXI_FUNCTION(0x3, "s_i2s1"),	/* LRCKR */
94 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),	/* PM_EINT4 */
95 
96 	/* Hole */
97 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 8),
98 		  SUNXI_FUNCTION(0x0, "gpio_in"),
99 		  SUNXI_FUNCTION(0x1, "gpio_out"),
100 		  SUNXI_FUNCTION(0x3, "s_i2c1"),	/* SCK */
101 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),	/* PM_EINT8 */
102 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 9),
103 		  SUNXI_FUNCTION(0x0, "gpio_in"),
104 		  SUNXI_FUNCTION(0x1, "gpio_out"),
105 		  SUNXI_FUNCTION(0x3, "s_i2c1"),	/* SDA */
106 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),	/* PM_EINT9 */
107 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 10),
108 		  SUNXI_FUNCTION(0x0, "gpio_in"),
109 		  SUNXI_FUNCTION(0x1, "gpio_out"),
110 		  SUNXI_FUNCTION(0x2, "s_i2s0"),	/* MCLK */
111 		  SUNXI_FUNCTION(0x3, "s_i2s1")),	/* MCLK */
112 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 11),
113 		  SUNXI_FUNCTION(0x0, "gpio_in"),
114 		  SUNXI_FUNCTION(0x1, "gpio_out"),
115 		  SUNXI_FUNCTION(0x2, "s_i2s0"),	/* BCLK */
116 		  SUNXI_FUNCTION(0x3, "s_i2s1")),	/* BCLK */
117 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 12),
118 		  SUNXI_FUNCTION(0x0, "gpio_in"),
119 		  SUNXI_FUNCTION(0x1, "gpio_out"),
120 		  SUNXI_FUNCTION(0x2, "s_i2s0"),	/* LRCK */
121 		  SUNXI_FUNCTION(0x3, "s_i2s1")),	/* LRCK */
122 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 13),
123 		  SUNXI_FUNCTION(0x0, "gpio_in"),
124 		  SUNXI_FUNCTION(0x1, "gpio_out"),
125 		  SUNXI_FUNCTION(0x2, "s_i2s0"),	/* DIN */
126 		  SUNXI_FUNCTION(0x3, "s_i2s1")),	/* DIN */
127 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 14),
128 		  SUNXI_FUNCTION(0x0, "gpio_in"),
129 		  SUNXI_FUNCTION(0x1, "gpio_out"),
130 		  SUNXI_FUNCTION(0x2, "s_i2s0"),	/* DOUT */
131 		  SUNXI_FUNCTION(0x3, "s_i2s1")),	/* DOUT */
132 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 15),
133 		  SUNXI_FUNCTION(0x0, "gpio_in"),
134 		  SUNXI_FUNCTION(0x1, "gpio_out"),
135 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)),	/* PM_EINT15 */
136 
137 	/* Hole */
138 	SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 0),
139 		  SUNXI_FUNCTION(0x0, "gpio_in"),
140 		  SUNXI_FUNCTION(0x1, "gpio_out"),
141 		  SUNXI_FUNCTION(0x2, "s_i2c0"),	/* SCK */
142 		  SUNXI_FUNCTION(0x3, "s_rsb")),	/* SCK */
143 	SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 1),
144 		  SUNXI_FUNCTION(0x0, "gpio_in"),
145 		  SUNXI_FUNCTION(0x1, "gpio_out"),
146 		  SUNXI_FUNCTION(0x2, "s_i2c0"),	/* SDA */
147 		  SUNXI_FUNCTION(0x3, "s_rsb")),	/* SDA */
148 };
149 
150 static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
151 	.pins = sun9i_a80_r_pins,
152 	.npins = ARRAY_SIZE(sun9i_a80_r_pins),
153 	.pin_base = PL_BASE,
154 	.irq_banks = 2,
155 };
156 
157 static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)
158 {
159 	return sunxi_pinctrl_init(pdev,
160 				  &sun9i_a80_r_pinctrl_data);
161 }
162 
163 static const struct of_device_id sun9i_a80_r_pinctrl_match[] = {
164 	{ .compatible = "allwinner,sun9i-a80-r-pinctrl", },
165 	{}
166 };
167 
168 static struct platform_driver sun9i_a80_r_pinctrl_driver = {
169 	.probe	= sun9i_a80_r_pinctrl_probe,
170 	.driver	= {
171 		.name		= "sun9i-a80-r-pinctrl",
172 		.owner		= THIS_MODULE,
173 		.of_match_table	= sun9i_a80_r_pinctrl_match,
174 	},
175 };
176 builtin_platform_driver(sun9i_a80_r_pinctrl_driver);
177