1 /*
2  * Allwinner A80 SoCs special pins pinctrl driver.
3  *
4  * Copyright (C) 2014 Maxime Ripard
5  * Maxime Ripard <maxime.ripard@free-electrons.com>
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2.  This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11 
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/of.h>
15 #include <linux/pinctrl/pinctrl.h>
16 
17 #include "pinctrl-sunxi.h"
18 
19 static const struct sunxi_desc_pin sun9i_a80_r_pins[] = {
20 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
21 		  SUNXI_FUNCTION(0x0, "gpio_in"),
22 		  SUNXI_FUNCTION(0x1, "gpio_out"),
23 		  SUNXI_FUNCTION(0x3, "s_uart"),	/* TX */
24 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* PL_EINT0 */
25 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
26 		  SUNXI_FUNCTION(0x0, "gpio_in"),
27 		  SUNXI_FUNCTION(0x1, "gpio_out"),
28 		  SUNXI_FUNCTION(0x3, "s_uart"),	/* RX */
29 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),	/* PL_EINT1 */
30 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
31 		  SUNXI_FUNCTION(0x0, "gpio_in"),
32 		  SUNXI_FUNCTION(0x1, "gpio_out"),
33 		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* TMS */
34 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),	/* PL_EINT2 */
35 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
36 		  SUNXI_FUNCTION(0x0, "gpio_in"),
37 		  SUNXI_FUNCTION(0x1, "gpio_out"),
38 		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* TCK */
39 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PL_EINT3 */
40 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
41 		  SUNXI_FUNCTION(0x0, "gpio_in"),
42 		  SUNXI_FUNCTION(0x1, "gpio_out"),
43 		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* TDO */
44 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),	/* PL_EINT4 */
45 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
46 		  SUNXI_FUNCTION(0x0, "gpio_in"),
47 		  SUNXI_FUNCTION(0x1, "gpio_out"),
48 		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* TDI */
49 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),	/* PL_EINT5 */
50 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
51 		  SUNXI_FUNCTION(0x0, "gpio_in"),
52 		  SUNXI_FUNCTION(0x1, "gpio_out"),
53 		  SUNXI_FUNCTION(0x3, "s_cir_rx"),
54 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),	/* PL_EINT6 */
55 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
56 		  SUNXI_FUNCTION(0x0, "gpio_in"),
57 		  SUNXI_FUNCTION(0x1, "gpio_out"),
58 		  SUNXI_FUNCTION(0x3, "1wire"),
59 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),	/* PL_EINT7 */
60 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
61 		  SUNXI_FUNCTION(0x0, "gpio_in"),
62 		  SUNXI_FUNCTION(0x1, "gpio_out"),
63 		  SUNXI_FUNCTION(0x2, "s_ps2"),		/* SCK1 */
64 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),	/* PL_EINT8 */
65 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
66 		  SUNXI_FUNCTION(0x0, "gpio_in"),
67 		  SUNXI_FUNCTION(0x1, "gpio_out"),
68 		  SUNXI_FUNCTION(0x2, "s_ps2"),		/* SDA1 */
69 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),	/* PL_EINT9 */
70 
71 	/* Hole */
72 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
73 		  SUNXI_FUNCTION(0x0, "gpio_in"),
74 		  SUNXI_FUNCTION(0x1, "gpio_out"),
75 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),	/* PM_EINT0 */
76 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
77 		  SUNXI_FUNCTION(0x0, "gpio_in"),
78 		  SUNXI_FUNCTION(0x1, "gpio_out"),
79 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),	/* PM_EINT1 */
80 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
81 		  SUNXI_FUNCTION(0x0, "gpio_in"),
82 		  SUNXI_FUNCTION(0x1, "gpio_out"),
83 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),	/* PM_EINT2 */
84 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
85 		  SUNXI_FUNCTION(0x0, "gpio_in"),
86 		  SUNXI_FUNCTION(0x1, "gpio_out"),
87 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),	/* PM_EINT3 */
88 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
89 		  SUNXI_FUNCTION(0x0, "gpio_in"),
90 		  SUNXI_FUNCTION(0x1, "gpio_out"),
91 		  SUNXI_FUNCTION(0x3, "s_i2s1"),	/* LRCKR */
92 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),	/* PM_EINT4 */
93 
94 	/* Hole */
95 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 8),
96 		  SUNXI_FUNCTION(0x0, "gpio_in"),
97 		  SUNXI_FUNCTION(0x1, "gpio_out"),
98 		  SUNXI_FUNCTION(0x3, "s_i2c1"),	/* SCK */
99 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),	/* PM_EINT8 */
100 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 9),
101 		  SUNXI_FUNCTION(0x0, "gpio_in"),
102 		  SUNXI_FUNCTION(0x1, "gpio_out"),
103 		  SUNXI_FUNCTION(0x3, "s_i2c1"),	/* SDA */
104 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),	/* PM_EINT9 */
105 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 10),
106 		  SUNXI_FUNCTION(0x0, "gpio_in"),
107 		  SUNXI_FUNCTION(0x1, "gpio_out"),
108 		  SUNXI_FUNCTION(0x2, "s_i2s0"),	/* MCLK */
109 		  SUNXI_FUNCTION(0x3, "s_i2s1")),	/* MCLK */
110 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 11),
111 		  SUNXI_FUNCTION(0x0, "gpio_in"),
112 		  SUNXI_FUNCTION(0x1, "gpio_out"),
113 		  SUNXI_FUNCTION(0x2, "s_i2s0"),	/* BCLK */
114 		  SUNXI_FUNCTION(0x3, "s_i2s1")),	/* BCLK */
115 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 12),
116 		  SUNXI_FUNCTION(0x0, "gpio_in"),
117 		  SUNXI_FUNCTION(0x1, "gpio_out"),
118 		  SUNXI_FUNCTION(0x2, "s_i2s0"),	/* LRCK */
119 		  SUNXI_FUNCTION(0x3, "s_i2s1")),	/* LRCK */
120 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 13),
121 		  SUNXI_FUNCTION(0x0, "gpio_in"),
122 		  SUNXI_FUNCTION(0x1, "gpio_out"),
123 		  SUNXI_FUNCTION(0x2, "s_i2s0"),	/* DIN */
124 		  SUNXI_FUNCTION(0x3, "s_i2s1")),	/* DIN */
125 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 14),
126 		  SUNXI_FUNCTION(0x0, "gpio_in"),
127 		  SUNXI_FUNCTION(0x1, "gpio_out"),
128 		  SUNXI_FUNCTION(0x2, "s_i2s0"),	/* DOUT */
129 		  SUNXI_FUNCTION(0x3, "s_i2s1")),	/* DOUT */
130 	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 15),
131 		  SUNXI_FUNCTION(0x0, "gpio_in"),
132 		  SUNXI_FUNCTION(0x1, "gpio_out"),
133 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)),	/* PM_EINT15 */
134 
135 	/* Hole */
136 	SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 0),
137 		  SUNXI_FUNCTION(0x0, "gpio_in"),
138 		  SUNXI_FUNCTION(0x1, "gpio_out"),
139 		  SUNXI_FUNCTION(0x2, "s_i2c0"),	/* SCK */
140 		  SUNXI_FUNCTION(0x3, "s_rsb")),	/* SCK */
141 	SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 1),
142 		  SUNXI_FUNCTION(0x0, "gpio_in"),
143 		  SUNXI_FUNCTION(0x1, "gpio_out"),
144 		  SUNXI_FUNCTION(0x2, "s_i2c0"),	/* SDA */
145 		  SUNXI_FUNCTION(0x3, "s_rsb")),	/* SDA */
146 };
147 
148 static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
149 	.pins = sun9i_a80_r_pins,
150 	.npins = ARRAY_SIZE(sun9i_a80_r_pins),
151 	.pin_base = PL_BASE,
152 	.irq_banks = 2,
153 	.disable_strict_mode = true,
154 	.io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
155 };
156 
sun9i_a80_r_pinctrl_probe(struct platform_device * pdev)157 static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)
158 {
159 	return sunxi_pinctrl_init(pdev,
160 				  &sun9i_a80_r_pinctrl_data);
161 }
162 
163 static const struct of_device_id sun9i_a80_r_pinctrl_match[] = {
164 	{ .compatible = "allwinner,sun9i-a80-r-pinctrl", },
165 	{}
166 };
167 
168 static struct platform_driver sun9i_a80_r_pinctrl_driver = {
169 	.probe	= sun9i_a80_r_pinctrl_probe,
170 	.driver	= {
171 		.name		= "sun9i-a80-r-pinctrl",
172 		.owner		= THIS_MODULE,
173 		.of_match_table	= sun9i_a80_r_pinctrl_match,
174 	},
175 };
176 builtin_platform_driver(sun9i_a80_r_pinctrl_driver);
177