1 /* 2 * Allwinner A31 SoCs pinctrl driver. 3 * 4 * Copyright (C) 2014 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/pinctrl.h> 18 19 #include "pinctrl-sunxi.h" 20 21 static const struct sunxi_desc_pin sun6i_a31_pins[] = { 22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), 23 SUNXI_FUNCTION(0x0, "gpio_in"), 24 SUNXI_FUNCTION(0x1, "gpio_out"), 25 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */ 26 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */ 27 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ 28 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ 29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), 30 SUNXI_FUNCTION(0x0, "gpio_in"), 31 SUNXI_FUNCTION(0x1, "gpio_out"), 32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */ 33 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */ 34 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ 35 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ 36 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), 37 SUNXI_FUNCTION(0x0, "gpio_in"), 38 SUNXI_FUNCTION(0x1, "gpio_out"), 39 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */ 40 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */ 41 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ 42 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ 43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), 44 SUNXI_FUNCTION(0x0, "gpio_in"), 45 SUNXI_FUNCTION(0x1, "gpio_out"), 46 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */ 47 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */ 48 SUNXI_FUNCTION(0x4, "uart1"), /* RING */ 49 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ 50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), 51 SUNXI_FUNCTION(0x0, "gpio_in"), 52 SUNXI_FUNCTION(0x1, "gpio_out"), 53 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */ 54 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */ 55 SUNXI_FUNCTION(0x4, "uart1"), /* TX */ 56 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ 57 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), 58 SUNXI_FUNCTION(0x0, "gpio_in"), 59 SUNXI_FUNCTION(0x1, "gpio_out"), 60 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */ 61 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */ 62 SUNXI_FUNCTION(0x4, "uart1"), /* RX */ 63 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ 64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), 65 SUNXI_FUNCTION(0x0, "gpio_in"), 66 SUNXI_FUNCTION(0x1, "gpio_out"), 67 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */ 68 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */ 69 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ 70 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ 71 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), 72 SUNXI_FUNCTION(0x0, "gpio_in"), 73 SUNXI_FUNCTION(0x1, "gpio_out"), 74 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */ 75 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */ 76 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ 77 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ 78 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), 79 SUNXI_FUNCTION(0x0, "gpio_in"), 80 SUNXI_FUNCTION(0x1, "gpio_out"), 81 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */ 82 SUNXI_FUNCTION(0x3, "lcd1"), /* D8 */ 83 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ 84 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), 85 SUNXI_FUNCTION(0x0, "gpio_in"), 86 SUNXI_FUNCTION(0x1, "gpio_out"), 87 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */ 88 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */ 89 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */ 90 SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */ 91 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ 92 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), 93 SUNXI_FUNCTION(0x0, "gpio_in"), 94 SUNXI_FUNCTION(0x1, "gpio_out"), 95 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */ 96 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */ 97 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */ 98 SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */ 99 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ 100 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), 101 SUNXI_FUNCTION(0x0, "gpio_in"), 102 SUNXI_FUNCTION(0x1, "gpio_out"), 103 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */ 104 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */ 105 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */ 106 SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */ 107 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ 108 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), 109 SUNXI_FUNCTION(0x0, "gpio_in"), 110 SUNXI_FUNCTION(0x1, "gpio_out"), 111 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */ 112 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */ 113 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */ 114 SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */ 115 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ 116 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), 117 SUNXI_FUNCTION(0x0, "gpio_in"), 118 SUNXI_FUNCTION(0x1, "gpio_out"), 119 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */ 120 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */ 121 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */ 122 SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */ 123 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */ 124 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), 125 SUNXI_FUNCTION(0x0, "gpio_in"), 126 SUNXI_FUNCTION(0x1, "gpio_out"), 127 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */ 128 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */ 129 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */ 130 SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */ 131 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */ 132 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), 133 SUNXI_FUNCTION(0x0, "gpio_in"), 134 SUNXI_FUNCTION(0x1, "gpio_out"), 135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */ 136 SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */ 137 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ 138 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), 139 SUNXI_FUNCTION(0x0, "gpio_in"), 140 SUNXI_FUNCTION(0x1, "gpio_out"), 141 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */ 142 SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */ 143 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ 144 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), 145 SUNXI_FUNCTION(0x0, "gpio_in"), 146 SUNXI_FUNCTION(0x1, "gpio_out"), 147 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */ 148 SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */ 149 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ 150 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), 151 SUNXI_FUNCTION(0x0, "gpio_in"), 152 SUNXI_FUNCTION(0x1, "gpio_out"), 153 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */ 154 SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */ 155 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ 156 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), 157 SUNXI_FUNCTION(0x0, "gpio_in"), 158 SUNXI_FUNCTION(0x1, "gpio_out"), 159 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */ 160 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */ 161 SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */ 162 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */ 163 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), 164 SUNXI_FUNCTION(0x0, "gpio_in"), 165 SUNXI_FUNCTION(0x1, "gpio_out"), 166 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */ 167 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */ 168 SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */ 169 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */ 170 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), 171 SUNXI_FUNCTION(0x0, "gpio_in"), 172 SUNXI_FUNCTION(0x1, "gpio_out"), 173 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */ 174 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */ 175 SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */ 176 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */ 177 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22), 178 SUNXI_FUNCTION(0x0, "gpio_in"), 179 SUNXI_FUNCTION(0x1, "gpio_out"), 180 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */ 181 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */ 182 SUNXI_FUNCTION(0x4, "spi3"), /* CLK */ 183 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */ 184 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23), 185 SUNXI_FUNCTION(0x0, "gpio_in"), 186 SUNXI_FUNCTION(0x1, "gpio_out"), 187 SUNXI_FUNCTION(0x2, "gmac"), /* COL */ 188 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */ 189 SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */ 190 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */ 191 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24), 192 SUNXI_FUNCTION(0x0, "gpio_in"), 193 SUNXI_FUNCTION(0x1, "gpio_out"), 194 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */ 195 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */ 196 SUNXI_FUNCTION(0x4, "spi3"), /* MISO */ 197 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */ 198 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25), 199 SUNXI_FUNCTION(0x0, "gpio_in"), 200 SUNXI_FUNCTION(0x1, "gpio_out"), 201 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */ 202 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */ 203 SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */ 204 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */ 205 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26), 206 SUNXI_FUNCTION(0x0, "gpio_in"), 207 SUNXI_FUNCTION(0x1, "gpio_out"), 208 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */ 209 SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */ 210 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */ 211 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27), 212 SUNXI_FUNCTION(0x0, "gpio_in"), 213 SUNXI_FUNCTION(0x1, "gpio_out"), 214 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */ 215 SUNXI_FUNCTION(0x3, "lcd1"), /* VSYNC */ 216 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */ 217 /* Hole */ 218 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), 219 SUNXI_FUNCTION(0x0, "gpio_in"), 220 SUNXI_FUNCTION(0x1, "gpio_out"), 221 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ 222 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 223 SUNXI_FUNCTION(0x4, "csi"), /* MCLK1 */ 224 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */ 225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), 226 SUNXI_FUNCTION(0x0, "gpio_in"), 227 SUNXI_FUNCTION(0x1, "gpio_out"), 228 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ 229 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */ 230 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), 231 SUNXI_FUNCTION(0x0, "gpio_in"), 232 SUNXI_FUNCTION(0x1, "gpio_out"), 233 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */ 234 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */ 235 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), 236 SUNXI_FUNCTION(0x0, "gpio_in"), 237 SUNXI_FUNCTION(0x1, "gpio_out"), 238 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */ 239 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */ 240 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), 241 SUNXI_FUNCTION(0x0, "gpio_in"), 242 SUNXI_FUNCTION(0x1, "gpio_out"), 243 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */ 244 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ 245 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */ 246 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), 247 SUNXI_FUNCTION(0x0, "gpio_in"), 248 SUNXI_FUNCTION(0x1, "gpio_out"), 249 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */ 250 SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 251 SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */ 252 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */ 253 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), 254 SUNXI_FUNCTION(0x0, "gpio_in"), 255 SUNXI_FUNCTION(0x1, "gpio_out"), 256 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */ 257 SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 258 SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */ 259 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */ 260 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), 261 SUNXI_FUNCTION(0x0, "gpio_in"), 262 SUNXI_FUNCTION(0x1, "gpio_out"), 263 SUNXI_FUNCTION(0x3, "i2s0"), /* DI */ 264 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */ 265 /* Hole */ 266 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 267 SUNXI_FUNCTION(0x0, "gpio_in"), 268 SUNXI_FUNCTION(0x1, "gpio_out"), 269 SUNXI_FUNCTION(0x2, "nand0"), /* WE */ 270 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 271 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), 272 SUNXI_FUNCTION(0x0, "gpio_in"), 273 SUNXI_FUNCTION(0x1, "gpio_out"), 274 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ 275 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ 276 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), 277 SUNXI_FUNCTION(0x0, "gpio_in"), 278 SUNXI_FUNCTION(0x1, "gpio_out"), 279 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ 280 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ 281 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), 282 SUNXI_FUNCTION(0x0, "gpio_in"), 283 SUNXI_FUNCTION(0x1, "gpio_out"), 284 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */ 285 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), 286 SUNXI_FUNCTION(0x0, "gpio_in"), 287 SUNXI_FUNCTION(0x1, "gpio_out"), 288 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */ 289 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), 290 SUNXI_FUNCTION(0x0, "gpio_in"), 291 SUNXI_FUNCTION(0x1, "gpio_out"), 292 SUNXI_FUNCTION(0x2, "nand0")), /* RE */ 293 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), 294 SUNXI_FUNCTION(0x0, "gpio_in"), 295 SUNXI_FUNCTION(0x1, "gpio_out"), 296 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ 297 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */ 298 SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */ 299 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), 300 SUNXI_FUNCTION(0x0, "gpio_in"), 301 SUNXI_FUNCTION(0x1, "gpio_out"), 302 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */ 303 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */ 304 SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */ 305 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), 306 SUNXI_FUNCTION(0x0, "gpio_in"), 307 SUNXI_FUNCTION(0x1, "gpio_out"), 308 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ 309 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */ 310 SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */ 311 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), 312 SUNXI_FUNCTION(0x0, "gpio_in"), 313 SUNXI_FUNCTION(0x1, "gpio_out"), 314 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ 315 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */ 316 SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */ 317 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), 318 SUNXI_FUNCTION(0x0, "gpio_in"), 319 SUNXI_FUNCTION(0x1, "gpio_out"), 320 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ 321 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */ 322 SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */ 323 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), 324 SUNXI_FUNCTION(0x0, "gpio_in"), 325 SUNXI_FUNCTION(0x1, "gpio_out"), 326 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ 327 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */ 328 SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */ 329 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), 330 SUNXI_FUNCTION(0x0, "gpio_in"), 331 SUNXI_FUNCTION(0x1, "gpio_out"), 332 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ 333 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */ 334 SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */ 335 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), 336 SUNXI_FUNCTION(0x0, "gpio_in"), 337 SUNXI_FUNCTION(0x1, "gpio_out"), 338 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ 339 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */ 340 SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */ 341 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), 342 SUNXI_FUNCTION(0x0, "gpio_in"), 343 SUNXI_FUNCTION(0x1, "gpio_out"), 344 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ 345 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */ 346 SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */ 347 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), 348 SUNXI_FUNCTION(0x0, "gpio_in"), 349 SUNXI_FUNCTION(0x1, "gpio_out"), 350 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ 351 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */ 352 SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */ 353 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), 354 SUNXI_FUNCTION(0x0, "gpio_in"), 355 SUNXI_FUNCTION(0x1, "gpio_out"), 356 SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */ 357 SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */ 358 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), 359 SUNXI_FUNCTION(0x0, "gpio_in"), 360 SUNXI_FUNCTION(0x1, "gpio_out"), 361 SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */ 362 SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */ 363 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), 364 SUNXI_FUNCTION(0x0, "gpio_in"), 365 SUNXI_FUNCTION(0x1, "gpio_out"), 366 SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */ 367 SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */ 368 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), 369 SUNXI_FUNCTION(0x0, "gpio_in"), 370 SUNXI_FUNCTION(0x1, "gpio_out"), 371 SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */ 372 SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */ 373 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20), 374 SUNXI_FUNCTION(0x0, "gpio_in"), 375 SUNXI_FUNCTION(0x1, "gpio_out"), 376 SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */ 377 SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */ 378 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21), 379 SUNXI_FUNCTION(0x0, "gpio_in"), 380 SUNXI_FUNCTION(0x1, "gpio_out"), 381 SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */ 382 SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */ 383 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22), 384 SUNXI_FUNCTION(0x0, "gpio_in"), 385 SUNXI_FUNCTION(0x1, "gpio_out"), 386 SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */ 387 SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */ 388 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23), 389 SUNXI_FUNCTION(0x0, "gpio_in"), 390 SUNXI_FUNCTION(0x1, "gpio_out"), 391 SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */ 392 SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */ 393 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24), 394 SUNXI_FUNCTION(0x0, "gpio_in"), 395 SUNXI_FUNCTION(0x1, "gpio_out"), 396 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ 397 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */ 398 SUNXI_FUNCTION(0x4, "mmc3")), /* RST */ 399 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25), 400 SUNXI_FUNCTION(0x0, "gpio_in"), 401 SUNXI_FUNCTION(0x1, "gpio_out"), 402 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */ 403 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26), 404 SUNXI_FUNCTION(0x0, "gpio_in"), 405 SUNXI_FUNCTION(0x1, "gpio_out"), 406 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */ 407 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27), 408 SUNXI_FUNCTION(0x0, "gpio_in"), 409 SUNXI_FUNCTION(0x1, "gpio_out"), 410 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ 411 /* Hole */ 412 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), 413 SUNXI_FUNCTION(0x0, "gpio_in"), 414 SUNXI_FUNCTION(0x1, "gpio_out"), 415 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ 416 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ 417 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), 418 SUNXI_FUNCTION(0x0, "gpio_in"), 419 SUNXI_FUNCTION(0x1, "gpio_out"), 420 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ 421 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ 422 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), 423 SUNXI_FUNCTION(0x0, "gpio_in"), 424 SUNXI_FUNCTION(0x1, "gpio_out"), 425 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ 426 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ 427 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), 428 SUNXI_FUNCTION(0x0, "gpio_in"), 429 SUNXI_FUNCTION(0x1, "gpio_out"), 430 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ 431 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ 432 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), 433 SUNXI_FUNCTION(0x0, "gpio_in"), 434 SUNXI_FUNCTION(0x1, "gpio_out"), 435 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ 436 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ 437 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), 438 SUNXI_FUNCTION(0x0, "gpio_in"), 439 SUNXI_FUNCTION(0x1, "gpio_out"), 440 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ 441 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ 442 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), 443 SUNXI_FUNCTION(0x0, "gpio_in"), 444 SUNXI_FUNCTION(0x1, "gpio_out"), 445 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ 446 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ 447 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), 448 SUNXI_FUNCTION(0x0, "gpio_in"), 449 SUNXI_FUNCTION(0x1, "gpio_out"), 450 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ 451 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ 452 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), 453 SUNXI_FUNCTION(0x0, "gpio_in"), 454 SUNXI_FUNCTION(0x1, "gpio_out"), 455 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ 456 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ 457 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), 458 SUNXI_FUNCTION(0x0, "gpio_in"), 459 SUNXI_FUNCTION(0x1, "gpio_out"), 460 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ 461 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */ 462 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), 463 SUNXI_FUNCTION(0x0, "gpio_in"), 464 SUNXI_FUNCTION(0x1, "gpio_out"), 465 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ 466 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ 467 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), 468 SUNXI_FUNCTION(0x0, "gpio_in"), 469 SUNXI_FUNCTION(0x1, "gpio_out"), 470 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ 471 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ 472 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), 473 SUNXI_FUNCTION(0x0, "gpio_in"), 474 SUNXI_FUNCTION(0x1, "gpio_out"), 475 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ 476 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ 477 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), 478 SUNXI_FUNCTION(0x0, "gpio_in"), 479 SUNXI_FUNCTION(0x1, "gpio_out"), 480 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ 481 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ 482 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), 483 SUNXI_FUNCTION(0x0, "gpio_in"), 484 SUNXI_FUNCTION(0x1, "gpio_out"), 485 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ 486 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ 487 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), 488 SUNXI_FUNCTION(0x0, "gpio_in"), 489 SUNXI_FUNCTION(0x1, "gpio_out"), 490 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ 491 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ 492 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), 493 SUNXI_FUNCTION(0x0, "gpio_in"), 494 SUNXI_FUNCTION(0x1, "gpio_out"), 495 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ 496 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ 497 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), 498 SUNXI_FUNCTION(0x0, "gpio_in"), 499 SUNXI_FUNCTION(0x1, "gpio_out"), 500 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ 501 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ 502 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), 503 SUNXI_FUNCTION(0x0, "gpio_in"), 504 SUNXI_FUNCTION(0x1, "gpio_out"), 505 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ 506 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ 507 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), 508 SUNXI_FUNCTION(0x0, "gpio_in"), 509 SUNXI_FUNCTION(0x1, "gpio_out"), 510 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ 511 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ 512 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), 513 SUNXI_FUNCTION(0x0, "gpio_in"), 514 SUNXI_FUNCTION(0x1, "gpio_out"), 515 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ 516 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), 517 SUNXI_FUNCTION(0x0, "gpio_in"), 518 SUNXI_FUNCTION(0x1, "gpio_out"), 519 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ 520 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), 521 SUNXI_FUNCTION(0x0, "gpio_in"), 522 SUNXI_FUNCTION(0x1, "gpio_out"), 523 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ 524 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), 525 SUNXI_FUNCTION(0x0, "gpio_in"), 526 SUNXI_FUNCTION(0x1, "gpio_out"), 527 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ 528 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), 529 SUNXI_FUNCTION(0x0, "gpio_in"), 530 SUNXI_FUNCTION(0x1, "gpio_out"), 531 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ 532 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), 533 SUNXI_FUNCTION(0x0, "gpio_in"), 534 SUNXI_FUNCTION(0x1, "gpio_out"), 535 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ 536 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), 537 SUNXI_FUNCTION(0x0, "gpio_in"), 538 SUNXI_FUNCTION(0x1, "gpio_out"), 539 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ 540 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), 541 SUNXI_FUNCTION(0x0, "gpio_in"), 542 SUNXI_FUNCTION(0x1, "gpio_out"), 543 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ 544 /* Hole */ 545 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), 546 SUNXI_FUNCTION(0x0, "gpio_in"), 547 SUNXI_FUNCTION(0x1, "gpio_out"), 548 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ 549 SUNXI_FUNCTION(0x3, "ts"), /* CLK */ 550 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */ 551 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), 552 SUNXI_FUNCTION(0x0, "gpio_in"), 553 SUNXI_FUNCTION(0x1, "gpio_out"), 554 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ 555 SUNXI_FUNCTION(0x3, "ts"), /* ERR */ 556 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */ 557 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), 558 SUNXI_FUNCTION(0x0, "gpio_in"), 559 SUNXI_FUNCTION(0x1, "gpio_out"), 560 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ 561 SUNXI_FUNCTION(0x3, "ts"), /* SYNC */ 562 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */ 563 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), 564 SUNXI_FUNCTION(0x0, "gpio_in"), 565 SUNXI_FUNCTION(0x1, "gpio_out"), 566 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ 567 SUNXI_FUNCTION(0x3, "ts"), /* DVLD */ 568 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */ 569 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), 570 SUNXI_FUNCTION(0x0, "gpio_in"), 571 SUNXI_FUNCTION(0x1, "gpio_out"), 572 SUNXI_FUNCTION(0x2, "csi"), /* D0 */ 573 SUNXI_FUNCTION(0x3, "uart5"), /* TX */ 574 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */ 575 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), 576 SUNXI_FUNCTION(0x0, "gpio_in"), 577 SUNXI_FUNCTION(0x1, "gpio_out"), 578 SUNXI_FUNCTION(0x2, "csi"), /* D1 */ 579 SUNXI_FUNCTION(0x3, "uart5"), /* RX */ 580 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */ 581 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), 582 SUNXI_FUNCTION(0x0, "gpio_in"), 583 SUNXI_FUNCTION(0x1, "gpio_out"), 584 SUNXI_FUNCTION(0x2, "csi"), /* D2 */ 585 SUNXI_FUNCTION(0x3, "uart5"), /* RTS */ 586 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */ 587 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), 588 SUNXI_FUNCTION(0x0, "gpio_in"), 589 SUNXI_FUNCTION(0x1, "gpio_out"), 590 SUNXI_FUNCTION(0x2, "csi"), /* D3 */ 591 SUNXI_FUNCTION(0x3, "uart5"), /* CTS */ 592 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */ 593 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), 594 SUNXI_FUNCTION(0x0, "gpio_in"), 595 SUNXI_FUNCTION(0x1, "gpio_out"), 596 SUNXI_FUNCTION(0x2, "csi"), /* D4 */ 597 SUNXI_FUNCTION(0x3, "ts"), /* D0 */ 598 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */ 599 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), 600 SUNXI_FUNCTION(0x0, "gpio_in"), 601 SUNXI_FUNCTION(0x1, "gpio_out"), 602 SUNXI_FUNCTION(0x2, "csi"), /* D5 */ 603 SUNXI_FUNCTION(0x3, "ts"), /* D1 */ 604 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */ 605 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), 606 SUNXI_FUNCTION(0x0, "gpio_in"), 607 SUNXI_FUNCTION(0x1, "gpio_out"), 608 SUNXI_FUNCTION(0x2, "csi"), /* D6 */ 609 SUNXI_FUNCTION(0x3, "ts"), /* D2 */ 610 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */ 611 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), 612 SUNXI_FUNCTION(0x0, "gpio_in"), 613 SUNXI_FUNCTION(0x1, "gpio_out"), 614 SUNXI_FUNCTION(0x2, "csi"), /* D7 */ 615 SUNXI_FUNCTION(0x3, "ts"), /* D3 */ 616 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */ 617 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), 618 SUNXI_FUNCTION(0x0, "gpio_in"), 619 SUNXI_FUNCTION(0x1, "gpio_out"), 620 SUNXI_FUNCTION(0x2, "csi"), /* D8 */ 621 SUNXI_FUNCTION(0x3, "ts"), /* D4 */ 622 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */ 623 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), 624 SUNXI_FUNCTION(0x0, "gpio_in"), 625 SUNXI_FUNCTION(0x1, "gpio_out"), 626 SUNXI_FUNCTION(0x2, "csi"), /* D9 */ 627 SUNXI_FUNCTION(0x3, "ts"), /* D5 */ 628 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */ 629 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), 630 SUNXI_FUNCTION(0x0, "gpio_in"), 631 SUNXI_FUNCTION(0x1, "gpio_out"), 632 SUNXI_FUNCTION(0x2, "csi"), /* D10 */ 633 SUNXI_FUNCTION(0x3, "ts"), /* D6 */ 634 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */ 635 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), 636 SUNXI_FUNCTION(0x0, "gpio_in"), 637 SUNXI_FUNCTION(0x1, "gpio_out"), 638 SUNXI_FUNCTION(0x2, "csi"), /* D11 */ 639 SUNXI_FUNCTION(0x3, "ts"), /* D7 */ 640 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */ 641 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), 642 SUNXI_FUNCTION(0x0, "gpio_in"), 643 SUNXI_FUNCTION(0x1, "gpio_out"), 644 SUNXI_FUNCTION(0x2, "csi"), /* MIPI CSI MCLK */ 645 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */ 646 /* Hole */ 647 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 648 SUNXI_FUNCTION(0x0, "gpio_in"), 649 SUNXI_FUNCTION(0x1, "gpio_out"), 650 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 651 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */ 652 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), 653 SUNXI_FUNCTION(0x0, "gpio_in"), 654 SUNXI_FUNCTION(0x1, "gpio_out"), 655 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 656 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ 657 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), 658 SUNXI_FUNCTION(0x0, "gpio_in"), 659 SUNXI_FUNCTION(0x1, "gpio_out"), 660 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 661 SUNXI_FUNCTION(0x4, "uart0")), /* TX */ 662 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), 663 SUNXI_FUNCTION(0x0, "gpio_in"), 664 SUNXI_FUNCTION(0x1, "gpio_out"), 665 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 666 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ 667 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), 668 SUNXI_FUNCTION(0x0, "gpio_in"), 669 SUNXI_FUNCTION(0x1, "gpio_out"), 670 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 671 SUNXI_FUNCTION(0x4, "uart0")), /* RX */ 672 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), 673 SUNXI_FUNCTION(0x0, "gpio_in"), 674 SUNXI_FUNCTION(0x1, "gpio_out"), 675 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 676 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ 677 /* Hole */ 678 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 679 SUNXI_FUNCTION(0x0, "gpio_in"), 680 SUNXI_FUNCTION(0x1, "gpio_out"), 681 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 682 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */ 683 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 684 SUNXI_FUNCTION(0x0, "gpio_in"), 685 SUNXI_FUNCTION(0x1, "gpio_out"), 686 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 687 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */ 688 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 689 SUNXI_FUNCTION(0x0, "gpio_in"), 690 SUNXI_FUNCTION(0x1, "gpio_out"), 691 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ 692 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */ 693 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 694 SUNXI_FUNCTION(0x0, "gpio_in"), 695 SUNXI_FUNCTION(0x1, "gpio_out"), 696 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ 697 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */ 698 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), 699 SUNXI_FUNCTION(0x0, "gpio_in"), 700 SUNXI_FUNCTION(0x1, "gpio_out"), 701 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ 702 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */ 703 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), 704 SUNXI_FUNCTION(0x0, "gpio_in"), 705 SUNXI_FUNCTION(0x1, "gpio_out"), 706 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ 707 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */ 708 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), 709 SUNXI_FUNCTION(0x0, "gpio_in"), 710 SUNXI_FUNCTION(0x1, "gpio_out"), 711 SUNXI_FUNCTION(0x2, "uart2"), /* TX */ 712 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */ 713 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), 714 SUNXI_FUNCTION(0x0, "gpio_in"), 715 SUNXI_FUNCTION(0x1, "gpio_out"), 716 SUNXI_FUNCTION(0x2, "uart2"), /* RX */ 717 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */ 718 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), 719 SUNXI_FUNCTION(0x0, "gpio_in"), 720 SUNXI_FUNCTION(0x1, "gpio_out"), 721 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ 722 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */ 723 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), 724 SUNXI_FUNCTION(0x0, "gpio_in"), 725 SUNXI_FUNCTION(0x1, "gpio_out"), 726 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ 727 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */ 728 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), 729 SUNXI_FUNCTION(0x0, "gpio_in"), 730 SUNXI_FUNCTION(0x1, "gpio_out"), 731 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ 732 SUNXI_FUNCTION(0x3, "usb"), /* DP3 */ 733 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */ 734 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), 735 SUNXI_FUNCTION(0x0, "gpio_in"), 736 SUNXI_FUNCTION(0x1, "gpio_out"), 737 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ 738 SUNXI_FUNCTION(0x3, "usb"), /* DM3 */ 739 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */ 740 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), 741 SUNXI_FUNCTION(0x0, "gpio_in"), 742 SUNXI_FUNCTION(0x1, "gpio_out"), 743 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ 744 SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */ 745 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */ 746 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), 747 SUNXI_FUNCTION(0x0, "gpio_in"), 748 SUNXI_FUNCTION(0x1, "gpio_out"), 749 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 750 SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */ 751 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */ 752 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), 753 SUNXI_FUNCTION(0x0, "gpio_in"), 754 SUNXI_FUNCTION(0x1, "gpio_out"), 755 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 756 SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */ 757 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */ 758 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15), 759 SUNXI_FUNCTION(0x0, "gpio_in"), 760 SUNXI_FUNCTION(0x1, "gpio_out"), 761 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 762 SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */ 763 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */ 764 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16), 765 SUNXI_FUNCTION(0x0, "gpio_in"), 766 SUNXI_FUNCTION(0x1, "gpio_out"), 767 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 768 SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */ 769 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */ 770 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17), 771 SUNXI_FUNCTION(0x0, "gpio_in"), 772 SUNXI_FUNCTION(0x1, "gpio_out"), 773 SUNXI_FUNCTION(0x2, "uart4"), /* TX */ 774 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */ 775 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18), 776 SUNXI_FUNCTION(0x0, "gpio_in"), 777 SUNXI_FUNCTION(0x1, "gpio_out"), 778 SUNXI_FUNCTION(0x2, "uart4"), /* RX */ 779 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */ 780 /* Hole */ 781 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), 782 SUNXI_FUNCTION(0x0, "gpio_in"), 783 SUNXI_FUNCTION(0x1, "gpio_out"), 784 SUNXI_FUNCTION(0x2, "nand1")), /* WE */ 785 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), 786 SUNXI_FUNCTION(0x0, "gpio_in"), 787 SUNXI_FUNCTION(0x1, "gpio_out"), 788 SUNXI_FUNCTION(0x2, "nand1")), /* ALE */ 789 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), 790 SUNXI_FUNCTION(0x0, "gpio_in"), 791 SUNXI_FUNCTION(0x1, "gpio_out"), 792 SUNXI_FUNCTION(0x2, "nand1")), /* CLE */ 793 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), 794 SUNXI_FUNCTION(0x0, "gpio_in"), 795 SUNXI_FUNCTION(0x1, "gpio_out"), 796 SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */ 797 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), 798 SUNXI_FUNCTION(0x0, "gpio_in"), 799 SUNXI_FUNCTION(0x1, "gpio_out"), 800 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */ 801 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), 802 SUNXI_FUNCTION(0x0, "gpio_in"), 803 SUNXI_FUNCTION(0x1, "gpio_out"), 804 SUNXI_FUNCTION(0x2, "nand1")), /* RE */ 805 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), 806 SUNXI_FUNCTION(0x0, "gpio_in"), 807 SUNXI_FUNCTION(0x1, "gpio_out"), 808 SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */ 809 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), 810 SUNXI_FUNCTION(0x0, "gpio_in"), 811 SUNXI_FUNCTION(0x1, "gpio_out"), 812 SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */ 813 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), 814 SUNXI_FUNCTION(0x0, "gpio_in"), 815 SUNXI_FUNCTION(0x1, "gpio_out"), 816 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */ 817 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), 818 SUNXI_FUNCTION(0x0, "gpio_in"), 819 SUNXI_FUNCTION(0x1, "gpio_out"), 820 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ 821 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ 822 SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */ 823 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), 824 SUNXI_FUNCTION(0x0, "gpio_in"), 825 SUNXI_FUNCTION(0x1, "gpio_out"), 826 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ 827 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ 828 SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */ 829 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), 830 SUNXI_FUNCTION(0x0, "gpio_in"), 831 SUNXI_FUNCTION(0x1, "gpio_out"), 832 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ 833 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ 834 SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */ 835 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12), 836 SUNXI_FUNCTION(0x0, "gpio_in"), 837 SUNXI_FUNCTION(0x1, "gpio_out"), 838 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ 839 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ 840 SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */ 841 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13), 842 SUNXI_FUNCTION(0x0, "gpio_in"), 843 SUNXI_FUNCTION(0x1, "gpio_out"), 844 SUNXI_FUNCTION(0x2, "pwm0")), 845 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14), 846 SUNXI_FUNCTION(0x0, "gpio_in"), 847 SUNXI_FUNCTION(0x1, "gpio_out"), 848 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ 849 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15), 850 SUNXI_FUNCTION(0x0, "gpio_in"), 851 SUNXI_FUNCTION(0x1, "gpio_out"), 852 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ 853 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16), 854 SUNXI_FUNCTION(0x0, "gpio_in"), 855 SUNXI_FUNCTION(0x1, "gpio_out"), 856 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ 857 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17), 858 SUNXI_FUNCTION(0x0, "gpio_in"), 859 SUNXI_FUNCTION(0x1, "gpio_out"), 860 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ 861 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18), 862 SUNXI_FUNCTION(0x0, "gpio_in"), 863 SUNXI_FUNCTION(0x1, "gpio_out"), 864 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ 865 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19), 866 SUNXI_FUNCTION(0x0, "gpio_in"), 867 SUNXI_FUNCTION(0x1, "gpio_out"), 868 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ 869 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20), 870 SUNXI_FUNCTION(0x0, "gpio_in"), 871 SUNXI_FUNCTION(0x1, "gpio_out"), 872 SUNXI_FUNCTION(0x2, "uart0")), /* TX */ 873 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21), 874 SUNXI_FUNCTION(0x0, "gpio_in"), 875 SUNXI_FUNCTION(0x1, "gpio_out"), 876 SUNXI_FUNCTION(0x2, "uart0")), /* RX */ 877 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22), 878 SUNXI_FUNCTION(0x0, "gpio_in"), 879 SUNXI_FUNCTION(0x1, "gpio_out")), 880 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23), 881 SUNXI_FUNCTION(0x0, "gpio_in"), 882 SUNXI_FUNCTION(0x1, "gpio_out")), 883 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24), 884 SUNXI_FUNCTION(0x0, "gpio_in"), 885 SUNXI_FUNCTION(0x1, "gpio_out")), 886 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25), 887 SUNXI_FUNCTION(0x0, "gpio_in"), 888 SUNXI_FUNCTION(0x1, "gpio_out")), 889 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26), 890 SUNXI_FUNCTION(0x0, "gpio_in"), 891 SUNXI_FUNCTION(0x1, "gpio_out")), 892 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27), 893 SUNXI_FUNCTION(0x0, "gpio_in"), 894 SUNXI_FUNCTION(0x1, "gpio_out")), 895 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28), 896 SUNXI_FUNCTION(0x0, "gpio_in"), 897 SUNXI_FUNCTION(0x1, "gpio_out")), 898 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 29), 899 SUNXI_FUNCTION(0x0, "gpio_in"), 900 SUNXI_FUNCTION(0x1, "gpio_out"), 901 SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */ 902 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 30), 903 SUNXI_FUNCTION(0x0, "gpio_in"), 904 SUNXI_FUNCTION(0x1, "gpio_out"), 905 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */ 906 }; 907 908 static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = { 909 .pins = sun6i_a31_pins, 910 .npins = ARRAY_SIZE(sun6i_a31_pins), 911 .irq_banks = 4, 912 }; 913 914 static int sun6i_a31_pinctrl_probe(struct platform_device *pdev) 915 { 916 return sunxi_pinctrl_init(pdev, 917 &sun6i_a31_pinctrl_data); 918 } 919 920 static struct of_device_id sun6i_a31_pinctrl_match[] = { 921 { .compatible = "allwinner,sun6i-a31-pinctrl", }, 922 {} 923 }; 924 MODULE_DEVICE_TABLE(of, sun6i_a31_pinctrl_match); 925 926 static struct platform_driver sun6i_a31_pinctrl_driver = { 927 .probe = sun6i_a31_pinctrl_probe, 928 .driver = { 929 .name = "sun6i-a31-pinctrl", 930 .of_match_table = sun6i_a31_pinctrl_match, 931 }, 932 }; 933 module_platform_driver(sun6i_a31_pinctrl_driver); 934 935 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); 936 MODULE_DESCRIPTION("Allwinner A31 pinctrl driver"); 937 MODULE_LICENSE("GPL"); 938